METHOD FOR PRODUCING SEMICONDUCTOR CAPACITORS HAVING DIFFERENT CAPACITANCE VALUES IN A SEMICONDUCTOR SUBSTRATE

Abstract

In a method for producing semiconductor capacitors having different capacitance values on a common substrate, firstly a partially processed semiconductor substrate is produced as a semi-finished product with hole structures and filled with a layer sequence of a dielectric and an electrically conductive layerindependently of the semiconductor capacitors to be produced subsequently. The production of the semiconductor capacitors having different capacitance values only then takes place in a second production phase by corresponding metallization and structuring. The semiconductor capacitors are then separated along dividing regions through which different groups of holes are separated from one another during the production of the semi-finished product. The method enables a more cost-effective production of semiconductor capacitors having different capacitance values in small numbers of items in make-to-order fabrication (foundry process).

Claims

1. A method for producing semiconductor capacitors having different capacitance values in a semiconductor substrate in which in a first production phase independently of the semiconductor capacitors to be produced in the semiconductor substrate: a hole structure comprising several groups of holes is produced in the semiconductor substrate, which groups are distributed over the semiconductor substrate and in each case are separated from one another by means of identifiable dividing regions having a width which is greater than the spacing of the holes within the groups and the hole structure is filled with a layer sequence of a dielectric and an electrically conductive layer as upper electrode of the semiconductor capacitor to be produced, wherein the layer sequence also extends between the holes and groups and each of the groups forms a first capacitance and in a second production phase depending on the semiconductor capacitors to be produced in the semiconductor substrate: different subregions of the semiconductor substrate are specified in which semiconductor capacitors having identical capacitance values are produced in each case, wherein the capacitance values of the semiconductor capacitors of the various subregions differ, the layer sequence is structured and a metallization is applied structured or is applied and then structured, wherein the structuring and the application of the metallization are accomplished so that within each subregion the semiconductor capacitors are formed depending on the desired capacitance values either in each case by one of the first capacitances or by electric parallel connection of several of the first capacitances and the semiconductor capacitors of each subregion are separated by separating the semiconductor substrate along dividing lines which run within the dividing regions.

2. The method according to claim 1, characterized in that the dividing regions extend rectilinearly over the entire semiconductor substrate.

3. The method according to claim 1, characterized in that in the first production phase further hole structures are also produced in the dividing regions.

4. The method according to claim 1, characterized in that in the first or second production phase a metallization is applied to the semiconductor substrate on the back side.

5. The method according to claim 1, characterized in that before the separation of the semiconductor capacitors, the semiconductor substrate is connected to a second semiconductor substrate, which has a lower sheet resistance than the semiconductor substrate due to a lower doping so that RC members are obtained by the separation.

6. The method according to claim 1, characterized in that before separation of the semiconductor capacitors the semiconductor substrate is provided with a backside layer or layer sequence which has a lower sheet resistance than the semiconductor substrate so that RC members are obtained by the separation.

7. The method according to claim 5, characterized in that in the second production phase a metallization is applied to the second semiconductor substrate on the back side or to the backside layer.

8. The method according to claim 6, characterized in that in the second production phase a metallization is applied to the backside layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The proposed method is explained once again hereinafter with reference to exemplary embodiments in conjunction with the drawings. In the figures:

[0013] FIG. 1 shows an example for the construction of a semiconductor capacitor such as can be produced with the proposed method;

[0014] FIG. 2 shows a schematic diagram of a distribution of the groups of holes over the semiconductor substrate according to the proposed method;

[0015] FIG. 3 shows an enlarged view of a section from FIG. 2 according to a first embodiment;

[0016] FIG. 4 shows an enlarged view of a section from FIG. 2 according to a second embodiment; and

[0017] FIG. 5 shows a highly schematic view of the connection to a second semiconductor substrate to produce RC snubber members.

WAYS FOR IMPLEMENTING THE INVENTION

[0018] With the proposed method, semiconductor capacitors, in particular silicon capacitors, having different electrical characteristics can be produced on a common semiconductor substrate, wherein in a first production phase a partially processed semiconductor substrate is produced as semi-finished product, which is constructed independently of the different electrical characteristics or capacitance values of the semiconductor capacitors to be produced. Using the method, for example, semiconductor capacitors can be produced, as shown for example in FIG. 1 or also RC snubber members comprising such semiconductor capacitors.

[0019] FIG. 1 shows a section of a semiconductor substrate 4 in cross-section, in the surface of which a hole structure with holes 5 is etched, which serve as the basis for the capacitor to be produced. The semiconductor substrate 4 has a high doping, for example, a boron doping, of at least 5*10.sup.18 cm.sup.3 and therefore a low ESR (equivalent series resistance). The holes 5 can be produced by known mask and etching technology. The holes 5 are then filled with a layer sequence of a dielectric 6 and a metal 7 which forms the upper electrode of the capacitor. This is followed by the deposition of an insulating layer 8 and a further metallization 9 which is used for the front-side contacting of the semiconductor capacitor. The backside of the semiconductor substrate 4 can also be provided with a corresponding metallization. The capacitance value of the semiconductor capacitor produced in this way in this case depends inter alia on the number of holes 5 or the area size of the hole structure. Hitherto, a usual chip fabrication method has been used to produce such semiconductor capacitors, in which the definition of the mask design for the capacitors to be produced is specified before the beginning of fabrication so that the capacitance values of the individual capacitors must also be known before the beginning of fabrication.

[0020] With the present method, the specification before the beginning of the production process is no longer necessary. On the contrary, semi-finished products can be produced in large numbers initially with exactly the same structures. The fabrication of semiconductor capacitors having different capacitance values then takes place on the same semiconductor substrate using these semi-finished products.

[0021] For this purpose, in the proposed method in a first production phase in which the semi-finished product is produced, a hole structure with holes is produced in the semiconductor substrate which extend over the entire semiconductor substrate. In the proposed method these holes are produced in separate groups using a mask and etching technique in the semiconductor substrate, wherein after the subsequent deposition of a layer sequence of dielectric and metal, each group forms a capacitance, here designated as first capacitance to distinguish with respect to the capacitance of the semiconductor capacitor to be produced.

[0022] FIG. 2 shows to this end in highly schematic view a plan view of a section of the semiconductor substrate 4, in which the individual groups 1 of holes occupy an approximately square area and are indicated by the small squares in the figure. The groups 1 of holes can also be approximated by different geometrical shapes, for example, rectangles or triangles. It can also be seen from FIG. 2 that dividing regions 2 are provided between the individual groups 1, which separate the individual groups 1 from one another and subsequently serve as dicing streets during the separation of the semiconductor capacitors. Following the production of the hole structure, a layer sequence of a dielectric and a metal is deposited on the semiconductor substrate by means of which the holes are filled in the known manner. This layer sequence is applied over the entire semiconductor substrate 4, i.e. over the dividing regions 2 between the individual groups 1, i.e. independently of the capacitance values of the capacitors to be produced subsequently.

[0023] Using the partially processed semiconductor substrate obtained in this way, also designated in the present patent application as semi-finished product, the second production phase is then carried out in which the individual semiconductor capacitors with the desired capacitance values are obtained. To this end, subregions 3 are specified within which a number of semiconductor capacitors having identical capacitance values is to be produced in each case. The size of these subregions 3 depends on the number and the capacitance values of the semiconductor capacitors to be produced. In FIG. 2 such a subregion 3 is only indicated schematically. Other subregions then in turn relate to semiconductor capacitors having different capacitance values. In the respective subregions 3, semiconductor capacitors which have the required number of groups 1 of holes for the desired capacitance are then produced in the second production phase by metallization and structuring. To this end, the individual first capacitances of the groups 1 of holes are switched in parallel in suitable number by the structuring and metallization. This requires a mask design matched to the respective capacitance value. This is then followed by the separation of the individual capacitors in the corresponding subregion 3 along the dividing regions 2.

[0024] To this end, FIG. 3 again shows an enlarged view of a section from FIG. 2 in which the individual holes 5 of the groups 1 can be identified. The dividing regions 2 between hole structures 1 here have no holes.

[0025] In a further embodiment however, corresponding recesses or holes can also be produced in the dividing regions 2, as shown schematically in FIG. 4. The holes 10 in these dividing regions 2 are arranged in this example as a result of a correspondingly enlarged distance from the groups 1 of holes 5 such that the individual dividing regions 2 and groups 1 of holes can still be identified. As a result of these additional holes 10 in the dividing regions 2, a stress migration is achieved so that when applying thicker layers to the semiconductor substrate, stresses between the layers and the semiconductor substrate are reduced in this region.

[0026] As a result of the hole structuring and the filling with a dielectric and a metal as upper electrode in the first production phase with a fixedly defined mask design which is independent of the semiconductor capacitors to be produced subsequently, the semi-finished product can be produced cost-effectively in a large quantity regardless of the semiconductor capacitors to be produced. The individualization or production of the semiconductor capacitors having different capacitance values is then only accomplished in the second production phase. In this second production phase, the dielectric and/or the upper electrode are structured and a metallization is produced over a part of the individual regions or groups in order to form the semiconductor capacitors with the corresponding capacitance values. This is then accomplished with an individually defined mask design in each case.

[0027] As a result of the parallel wiring of the hole structures of several of the groups 1, most diverse capacitance values can thus be obtained. Thus, for example, the semi-finished product can be produced by processing on a low-resistance p-substrate. The dimensioning of the area of the groups 1 can be accomplished in this case, for example so that if an area of each group 1 is 0.5 mm.sup.2 and a first capacitance value of this group is 250 pF, capacitance values C of 1 to 10 nF can be obtained by parallel wiring of several of the groups. This is shown in the following table which shows the total area A and the total numbers of the parallel-wired groups 1 in each case.

TABLE-US-00001 C in nF 1 1.5 3.0 4.5 5.0 5.5 10 A in mm.sup.2 2 3 6 9 10 12 20 Number of 4 6 12 18 20 24 40 groups

[0028] The proposed method is also suitable for producing RC snubber members. In this case, in addition to the semiconductor capacitors, the corresponding resistance must also be produced. This can be accomplished in the proposed method by bonding the semiconductor substrate 4 with the hole structures before separating into the individual components onto a lower-doped semiconductor substrate 11, as is shown highly schematically in FIG. 5. In this figure, the region with the hole structures is merely shown hatched. The doping of this second semiconductor substrate is selected in this case so that the desired resistance value is achieved. The following table shows examples of the serial resistance R.sub.ESR for various second substrates (e.g. 400 m thick) with different resistivity p at 5 nF/10 mm.sup.2. The first value corresponds to the conditions without a second substrate (only capacitor).

TABLE-US-00002 in cm 0 0.5 1.0 3.0 10 30 100 R.sub.ESR in 0.1 0.3 0.5 1.3 4.1 12 40

[0029] A further possibility for producing RC snubber members consists in depositing a poorly conductive layerdepending on the required series resistanceon the rear side of the semiconductor substrate before separating into the individual components. Here it is also possible to select the temperature dependence of the resistance in a targeted manner or deposit a multilayer system for compensation of the temperature dependence. Examples of suitable layer materials are ceramics, metal layers, amorphous silicon etc. with high thermal conductivity. The following table here again gives examples of the serial resistance R.sub.ESR for various layers (e.g. 4 m thick) having different resistivity at 5 nF/10 mm.sup.2. The first value again corresponds to the conditions without the additional resistance layer (only capacitor).

TABLE-US-00003 in cm 0 50 100 300 1k 3k 10k R.sub.ESR in 0.1 0.3 0.5 1.3 4.1 12 40

REFERENCE LIST

[0030] 1 Group of holes [0031] 2 Dividing regions [0032] 3 Subregions [0033] 4 Semiconductor substrate [0034] 5 Holes [0035] 6 Dielectric [0036] 7 Metal [0037] 8 Insulation layer [0038] 9 Metallization [0039] 10 Further holes [0040] 11 Second semiconductor substrate