COPPER/CERAMIC JOINED BODY AND INSULATED CIRCUIT BOARD

Abstract

According to the present invention, there is provided a copper/ceramic bonded body including: a copper member made of copper or a copper alloy; and a ceramic member made of silicon-containing ceramics, the copper member and the ceramic member being bonded to each other, in which a maximum indentation hardness in a region is set to be in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less, the region being from 10 μm to 50 μm with reference to a bonded interface between the copper member and the ceramic member toward the copper member side.

Claims

1. A copper/ceramic bonded body comprising: a copper member made of copper or a copper alloy; and a ceramic member made of silicon-containing ceramics, the copper member and the ceramic member being bonded to each other, wherein a maximum indentation hardness in a region is set to be in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less, the region being from 10 μm to 50 μm with reference to a bonded interface between the copper member and the ceramic member toward the copper member side.

2. The copper/ceramic bonded body according to claim 1, wherein, at the bonded interface between the ceramic member and the copper member, an active metal compound layer containing a compound of one or more active metals selected from the group consisting of Ti, Zr, Nb, and Hf is formed on the ceramic member side, and a maximum particle size of particles of the active metal compound in the active metal compound layer is 180 nm or less.

3. The copper/ceramic bonded body according to claim 1, wherein Si, Cu, and Ag are present in the active metal compound layer.

4. An insulating circuit substrate comprising: a copper sheet made of copper or a copper alloy; and a ceramic substrate made of silicon-containing ceramics, the copper sheet being bonded to a surface of the ceramic substrate, wherein a maximum indentation hardness in a region is set to be in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less, the region being from 10 μm to 50 μm with reference to a bonded interface between the copper sheet and the ceramic substrate toward the copper sheet side.

5. The insulating circuit substrate according to claim 4, wherein, at the bonded interface between the copper sheet and the ceramic substrate, an active metal compound layer containing a compound of one or more active metals selected from the group consisting of Ti, Zr, Nb, and Hf is formed on the ceramic substrate side, and a maximum particle size of particles of the active metal compound in the active metal compound layer is 180 nm or less.

6. The insulating circuit substrate according to claim 4, wherein Si, Cu, and Ag are present in the active metal compound layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0034] FIG. 1 is a schematic explanatory view of a power module using an insulating circuit substrate according to an embodiment of the present invention.

[0035] FIG. 2 is an enlarged explanatory view of a bonded interface between a circuit layer (metal layer) and a ceramic substrate of the insulating circuit substrate according to the embodiment of the present invention.

[0036] FIG. 3 is an observation photograph of an active metal compound layer formed at the bonded interface between the circuit layer (metal layer) and the ceramic substrate of the insulating circuit substrate according to the embodiment of the present invention.

[0037] FIG. 4 is an example of an EDS spectrum of the active metal compound layer.

[0038] FIG. 5 is a flowchart of a production method of the insulating circuit substrate according to the embodiment of the present invention.

[0039] FIG. 6 is a schematic explanatory view of the production method of the insulating circuit substrate according to the embodiment of the present invention.

[0040] FIG. 7 is an explanatory view showing a measurement point of the maximum indentation hardness in the vicinity of a bonded interface in Examples.

[0041] FIG. 8 is an explanatory view showing a measurement principle of an indentation hardness test in Examples.

DESCRIPTION OF EMBODIMENTS

[0042] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0043] A copper/ceramic bonded body according to the present embodiment is an insulating circuit substrate 10 formed by bonding a ceramic substrate 11 as a ceramic member made of ceramics to a copper sheet 22 (circuit layer 12) and a copper sheet 23 (metal layer 13) as a copper member made of copper or a copper alloy. FIG. 1 shows a power module 1 including the insulating circuit substrate 10 according to the present embodiment.

[0044] The power module 1 includes the insulating circuit substrate 10 on which the circuit layer 12 and the metal layer 13 are disposed, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 with a bonding layer 2 interposed therebetween, and a heat sink 30 disposed on the other side (lower side in FIG. 1) of the metal layer 13.

[0045] The semiconductor element 3 is made of a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded to each other with the bonding layer 2 interposed therebetween.

[0046] The bonding layer 2 is made of, for example, a Sn—Ag-based, Sn—In-based, or Sn—Ag—Cu-based solder material.

[0047] The heat sink 30 dissipates heat from the above-mentioned insulating circuit substrate 10. The heat sink 30 is made of copper or a copper alloy, and in the present embodiment, the heat sink 30 is made of phosphorus deoxidized copper. The heat sink 30 is provided with a passage 31 through which a cooling fluid flows.

[0048] In the present embodiment, the heat sink 30 and the metal layer 13 are bonded to each other by a solder layer 32 made of a solder material. The solder layer 32 is made of, for example, a Sn—Ag-based, Sn—In-based, or Sn—Ag—Cu-based solder material.

[0049] As shown in FIG. 1, the insulating circuit substrate 10 according to the present embodiment includes the ceramic substrate 11, the circuit layer 12 disposed on one surface (upper surface in FIG. 1) of the ceramic substrate 11, and the metal layer 13 disposed on the other surface (lower surface in FIG. 1) of the ceramic substrate 11.

[0050] The ceramic substrate 11 is made of silicon-containing ceramics having excellent insulating properties and heat radiation, and in the present embodiment, the ceramic substrate 11 is made of silicon nitride (Si.sub.3N.sub.4). The thickness of the ceramic substrate 11 is set to be in a range of, for example, 0.2 mm or more and 1.5 mm or less, and in the present embodiment, the thickness is set to 0.32 mm.

[0051] As shown in FIG. 6, the circuit layer 12 is formed by bonding the copper sheet 22 made of copper or a copper alloy to one surface (upper surface in FIG. 6) of the ceramic substrate 11.

[0052] In the present embodiment, the circuit layer 12 is formed by bonding the copper sheet 22 made of a rolled plate of oxygen-free copper to the ceramic substrate 11.

[0053] The thickness of the copper sheet 22 serving as the circuit layer 12 is set to be in a range of 0.1 mm or more and 2.0 mm or less, and in the present embodiment, the thickness is set to 0.6 mm.

[0054] As shown in FIG. 6, the metal layer 13 is formed by bonding the copper sheet 23 made of copper or a copper alloy to the other surface (lower surface in FIG. 6) of the ceramic substrate 11.

[0055] In the present embodiment, the metal layer 13 is formed by bonding the copper sheet 23 made of a rolled plate of oxygen-free copper to the ceramic substrate 11.

[0056] The thickness of the copper sheet 23 serving as the metal layer 13 is set to be in a range of 0.1 mm or more and 2.0 mm or less, and in the present embodiment, the thickness is set to 0.6 mm.

[0057] At the bonded interface between the ceramic substrate 11 and the circuit layer 12 (metal layer 13), as shown in FIG. 2, an active metal compound layer 41 containing a compound of one or more active metals selected from the group consisting of Ti, Zr, Nb, and Hf is formed.

[0058] The active metal compound layer 41 is formed by reacting an active metal contained in a bonding material with the ceramic substrate 11.

[0059] In the present embodiment, Ti is used as the active metal and the ceramic substrate 11 is made of aluminum nitride, so that the active metal compound layer 41 becomes a titanium nitride (TiN) layer.

[0060] In the insulating circuit substrate 10 according to the present embodiment, the maximum indentation hardness in a region from 10 μm to 50 μm from the bonded interface between the circuit layer 12 (metal layer 13) and the ceramic substrate 11 to the circuit layer 12 (metal layer 13) side is in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less.

[0061] The lower limit of the maximum indentation hardness is preferably 75 mgf/μm.sup.2 or more, and more preferably 85 mgf/μm.sup.2 or more. On the other hand, the upper limit of the maximum indentation hardness is preferably 135 mgf/μm.sup.2 or less, and more preferably 125 mgf/μm.sup.2 or less.

[0062] In the insulating circuit substrate 10 according to the present embodiment, as shown in FIG. 3, it is preferable that the maximum particle size of active metal compound particles 45 in the active metal compound layer 41 is 180 nm or less. Grain boundaries between the active metal compound particles 45 form a metal phase. Since the maximum particle size of the active metal compound particles 45 is 180 nm or less, a proportion of a metal phase having a relatively low hardness increases, and impact resistance of the active metal compound layer 41 is improved. As a result, for example, when a terminal material is ultrasonically bonded to the copper member, it is possible to suppress the generation of cracks in the active metal compound layer 41, and to suppress peeling of the copper member from the ceramic member and the generation of cracks in the ceramic member.

[0063] The maximum particle size of the active metal compound particles 45 in the active metal compound layer 41 is more preferably 150 nm or less, and still more preferably 120 nm or less.

[0064] Further, in the insulating circuit substrate 10 according to the present embodiment, it is preferable that Si, Cu, and Ag are present in the active metal compound layer 41.

[0065] Si, Cu, and Ag present in the active metal compound layer 41 can be confirmed by observing the interparticles and the grain boundaries of the active metal compound particles 45 in the active metal compound layer 41 using a transmission electron microscope and obtaining an EDS spectrum. An example of the EDS spectrum of the active metal compound layer 41 is shown in FIG. 4. Peaks of Si, Cu, and Ag are confirmed, and it can be seen that Si, Cu, and Ag are present in the active metal compound layer 41.

[0066] Hereinafter, a production method of the insulating circuit substrate 10 according to the present embodiment will be described with reference to FIGS. 5 and 6.

[0067] (Laminating Step S01)

[0068] First, the ceramic substrate 11 made of silicon nitride (Si.sub.3N.sub.4) is prepared, and as shown in FIG. 6, an Ag—Ti-based brazing material (Ag—Cu—Ti-based brazing material) 24 is disposed between the copper sheet 22 serving as the circuit layer 12 and the ceramic substrate 11, and between the copper sheet 23 serving as the metal layer 13 and the ceramic substrate 11.

[0069] As the Ag—Ti-based brazing material (Ag—Cu—Ti-based brazing material) 24, for example, it is preferable to use a composition containing Cu in a range of 0 mass % or more and 32 mass % or less, Ti as an active metal in a range of 0.5 mass % or more and 20 mass % or less, and a balance being Ag and inevitable impurities. The thickness of the Ag—Cu—Ti-based brazing material 24 is preferably in a range of 2 μm or more and 10 μm or less.

[0070] (Heating Step S02)

[0071] Next, the copper sheet 22 and the ceramic substrate 11 are heated in a heating furnace in a vacuum atmosphere in a state of being pressed, to melt the Ag—Ti-based brazing material (Ag—Cu—Ti-based brazing material) 24.

[0072] Here, a heating temperature in the heating step S02 is in a range of the eutectic point temperature of Cu and Si or more and 850° C. or less. In the heating step S02, a temperature integration value at the above-described heating temperature is in a range of 1° C..Math.h or higher and 110° C..Math.h or lower.

[0073] A pressing load in the heating step S02 is in a range of 0.029 MPa or more and 2.94 MPa or less.

[0074] (Cooling Step S03)

[0075] Then, after the heating step S02, the molten Ag—Ti-based brazing material (Ag—Cu—Ti-based brazing material) 24 is solidified by cooling.

[0076] A cooling rate in the cooling step S03 is preferably in a range of 2° C./min or higher and 10° C./min or lower.

[0077] Here, in the heating step S02, a eutectic liquid phase is present at the grain boundary of TiN in the active metal compound layer 41, and Si on the ceramic substrate 11 side and Ag, Cu, and Ti of the Ag—Cu—Ti-based brazing material 24 diffuse into each other by using the eutectic liquid phase as a diffusion path, thereby promoting the interfacial reaction of the ceramic substrate 11.

[0078] As a result, the maximum indentation hardness in a region from 10 μm to 50 μm from the bonded interface with the ceramic substrate 11 to the circuit layer 12 (metal layer 13) side is in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less.

[0079] As described above, the ceramic substrate 11 and the copper sheets 22 and 23 are bonded to each other by the laminating step S01, the heating step S02, and the cooling step S03, thereby producing the insulating circuit substrate 10 according to the present embodiment.

[0080] (Heat Sink Bonding Step S04)

[0081] Next, the heat sink 30 is bonded to the other surface side of the metal layer 13 of the insulating circuit substrate 10.

[0082] The insulating circuit substrate 10 and the heat sink 30 are laminated with a solder material interposed therebetween and are loaded into a heating furnace such that the insulating circuit substrate 10 and the heat sink 30 are solder-bonded to each other with the solder layer 32 interposed therebetween.

[0083] (Semiconductor Element-Bonding Step S05)

[0084] Next, the semiconductor element 3 is bonded to one surface of the circuit layer 12 of the insulating circuit substrate 10 by soldering.

[0085] The power module 1 shown in FIG. 1 is produced by the above steps.

[0086] According to the insulating circuit substrate 10 (copper/ceramic bonded body) according to the present embodiment having the above configuration, since the maximum indentation hardness in the region from 10 μm to 50 μm from the bonded interface between the circuit layer 12 (metal layer 13) and the ceramic substrate 11 to the circuit layer 12 (metal layer 13) is set to 70 mgf/μm.sup.2 or more, the copper in the vicinity of the bonded interface is sufficiently melted to form a liquid phase, and the ceramic substrate 11 and the circuit layer 12 (metal layer 13) are more firmly bonded to each other.

[0087] On the other hand, since the maximum indentation hardness is suppressed to 150 mgf/μm.sup.2 or less, the vicinity of the bonded interface is not harder than necessary, and the generation of cracks during loading of the thermal cycle can be suppressed.

[0088] In the insulating circuit substrate 10 according to the present embodiment, in a case where the maximum particle size of the active metal compound particles 45 in the active metal compound layer 41 formed at the bonded interface between the ceramic substrate 11 and the circuit layer 12 (metal layer 13) is 180 nm or less, a proportion of a grain boundary region formed of a metal phase having a relatively low hardness in the active metal compound layer 41 increases, and impact resistance of the active metal compound layer 41 can be secured. As a result, for example, when a terminal material is ultrasonically bonded to the circuit layer 12 (metal layer 13), it is possible to suppress the generation of cracks in the active metal compound layer 41, and to suppress peeling of the circuit layer 12 (metal layer 13) from the ceramic substrate 11 and the generation of cracks in the ceramic substrate 11.

[0089] In the insulating circuit substrate 10 according to the present embodiment, in a case where Si, Cu, and Ag are present in the active metal compound layer 41, it is possible to suppress the generation of cracks in the active metal compound layer 41, and to obtain an insulating circuit substrate 10 having a high brazing bonding strength because no unreacted portion is formed at the bonded interface between the ceramic substrate 11 and the circuit layer 12 (metal layer 13).

[0090] The embodiment of the present invention has been described, but the present invention is not limited thereto, and can be appropriately changed without departing from the technical ideas of the present invention.

[0091] For example, in the present embodiment, the semiconductor element is mounted on the insulating circuit substrate to form the power module, but the present embodiment is not limited thereto. For example, an LED element may be mounted on the circuit layer of the insulating circuit substrate to form an LED module, or a thermoelectric element may be mounted on the circuit layer of the insulating circuit substrate to form a thermoelectric module.

[0092] In the insulating circuit substrate according to the present embodiment, it has been described that the circuit layer and the metal layer are both made of a copper sheet made of copper or a copper alloy, but the present invention is not limited thereto.

[0093] For example, in a case where the circuit layer and the ceramic substrate are made of the copper/ceramic bonded body according to the present invention, there is no limitation on the material and the bonding method of the metal layer. There may be no metal layer, the metal layer may be made of aluminum or an aluminum alloy, or may be made of a laminate of copper and aluminum.

[0094] On the other hand, in a case where the metal layer and the ceramic substrate are made of the copper/ceramic bonded body according to the present invention, there is no limitation on the material and the bonding method of the circuit layer. The circuit layer may be made of aluminum or an aluminum alloy, or may be made of a laminate of copper and aluminum.

[0095] In the present embodiment, it has been described that the Ag—Ti-based brazing material (Ag—Cu—Ti-based brazing material) 24 is disposed between the copper sheets 22 and 23 and the ceramic substrate 11 in the laminating step SOL but the present invention is not limited thereto, and a bonding material containing another active metal may be used.

[0096] In the present embodiment, it has been described that the ceramic substrate is made of silicon nitride (Si.sub.3N.sub.4), but the present invention is not limited thereto, and the ceramic substrate may be made of other silicon-containing ceramics.

EXAMPLES

[0097] Hereinafter, results of confirmation experiments performed to confirm the effects of the present invention will be described.

Example 1

[0098] First, a ceramic substrate (40 mm×40 mm×0.32 mm) made of silicon nitride (Si.sub.3N.sub.4) was prepared.

[0099] A copper sheet (37 mm×37 mm×thickness of 1.0 mm) made of oxygen-free copper was bonded to both surfaces of the ceramic substrate under the conditions shown in Table 1 by using an Ag—Cu-based brazing material containing an active metal shown in Table 1, to obtain an insulating circuit substrate (copper/ceramic bonded body). The degree of vacuum of a vacuum furnace at the time of bonding was set to 5×10.sup.−3 Pa.

[0100] For the obtained insulating circuit substrate (copper/ceramic bonded body), the maximum indentation hardness in the vicinity of a bonded interface, and the reliability of the thermal cycle were evaluated as follows.

[0101] (Maximum Indentation Hardness in Vicinity of Bonded Interface)

[0102] The maximum indentation hardness was measured in a region from 10 μm to 50 μm from the bonded interface between the copper sheet and the ceramic substrate to the copper sheet side by using an indentation hardness tester (ENT-1100a manufactured by Elionix Inc.). The measurement condition was F.sub.max=5000 mgf (number of divisions=500, step interval=20 ms) using a Berkovich indenter. A target section was exposed by buffing to make a measuring surface, and as shown in FIG. 7, the indentation hardness was measured at 50 measurement points at intervals of 10 μm, and the maximum value of the indentation hardness among them was confirmed.

[0103] In this indentation hardness test, as shown in FIG. 8, a load applied in the indenter indentation process and an indentation depth can be continuously measured, and information such as plasticity/elasticity/creep can be obtained from a load-displacement curve.

[0104] (Reliability of Thermal Cycle)

[0105] After holding in the following atmosphere, the bonded interface between the copper sheet and the ceramic substrate was inspected by SAT inspection, and the presence or absence of ceramic breaking was determined.

−78° C.×2 minutes←.fwdarw.350° C.×2 minutes

[0106] The number of cycles in which breaking occurred was evaluated. A case where breaking was confirmed in less than 6 times of cycle was evaluated as “C”, and a case where breaking was not confirmed even in 6 times or more of cycle was evaluated as “A”. The evaluation results are shown in Table 1.

TABLE-US-00001 TABLE 1 Maximum Heating step indentation Temperature hardness at Reliability integration bonded of Active Load value interface.sup.※ thermal metal (MPa) (° C.-h) (kgf/μm.sup.2) cycle Present Ti 2.94 100 70 A Invention Example 1 Present Ti 0.098 1 150 A Invention Example 2 Present Ti 1.96 78 100 A Invention Example 3 Present Hf 1.47 22 134 A Invention Example 4 Present Zr 0.49 88 91 A Invention Example 5 Present Zr 0.49 56 124 A Invention Example 6 Present Nb 0.049 8 144 A Invention Example 7 Present Zr 0.98 70 101 A Invention Example 8 Comparative Ti 0.098 0.5 173 C Example 1 Comparative Zr 0.49 0.7 160 C Example 2 .sup.※Maximum indentation hardness in region from 10 μm to 50 μm from bonded interface between copper sheet and ceramic substrate to copper sheet side

[0107] In Comparative Example 1 in which a temperature integration value in the heating step was 0.5° C..Math.h using Ti as the active metal, the maximum indentation hardness of the bonded interface was 174 mgf/μm.sup.2, which was larger than the range of the present invention, and the reliability of the thermal cycle was “C”.

[0108] In Comparative Example 2 in which a temperature integration value in the heating step was 0.7° C..Math.h using Zr as the active metal, the maximum indentation hardness of the bonded interface was 160 mgf/μm.sup.2, which was larger than the range of the present invention, and the reliability of the thermal cycle was “C”.

[0109] On the other hand, in Present Invention Examples 1 to 8 in which the maximum indentation hardness of the bonded interface was in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less, the reliability of the thermal cycle was “A” regardless of the type of the active metal.

Example 2

[0110] A ceramic substrate (40 mm×40 mm×0.32 mm) made of silicon nitride (Si.sub.3N.sub.4) was prepared.

[0111] A copper sheet (37 mm×37 mm×thickness of 0.2 mm) made of oxygen-free copper was bonded to both surfaces of the ceramic substrate under the conditions shown in Table 2 by using an Ag—Cu-based brazing material containing an active metal shown in Table 2, to obtain an insulating circuit substrate (copper/ceramic bonded body). A degree of vacuum of a vacuum furnace at the time of bonding was set to 5×10.sup.−3 Pa.

[0112] For the obtained insulating circuit substrate (copper/ceramic bonded body), the maximum indentation hardness in the vicinity of a bonded interface was evaluated by the same method as in Example 1.

[0113] In addition, the maximum particle size of the active metal compound particles in the active metal compound layer, the presence or absence of Si, Ag, and Cu in the active metal compound layer, and ultrasonic welding were evaluated by the method shown below.

[0114] (Maximum Particle Size of Active Metal Compound Particles)

[0115] The active metal compound layer was observed at a magnification of 500,000× by using a transmission electron microscope (Titan ChemiSTEM manufactured by FEI Company), to obtain a HAADF image.

[0116] By image analysis of the HAADF image, the equivalent circle diameter of the active metal compound particles was calculated. From the results of image analysis in 10 fields of view, the maximum equivalent circle diameter of the observed active metal compound particles is shown in Table 2 as the maximum particle size.

[0117] (Presence or Absence of Si, Ag, and Cu in Active Metal Compound Layer)

[0118] The grain boundaries in the active metal compound layer were integrated for 1100 frames at an acceleration voltage of 200 kV, a magnification of 500,000× to 700,000×, and 7 μs per point by using a transmission electron microscope (Titan ChemiSTEM manufactured by FEI Company). In the EDS spectrum, in a case where Si, Ag, and Cu were 0.15 cps/eV, Si, Ag, and Cu were evaluated as “present”.

[0119] (Evaluation of Ultrasonic Welding)

[0120] A copper terminal (10 mm×20 mm×2.0 mm in thickness) was ultrasonically bonded to the insulating circuit substrate by using an ultrasonic metal bonding machine (60C-904 manufactured by Ultrasonic Engineering Co., Ltd.) under the conditions of a load of 850 N, a collapse amount of 0.7 mm, and a bonding area of 5 mm×5 mm. Fifty copper terminals were bonded at a time.

[0121] After bonding, the bonded interface between the copper sheet and the ceramic substrate was inspected by using an ultrasonic flaw detector (FineSAT200 manufactured by Hitachi Solutions, Ltd.). A case where peeling of the copper sheet from the ceramic substrate or ceramic breaking was observed in 5 pieces or more out of 50 pieces was evaluated as “D”, a case where peeling of the copper sheet from the ceramic substrate or ceramic breaking was observed in 3 pieces or more and 4 pieces or less out of 50 pieces was evaluated as “C”, a case where peeling of the copper sheet from the ceramic substrate or ceramic breaking was observed in 1 piece or more and 2 pieces or less out of 50 pieces was evaluated as “B”, and a case where peeling of the copper sheet from the ceramic substrate or ceramic breaking was not observed in all 50 pieces was evaluated as “A”. The evaluation results are shown in Table 2.

TABLE-US-00002 TABLE 2 Maximum indentation Heating step Active metal compound layer hardness Temperature Heating Maximum at bonded Evaluation Active Load integration value temperature Si, Ag, particle size interface.sup.※ of ultrasonic metal (MPa) (° C. .Math. h) (° C.) Material and Cu (μm) (kgf/μm.sup.2) welding Present Ti 0.098 1 825 TiN Present 89 150 A Invention Example 11 Present Ti 0.098 10 825 TiN Present 102 136 A Invention Example 12 Present Ti 0.098 26 835 TiN Present 131 123 B Invention Example 13 Present Hf 1.47 22 825 HfN Present 118 134 A Invention Example 14 Present Hf 1.47 37 835 HfN Present 150 121 B Invention Example 15 Present Hf 1.47 60 815 HfN Present 115 116 A Invention Example 16 Present Zr 0.49 56 835 ZrN Present 156 124 C Invention Example 17 Present Zr 0.49 72 835 ZrN Present 179 110 C Invention Example 18 Present Zr 0.49 110 850 ZrN Present 213 91 D Invention Example 19 .sup.※Maximum indentation hardness in region from 10 μm to 50 μm from bonded interface between copper sheet and ceramic substrate to copper sheet side

[0122] From the comparison among Present Invention Examples 11 to 13 in which the active metal is Ti, among Present Invention Examples 14 to 16 in which the active metal is Hf, and among Present Invention Examples 17 to 19 in which the active metal is Zr, it is confirmed that the maximum particle size of the active metal compound particles in the active metal compound layer is reduced, whereby the peeling of the copper sheet from the ceramic substrate and the generation of cracks in the ceramic substrate during ultrasonic welding can be suppressed.

[0123] As described above, according to Present Invention Examples, it was confirmed that it is possible to provide a copper/ceramic bonded body and an insulating circuit substrate, which have a high brazing bonding strength and a particularly reliable thermal cycle.

REFERENCE SIGNS LIST

[0124] 10: Insulating circuit substrate (copper/ceramic bonded body) [0125] 11: Ceramic substrate (ceramic member) [0126] 12: Circuit layer (copper member) [0127] 13: Metal layer (copper member) [0128] 41: Active metal compound layer [0129] 45: Active metal compound particles