Communications device with adaptive clock frequency

Abstract

The invention provides a communications device which uses a clock circuit for generating a clock signal, the clock circuit comprising a tuneable oscillator. The clock frequency is varied to make sure it remains within a tolerance range, so that the device can continue to receive messages correctly. An error rate of received messages is determined, and in response to the error rate exceeding a threshold, a setting of the resistor arrangement and/or the capacitor arrangement is changed to change the clock signal frequency thereby to lower the error rate.

Claims

1. A communications device, comprising: a clock circuit configured and arranged to generate a clock signal and including on-chip circuitry that defines a time constant which governs a clock signal frequency of the clock signal, wherein the clock signal frequency is tuneable; a receiver for receiving messages using the clock signal; a controller adapted to: determine an error rate of received messages; and in response to an error rate exceeding a threshold, vary the clock signal frequency thereby to lower the error rate; wherein the controller is configured and arranged to iteratively adjust the clock signal frequency by increasing a difference between the clock signal frequency and a starting frequency; and to alternate between setting the clock signal frequency above the starting frequency and setting the clock signal frequency below the starting frequency.

2. The communications device of claim of claim 1, wherein the controller is further configured and arranged to iteratively adjust the clock signal frequency by increasing a difference between the clock signal frequency and a starting frequency in each iteration.

3. The communications device of claim of claim 1, wherein the controller is further configured and arranged to iteratively adjust the clock signal frequency by increasing a difference between the clock signal frequency and a starting frequency in each iteration, and to alternate between setting the clock signal frequency above the starting frequency and setting the clock signal frequency below the starting frequency, the controller setting the clock signal frequency above the starting frequency in even iterations and below the starting frequency in odd iterations.

4. A communications device, comprising: a clock circuit configured and arranged to generate a clock signal and including on-chip circuitry that defines a time constant which governs a clock signal frequency of the clock signal, wherein the clock signal frequency is tuneable; a receiver for receiving messages using the clock signal; a controller adapted to: determine an error rate of received messages; and in response to an error rate exceeding a threshold, vary the clock signal frequency thereby to lower the error rate; wherein the controller is configured and arranged to iteratively adjust the clock signal frequency by increasing a difference between the clock signal frequency and a starting frequency; and to, for first and second successive iterations, respectively: set the clock signal frequency to a first value which varies as a function of odd versus even parity and a fixed offset; and set the clock signal frequency to a second value which varies as a function of even versus odd parity and the fixed offset.

5. The communications device of claim of claim 4, wherein the controller is further configured and arranged to iteratively adjust the clock signal frequency by increasing a difference between the clock signal frequency and a starting frequency in each iteration.

6. The communications device of claim of claim 4, wherein the controller is further configured and arranged to: in the first successive iteration (2n1), set the clock signal frequency to a first value (f.sub.2n1), where f.sub.2n1=f0(2n1)*Off, where Off is the fixed offset; and in the second successive iteration (2n), set the clock signal frequency to a second value (f.sub.2n), where f.sub.2n=f0+(2n)*Off.

7. A device comprising: an RC circuit that includes a resistor and a capacitor, wherein at least one of the resistor and the capacitor is tuneable in response to a control signal; an oscillator circuit configured to generate a clock signal having a clock frequency set by an RC time constant of the RC circuit; a receiver circuit configured to receive messages using the clock signal; and a controller circuit configured to resynchronize mismatches between the clock frequency and frequencies for the received messages by changing a length of a phase of the messages; and change the control signal in response to a change in the length of the phase of the received messages.

8. The device of claim 7, wherein the controller circuit is further configured to generate the control signal to increase the RC time constant in response to the length of the phase of the messages increasing.

9. The device of claim 7, wherein the controller circuit is further configured to generate the control signal to decrease the RC time constant in response to the length of the phase of the messages decreasing.

10. The device of claim 7, wherein the receiver circuit is configured to oversample the received messages.

11. The device of claim 7, wherein the receiver circuit is configured to receive messages on a bus; and the controller circuit is configured to detect activity on the bus using samples from the oversampling.

12. The device of claim 7, wherein the controller circuit is configured to detect an error when a communication is detected on the bus and a corresponding message fails to decode.

13. The device of claim 12, wherein the controller circuit is configured to modify the control signal in response to detecting a threshold amount of errors.

14. The device of claim 12, wherein the controller circuit is configured to distinguish between multiple errors by detecting a lack of activity on the bus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will now be described with reference to the accompanying drawings, in which:

(2) FIG. 1 shows a known RC oscillator;

(3) FIG. 2 shows an oscillator design which can be used in the device of the invention;

(4) FIG. 3 shows the CAN bit timing, known from ISO11898-1;

(5) FIG. 4 is used to explain the control method of the invention; and

(6) FIG. 5 shows an example of variation of oscillator frequency with temperature.

DETAILED DESCRIPTION OF EMBODIMENTS

(7) The invention provides a communications device which uses a clock circuit for generating a clock signal, the clock circuit comprising a tuneable on-chip oscillator circuit, for example comprising a resistor arrangement and a capacitor arrangement which together define an RC time constant which governs the oscillator frequency. The clock frequency is tuneable, for example at least one of the resistor arrangement and capacitor arrangement is tuneable.

(8) The clock frequency is varied to make sure it remains within (or evolves to) a tolerance range, so that the device can continue to receive messages correctly. An error rate of received messages is determined, and in response to the error rate exceeding a threshold, the clock frequency is adjusted. For example, a setting of the resistor arrangement and/or the capacitor arrangement is changed to change the clock signal frequency thereby to lower the error rate.

(9) The implementation of the invention firstly requires an oscillator which can be tuned, preferably digitally, during operation, and secondly requires a communications system in which receive errors which result from frequency drift of the clock signal can be detected (by the device which itself is suffering the frequency drift).

(10) There are various different types of oscillator which can be used in the device of the invention.

(11) One example of RC oscillator is shown in FIG. 1, and is described in U.S. Pat. No. 7,176,765. However, LC oscillators may also be used.

(12) The oscillator 10 has an RC circuit 11, and an RS latch 12 for switching between the output of two comparators 15, 17. An RC node 13 is coupled to an inverting input lead 14 of a discharge comparator 15 and to a non-inverting input lead 16 of a charge comparator 17.

(13) Charge comparator 17 detects when the voltage on RC node 13 reaches a lower reference voltage, at which time RS latch 12 causes charge to accumulate on RC node 13. Discharge comparator 15 detects when the voltage on RC node 13 reaches a higher reference voltage, at which time RS latch 12 causes charge to discharge from RC node 13. The reference voltages are generated by a voltage divider 18 formed by a resistor string.

(14) As the operating temperature of oscillator 10 changes, the resistance of the resistors in the resistor string change, thereby changing the reference voltages.

(15) Other designs of RC oscillator do not use comparators in this way. For example, the resistor can be part of a current generator circuit, which determines the rate at which the capacitor is charged. When the capacitor is charged to a given voltage (sufficient to latch the output of a logic device), a shorting transistor is operated to discharge the capacitor. In this way, there is only one reference voltage level.

(16) Other RC oscillator circuit will be known to those skilled in the art. The invention applies equally to all such designs as well as other tuneable oscillators.

(17) FIG. 2 shows a device of the invention in the form of a communications device having an RC oscillator 20 which generates a clock signal CLK, which is used by a protocol controller 28 for the reception (and optionally also transmission) of data messages. The example of FIG. 2 is for a CAN system. The protocol controller 28 incorporates the message receiver for the CAN system.

(18) The RC oscillator 20 can be of any suitable known design, providing it has a digitally tuneable capacitor or resistor arrangement 22 as well as the other oscillator circuitry 24.

(19) A tuneable resistor arrangement can comprise a string of resistors in series, with a respective shorting transistor in parallel with each resistor in the string (or only a sub-set of the resistors may need to be shortable). The gate voltages of the shorting transistors are controlled so that they function as binary switches.

(20) A tuneable capacitor arrangement can comprise an array of capacitors in parallel, with a respective transistor in series with each capacitor in the array (or only a sub-set of the capacitors may need to be switchable into circuit). The gate voltages of the shorting transistors are controlled so that they again function as binary switches.

(21) The trimmable capacitor or resistor arrangement is shown schematically as 22.

(22) The CAN controller 28 applies a trimming setting to the resistor arrangement and/or the capacitor arrangement as determined by the method described below. The CAN controller, also receives messages from (and optionally also sends messages to) a CAN bus 26.

(23) The invention relates specifically to communications devices which use a local oscillator as a clock generator, and then use the clock signal for timing during reception of messages. If the clock signal drifts too far from the designed value, the reception of messages gives rise to errors.

(24) The communications device needs to be able to detect messages, even if they cannot be received without error, and needs to be able to distinguish between messages that have been received without error and those that have been received with errors.

(25) As mentioned above, FIG. 2 shows the invention applied to a controller area network (CAN). This is a vehicle bus standard which allows devices and controllers to communicate with each other. The devices require their own clocks, and there is a small tolerance of permitted clock frequency variation.

(26) The CAN system uses an automatic arbitration method, based on the use of dominant and recessive bits.

(27) Synchronization is done by dividing each bit of the frame into a number of segments: Synchronization, Propagation, Phase 1 and Phase 2. The length of each phase segment can be adjusted based on network and node conditions The Synchronization segment is fixed to 1 time quanta, the propagation segment is configured to a fixed length, and Phases 1 and 2 are adjusted by a re-synchronization process. The bit sampling point falls between Phase Segment 1 and Phase Segment 2, which helps facilitate continuous synchronization. Continuous synchronization in turn enables the receiver to be able to properly read the messages.

(28) FIG. 3 is a diagram showing the CAN Bit Timing.

(29) The invention uses the controller to obtain information as to whether there is communication on the bus or not. If there is communication on the bus, but nothing is received, then there are errors. This logic applies independently of the protocol/physical layer used, so that the principles underlying the invention can also applied to other communication systems than CAN.

(30) In accordance with the invention when applied to a CAN system, the CAN receiver receives messages using the clock signal. An error rate of received messages is determined and if the error rate exceeds a threshold, the clock signal frequency is iteratively adjusted.

(31) The receiver performs oversampling, and this is the case for many protocols, such as CAN, FlexRay and Ethernet. At some points in time, the samples will show activity on the bus and immediately any communication controller will interpret this as the start-of frame and try to decode the message. The oversampling means that activity will be detected even if the clock frequency is incorrect. The controller may of course fail to decode the message due to wrong clock frequency.

(32) The decoder will for example find that the frame format does not fit, the stuffing rules are not met, or that the cyclic redundancy check (CRC) is wrong, as examples of possible ways that an error is identified. The incoming stream of samples is interpreted according to fixed rules regardless of the clock frequency, thus resulting in incorrect results when the clock frequency is incorrect.

(33) The invention applies to nodes that are receive only, as well as to nodes that additionally include transmission capability. A transmit and receive node will in practice not be allowed to send messages (including error messages) if the clock is not properly adjusted.

(34) If following detection of activity on the bus, a frame is received without any error than there was clearly no error, and this is used to update a count of correctly received frames.

(35) If there was some activity on the bus that could not be interpreted as a frame, there was an error and this is used to update a count of error frames. The decoder then needs to wait for silence, before trying to decode starting with the next activity after this period of silence. How to interpret this silence depends on the rules (that are executed regardless of the clock frequency) of the protocol. For CAN this would mean for example that 10 bits sampled are identified as recessive, whereas FlexRay waits 11 bits.

(36) In this way, it is possible to count the number of trials and the number of errors and correct received frames.

(37) FIG. 4 shows how the frequency of the clock signal is varied when it is determined that frequency adjustment is needed.

(38) The target frequency of the oscillator is denoted as: f.sub.nominal, and this is centred within a tolerance range .sub.0, which is the difference between the maximum and minimum allowed frequency.

(39) The actual frequency of the oscillator after switching on is denoted as: f.sub.0.

(40) In the initial step after switching on the CAN controller receives m.sub.0 start-of-frame bits and e.sub.0 error frames and n.sub.0 correctly received frames (e.sub.0=m.sub.0n.sub.0).

(41) For event triggered protocols such as CAN, a fixed value of m is used for the analysis. A fixed time interval could be used in time-triggered communication systems like FlexRay or TT-CAN.

(42) If e.sub.0 is greater than a defined limit, for example 10% of m.sub.0, then the oscillator is tuned to the frequency f.sub.1. In one example, this is a lower frequency (although it could of course be a higher frequency, without changing the way the invention works), and it is below f.sub.0 by an amount less than the tolerance range.

(43) The CAN controller then receives m.sub.1 start-of-frame bits which represent initial activity on the bus, and e.sub.1=m.sub.1n.sub.1 error frames. If e.sub.1 is greater than a defined limit, again such as 10% of m.sub.1, then the oscillator DCO is tuned to the frequency f.sub.2 . . . and so on.

(44) The frequencies need to cover a range above and below f.sub.0 and with spacing less than the tolerance range. In one example, the new frequencies alternate above and below the initial frequency, with increasing distance from the initial frequency. This implements an iterative frequency search:
f.sub.2n1=f.sub.0(2n1)(.sub.0) with 0<<.sub.0.
f.sub.2n=f.sub.0+2n(.sub.0) with 0<<.sub.0.

(45) (.sub.0) corresponds to a fixed offset in the register value of the register that is used to trim resistor or capacitor.

(46) With this method, the oscillator finds a reliable frequency close to the desired frequency within the allowed tolerance range. Further methods may be used in order to bring the frequency closer to the target after having found a frequency in the tolerance range, for example by using information about the synchronization jump widths or phase corrections that were applied during frame reception.

(47) Other approaches may be employed, for example stepping down in frequency by an amount corresponding to a maximum expected frequency deviation, and then stepping up in increments.

(48) As mentioned above, the CAN system enables information to be derived from the correctly received frames. If all re-synchronizations where done by lengthening Phase 1 (as shown in FIG. 3), the frequency is too high. If all re-synchronisation steps are implemented by shortening Phase 2, then the frequency is too low.

(49) More generally, if the format of the received message gives some information about clock frequency, this can be used to adapt the way the clock frequency is adjusted, for example giving finer tuning even after messages are being received correctly.

(50) FIG. 5 shows an example of the drift of an oscillator frequency over temperature.

(51) The average frequency is in the allowed frequency range between f.sub.min and f.sub.max. However, at certain temperatures the frequency leaves the allowed range.

(52) The invention makes use of the digital trimming of the oscillator to provide temperature compensation, based on detection of increased errors. However, the invention is not based on temperature measurement, and can therefore compensate for other causes of clock frequency drift, for example supply voltage variations. Furthermore, the invention can also perform oscillator trimming based on a detected increases in synchronization jump width, or detected phase correction requirements in correctly received frames. In turn, the method can decrease the necessary synchronization jump width or phase correction steps. Thus, any adverse affects to frame reception that occur when the clock frequency has deviated from the desired frequency, and particularly outside the tolerance range, can be compensated.

(53) This invention can be used in a variety of communications devices. Of particular interest is oscillators that are used to clock the digital logic of a protocol controller. As outlined above, one area of interest is in the field of partial networking; especially for CAN bus systems.

(54) Various modifications will be apparent to those skilled in the art.