DYNAMIC CURRENT LIMIT FOR OPERATIONAL AMPLIFIER

Abstract

An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

Claims

1. An output stage of an operational amplifier, comprising: a first metal oxide semiconductor (MOS) device having a first gate, a first drain, and a first source, an output current of the operational amplifier flowing through the first MOS device; and a dynamic current limit circuit comprising a second MOS device having a second gate, a second drain, and a second source, the second gate being coupled to a drain of the first MOS device; a resistor coupled between the second drain and a common node; a third MOS device having a third gate, a third drain, and a third source, the third gate being coupled to a threshold voltage, the third source being coupled to the second source, and the third drain being coupled to a first current source, the second MOS device operating in an OFF mode when a drain voltage of the first MOS device is greater than the threshold voltage, and the second MOS device operating in an ON mode when the drain voltage of the first MOS device is less than the threshold voltage; a plurality of series-connected MOS devices, wherein a first voltage is generated across the plurality of series-connected MOS devices in response to a biasing current supplied to a drain of one of the plurality of series-connected MOS devices, wherein a source of another of the plurality of series-connected MOS devices is coupled to the resistor so that a combination of a first current flowing through the second MOS device and a second current flowing through the plurality of series-connected MOS devices generates a second voltage across the resistor; and wherein a drain voltage of the one of the plurality of series-connected MOS devices is a sum of the first voltage and the second voltage; and a voltage clamp circuit coupled between the drain of the one of the plurality of series-connected MOS devices and the first gate, wherein a gate to source voltage of the first MOS device is limited to the drain voltage of the one of the plurality of series-connected MOS devices.

2. The output stage of claim 1, wherein the resistor is a first resistor and wherein the output stage of the operational amplifier further comprises a second resistor coupled between the second source and the third source, wherein a first resistance of the first resistor and a second resistance of the second resistor are selected such that a gain of a feedback loop of the dynamic current limit circuit when the second MOS device is activated is less than 1.

3. The output stage of claim 1, further comprising a high voltage MOS device having a source coupled to the first drain, a gate coupled to a driver voltage, and a drain coupled to an output pin of the operational amplifier.

4. The output stage of claim 1, wherein the first MOS device, the second MOS device, the third MOS device, and the plurality of series-connected MOS devices are low voltage MOS devices.

5. The output stage of claim 1, wherein the output current of the operational amplifier when an output voltage of the operational amplifier is higher than a threshold voltage is lower than the output current of the operational amplifier when the output voltage is lower than the threshold voltage.

6. The output stage of claim 1, wherein the voltage clamp circuit comprises: a fourth MOS device having a fourth gate, a fourth drain, and a fourth source, wherein the fourth source is coupled to the drain of the one of the plurality of series-connected MOS devices; a second current source coupled between the fourth drain and the common node; a fifth MOS device having a fifth gate, a fifth drain, and a fifth source, wherein the fifth gate is coupled to the fourth gate and the fifth source is coupled to the first gate; and a sixth MOS device having a sixth gate, a sixth drain, and a sixth source, wherein the sixth drain is coupled to the fifth source, the sixth gate is coupled to the fifth drain, and the sixth source is coupled to the common node.

7. An output stage of an operational amplifier, comprising: a low voltage (LV) metal oxide semiconductor (MOS) device, wherein an output current of the operational amplifier flows through the LV MOS device; and a dynamic current limit circuit configured to sense a drain voltage of the LV MOS device; and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

8. The output stage of claim 7, wherein LV MOS device is a first LV MOS device having a first gate, a first drain, and a second source, and wherein the dynamic current limit circuit comprises: a second MOS device having a second gate, a second drain, and a second source, the second gate being coupled to a drain of the first LV MOS device; a resistor coupled between the second drain and a common node; a third MOS device having a third gate, a third drain, and a third source, the third gate being coupled to a threshold voltage, the third source being coupled to the second source, and the third drain being coupled to a first current source, the second MOS device operating in an OFF mode when the drain voltage of the first MOS device is greater than the threshold voltage, and the second MOS device operating in an ON mode when the drain voltage of the first MOS device is less than the threshold voltage; a plurality of series-connected MOS devices, wherein a first voltage is generated across the plurality of series-connected MOS devices in response to a biasing current supplied to a drain of one of the plurality of series-connected MOS devices, wherein a source of another of the plurality of series-connected MOS devices is coupled to the resistor so that a combination of a first current flowing through the second MOS device and a second current flowing through the plurality of series-connected MOS devices generates a second voltage across the resistor, wherein a drain voltage of the one of the plurality of series-connected MOS devices is a sum of the first voltage and the second voltage; and a voltage clamp circuit coupled between the drain of the one of the plurality of series-connected MOS devices and the first gate, wherein a gate to source voltage of the first MOS device is limited to the drain voltage of the one of the plurality of series-connected MOS devices.

9. The output stage of claim 8, wherein the resistor is a first resistor and wherein the operational amplifier further comprises a second resistor coupled between the second source and the third source, wherein a first resistance of the first resistor and a second resistance of the second resistor are selected such that a gain of a feedback loop of the operational amplifier when the second MOS device is activated is less than 1.

10. The output stage of claim 8, wherein the second MOS device, the third MOS device, and the plurality of series-connected MOS devices are low voltage MOS devices.

11. The output stage of claim 8, wherein the voltage clamp circuit comprises: a fourth MOS device having a fourth gate, a fourth drain, and a fourth source, wherein the fourth source is coupled to the drain of the one of the plurality of series-connected MOS devices; a second current source coupled between the fourth drain and the common node; a fifth MOS device having a fifth gate, a fifth drain, and a fifth source, wherein the fifth gate is coupled to the fourth gate and the fifth source is coupled to the first gate; and a sixth MOS device having a sixth gate, a sixth drain, and a sixth source, wherein the sixth drain is coupled to the fifth source, the sixth gate is coupled to the fifth drain, and the sixth source is coupled to the common node.

12. The output stage of claim 7, wherein the output current of the operational amplifier when an output voltage of the operational amplifier is higher than a threshold voltage is lower than the output current of the operational amplifier when the output voltage is lower than the threshold voltage.

13. The output stage of claim 7, further comprising a high voltage (HV) MOS device having a source coupled to a drain of the LV MOS device, a gate coupled to a driver voltage, and a drain coupled to an output of the operational amplifier.

14. A dynamic current limit circuit, comprising: a first metal oxide semiconductor (MOS) device having a first gate, a first drain, and a first source, the first gate being coupled to a drain of a low voltage MOS device in an output stage of an operational amplifier; a resistor coupled between the first drain and a common node; a second MOS device having a second gate, a second drain, and a second source, the second gate being coupled to a threshold voltage, the second source being coupled to the first source, and the second drain being coupled to a first current source, the first MOS device operating in an OFF mode when a drain voltage of the low voltage MOS device is greater than the threshold voltage, and the first MOS device operating in an ON mode when the drain voltage of the low voltage MOS device is less than the threshold voltage; a plurality of series-connected MOS devices, wherein a first voltage is generated across the plurality of series-connected MOS devices in response to a biasing current supplied to a drain of one of the plurality of series-connected MOS devices, wherein a source of a another of the plurality of series-connected MOS devices is coupled to the resistor so that a combination of a first current flowing through the first MOS device and a first current flowing through the plurality of series-connected MOS devices generates a second voltage across the resistor, wherein a drain voltage of the one of the plurality of series-connected MOS devices is a sum of the first voltage and the second voltage; and a voltage clamp circuit coupled between the drain of the one of the plurality of series-connected MOS devices and a gate of the low voltage MOS device in the output stage of the operational amplifier, wherein a gate to source voltage of the low voltage MOS device in the output stage of the operational amplifier is limited to the drain voltage of the one of the plurality of series-connected MOS devices.

15. The dynamic current limit circuit of claim 14, wherein the resistor is a first resistor and wherein the dynamic current limit circuit further comprises a second resistor coupled between the first source and the second source, wherein a first resistance of the first resistor and a second resistance of the second resistor are selected such that a gain of a feedback loop of the dynamic current limit circuit when the first MOS device is activated is less than 1.

16. The dynamic current limit circuit of claim 15, wherein the first MOS device, the second MOS device, and the plurality of series-connected MOS devices are low voltage MOS devices.

17. The dynamic current limit circuit of claim 15, wherein the voltage clamp circuit comprises: a fourth MOS device having a fourth gate, a fourth drain, and a fourth source, wherein the fourth source is coupled to the drain of the one of the plurality of series-connected MOS devices; a second current source coupled between the fourth drain and the common node; a fifth MOS device having a fifth gate, a fifth drain, and a fifth source, wherein the fifth gate is coupled to the fourth gate and the fifth source is coupled to the first gate; and a sixth MOS device having a sixth gate, a sixth drain, and a sixth source, wherein the sixth drain is coupled to the fifth source, the sixth gate is coupled to the fifth drain, and the sixth source is coupled to the common node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a current vs. voltage plot that illustrates the behavior of a dynamic current limit circuit, according to one aspect of this description.

[0006] FIG. 2 is a block diagram of an example output stage of a high voltage operational amplifier that includes an example dynamic current limit circuit, according to one aspect of this description.

[0007] FIG. 3 is a schematic diagram of an output stage of a high voltage operational amplifier that includes an example dynamic current limit circuit operating in a first mode, according to one aspect of this description.

[0008] FIG. 4 is a schematic diagram of the example output stage of a high voltage operational amplifier of FIG. 3 operating in a second mode, according to one aspect of this description.

[0009] FIG. 5 is a schematic diagram of the example output stage of a high voltage operational amplifier of FIG. 3 with a feedback loop opened to calculate gain, according to one aspect of this description.

[0010] FIG. 6 is a current vs. voltage plot that illustrates the behavior of the dynamic current limit circuit of FIG. 3 with three different sets of design parameters, according to one aspect of this description.

[0011] The same reference number or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

[0012] The drawings may not be drawn to scale.

[0013] Operational amplifiers have a specified “short circuit current” which is the maximum current that the operational amplifier will source or sink at the operational amplifier's maximum output voltage. To protect against exceeding SOA/heat dissipation limits, some operational amplifiers employ some type of current limiting in their output stage. One type of current limiting is fixed current limiting in which the current that is sourced or sunk by the output stage of the operational amplifier is limited to the short circuit current.

[0014] FIG. 1 is a current vs. voltage plot depicting the maximum current that can be sourced or sunk by an output stage of an operational amplifier as a function of output voltage. For the purposes of the example shown in FIG. 1, the maximum output voltage of the operational amplifier is 6 V. Thus, for the operational amplifier whose characteristics are illustrated in FIG. 1, the short circuit current is the maximum allowable current (in terms of SOA/heat dissipation limits) when the output stage is at 6V, or approximately 12.5 mA. The fixed current limiting technique is shown in dashed line in FIG. 1. It can be seen that at output voltages higher than approximately 0.75V the current sourced or sunk by the operational amplifier output stage is limited to the short circuit current of approximately 12.5 mA even though at 0.75V a much higher current could be sourced or sunk by the output stage while remaining within the SOA/heat dissipation limits. As the expected operating voltages of operational amplifiers increase, this limiting of current sinking or sourcing capabilities to the short circuit current unnecessarily caps the current sourced or sunk by the operational amplifier through a significant portion of its operating range.

[0015] Described herein are operational amplifier output stage topologies that feature a dynamic current limit circuit to allow an output stage metal-oxide semiconductor (MOS) device (e.g., MOSFET such as a p-type MOSFET (PMOS) based circuit) to sink (or source) current higher than the short circuit current of the operational amplifier when the output voltage of the operational amplifier is relatively low. The described topologies sense when the output of the operational amplifier is at or near a threshold voltage that is selected based on SOA/heat dissipation limits of devices in the output stage. When the output of the operational amplifier is below the threshold voltage, the dynamic current limit circuit controls the gate voltage of an output stage MOS device to increase the amount of current that can flow through the output stage of the operational amplifier. When the output of the operational amplifier is greater than the threshold voltage, the dynamic current limit circuit controls the gate voltage of the output stage MOS device to limit the amount of current that can flow through the output stage to the short circuit current. In this manner, the current that can be sunk or sourced is increased at lower output voltages but will not exceed SOA/heat dissipation limits for MOS devices (e.g., a high voltage (HV) MOS device) in the operational amplifier at higher output voltages. The sensing and control are performed without using a complex feedback loop or control algorithm and, in some examples, use only low voltage devices.

[0016] Throughout this description, components that are exemplary versions of a same or analogous component are assigned reference characters having the same value for the last two digits while the initial digit(s) of reference characters are assigned based on the FIG. number in which they are first introduced.

[0017] Throughout this description, certain devices are described and/or illustrated as being either n-type or p-type MOS devices. It is to be understood that in other examples the devices may have an opposite type channel with appropriate design modification.

[0018] FIG. 2 is a block diagram of an example output stage of a high voltage operational amplifier 200 that includes a dynamic current limit circuit 220 and an output stage 290. The output stage 290 includes an n-type high voltage depletion-enhancement metal oxide semiconductor FET (DE-MOSFET) 293 having a drain connected to an output pin 205 of the output stage of the high voltage operational amplifier 200 and to supply voltage V.sub.SUPPLY. The gate of the HV DE-MOSFET 293 receives a driver voltage V.sub.DRIVER.

[0019] An n-type low voltage (LV) MOS device 297 includes a drain that is coupled to a source of the HV DE-MOSFET 293 and includes a source connected to a common node (e.g., a ground or other reference voltage). One function of the HV DE-MOSFET 293 is to protect the LV MOS device 297 from damage when high voltage is driven on the output pin 205 of the output stage of the high voltage operational amplifier 200. The positive driver voltage V.sub.DRIVER maintains the HV DE-MOSFET 293 in an ON mode. When a high voltage is present on the output pin 205, the voltage drop across the HV DE-MOSFET 293 will be a significant portion of the output voltage. In this manner, at high output voltages the voltage drop across the HV DE-MOSFET 293 significantly limits the drain voltage of the LV MOS device 297. When a low voltage is present on the output pin 205, the voltage drop across the HV DE-MOSFET 293 is much lower and the drain voltage of the LV MOS device 297 is much closer to the output voltage.

[0020] The LV MOS device 297 controls the output current I.sub.OUT through the output stage 290. As described above, excessive current through the output stage could cause the HV DE-MOSFET 293 to operate outside the SOA. With fixed current limiting, as shown by the dashed line in FIG. 1, regardless of the output voltage, the output current is limited to the maximum amount of current that can be sunk when the output voltage at its maximum value. Thus, even though the HV DE-MOSFET 293 could conduct a current greater than the short circuit current at lower output voltages and remain within the SOA, the amount of current in a fixed current limiting scheme is capped at the short circuit current for all output voltages. This unnecessarily limits the current capabilities of the output stage 290 at lower output voltages, which may represent a fairly significant portion of the operating conditions of the operational amplifier.

[0021] The dynamic current limit circuit 220 controls a clamping voltage V.sub.CLAMP provided to the gate of the LV MOS device 297 to cause the LV MOS device 297 to limit the flow of output current I.sub.OUT through the output stage 290 as the output voltage V.sub.OUT approaches and exceeds the threshold voltage. The dynamic current limit circuit 220 senses the drain voltage V.sub.DLV of the LV MOS device 297 to determine a relative level of the output voltage of the operational amplifier. When the output voltage is low (e.g., lower than the driver voltage V.sub.DRIVER reduced by the V.sub.th of the HV DE-MOSFET 293), the drain voltage of the LV MOS device 297 is determined by the output voltage V.sub.OUT. When the output voltage is high, the drain voltage of the LV MOS device 297 is determined by the gate voltage of the HV DE-MOSFET 293 minus the gate-to-source voltage (V.sub.gs) of the HV DE-MOSFET 293.

[0022] The dynamic current limit circuit 220 receives (or in some examples generates) a threshold voltage V.sub.THRESH that is selected to be lower than the drain voltage V.sub.DLV of the LV MOS device 297 when the output stage 290 is supplying a high output voltage. The threshold voltage V.sub.THRESH sets the output voltage below which the dynamic current limit circuit 220 will be activated to increase the allowed maximum flow of current through the output stage 290. Referring back to FIG. 1, the solid line corresponds to the maximum output current allowed by the dynamic current limit circuit 220. With a dynamic current limit at lower output voltages the maximum current is higher than the short circuit current. For example, at approximately 2.0 V the maximum current is approximately 26 mA as compared to the short circuit current of approximately 12.5 mA. At output voltages higher than about 3.0 V the maximum current is limited to the short circuit current.

[0023] To summarize, the dynamic current limit circuit 220 operates in one of two operational modes, the operational mode being controlled based on a comparison of V.sub.DLV and V.sub.THRESH. When V.sub.DLV is greater than V.sub.THRESH, the dynamic current limit circuit 220 operates in a first mode and sets V.sub.CLAMP to limit current through the LV MOS device 297 to the short circuit current of the operational amplifier. When V.sub.DLV is lower than V.sub.THRESH, the dynamic current limit circuit 220 operates in a second mode and increases V.sub.CLAMP to allow more current to flow through the LV MOS device 297.

[0024] In some examples the output stage 290 includes a HV DE-MOSFET 293 as a cascade device and a LV MOS device 297 as an output device. However, the dynamic current limit circuit 220 can also be applied to an amplifier that includes a single MOS device in the output stage because the dynamic current limit circuit 220 senses the output voltage of the amplifier at the drain of the LV MOS device 297 to control the clamping voltage (and thus current) for the LV MOS device 297. Thus the HV DE-MOSFET 293 is not necessary for the dynamic current limit control function.

[0025] FIG. 3 is a schematic diagram of an output stage of an operational amplifier 300 that includes the output stage 290 and an example dynamic current limit circuit 320. N-type MOS device 315, resistor 362, and constant current source 359 generate a threshold voltage V.sub.THRESH from the driver voltage V.sub.DRIVER The dynamic current limit circuit 320 receives a bias voltage V.sub.BIAS from an external source (e.g., a different functional block implemented on a same integrated circuit as the output stage 290) and includes several constant current sources 351, 353, 355, 357, 359 that provide biasing currents I.sub.BIAS3, I.sub.BIAS4 I.sub.BIAS5, I.sub.BIAS2, and I.sub.BIAS1, respectively, to various parts of the dynamic current limit circuit 320. In one example, I.sub.BIAS1, I.sub.BIAS2, I.sub.BIAS4, and I.sub.BIAS5 are equal and I.sub.BIAS3 is twice I.sub.BIAS1.

[0026] The bias voltage V.sub.BIAS is applied to the source of p-type MOS device 322. The drain voltage of MOS device 322 is applied to the source of p-type MOS device 324. The drain voltage of MOS device 322 reduced by a voltage drop across resistor 364 is applied to the source of p-type MOS device 326. Current source 357 assures a constant current I.sub.BIAS2 through the drain node of MOS device 324. The gate voltage of MOS device 322 adjusts so that the current flowing through the MOS device 324 remains I.sub.BIAS2.

[0027] MOS devices 324 and 326 act like a differential pair with an offset determined by a resistance R2 of resistor 364. The operational mode of the MOS device 326 is controlled based on a comparison between V.sub.DLV and V.sub.THRESH. When V.sub.DLV at the gate of MOS device 326 is higher than V.sub.THRESH at the gate of MOS device 324, MOS device 326 is an OFF mode and no current is conducted through MOS device 326 (e.g., I.sub.1 is zero as shown in FIG. 3). When V.sub.DLV at the gate of MOS device 326 is less than V.sub.THRESH at the gate of MOS device 324, MOS device 326 turn to an ON mode and current I.sub.1 is conducted through MOS device 326. As this additional current is conducted through MOS device 326, the gate voltage of MOS device 322 is adjusted so that the MOS device 322 conducts I.sub.BIAS2 plus the current I.sub.1 conducted through MOS device 326. As V.sub.DLV falls further below V.sub.THRESH the MOS device 326 will conduct a higher current as the V.sub.gs of the MOS device 326 increases.

[0028] An internal low drop out (LDO) bias voltage V.sub.BIAS and a biasing current I.sub.BIAS3 provided by the constant current source 351 generate a constant voltage V.sub.FIXED across a set of series connected n-type MOS devices 328, 332, 334. A current I.sub.2 flows through the set of series-connected MOS device 328, 332, 334. A voltage clamp circuit includes p-type MOS devices 336 and 338, n-type MOS device 340, and constant current sources 353 and 355. The constant current sources 353, 355 maintain equal currents I.sub.BIAS4, I.sub.BIAS5, through the MOS devices 336 and 338, respectively. The source voltage of MOS device 338 will not exceed the source voltage of MOS device 336. In this manner, the voltage clamp circuit limits the voltage V.sub.CLAMP to the drain voltage of the MOS device 328 which is present at the source of MOS device 336. The drain voltage of the MOS device 328, and therefore the clamping voltage V.sub.CLAMP, is limited to the sum of the fixed voltage across the set of series-connected MOS devices 328, 332, 334 and an adjustable voltage V.sub.ADJ that is generated across resistor 366.

[0029] When the drain voltage V.sub.DLV of the LV MOS device 297 is greater than the threshold voltage, the MOS device 326 will have sufficiently low V.sub.gs to cause the MOS device 326 to turn to the OFF mode and current will not flow through the MOS device 326 (i.e., I.sub.1=0). When the drain voltage V.sub.DLV of the LV MOS device 297 is below the threshold voltage, the MOS device 326 will be in the ON mode and current will flow through the MOS device 326 (i.e., I.sub.1≠0) to common node 301 (e.g., ground). Thus the adjustable voltage V.sub.ADJ, which will change depending on whether current is flowing through the MOS device 326, varies as a function of the relationship between the threshold voltage V.sub.THRESH and the drain voltage of the LV MOS device 297 V.sub.DLV.

[0030] FIG. 3 illustrates the operation of the dynamic current limit circuit 320 in the first mode because V.sub.DLV is greater than the threshold voltage V.sub.THRESH. When V.sub.DLV is greater than the threshold voltage V.sub.THRESH, the output voltage V.sub.OUT of the operational amplifier is high enough that the output current should be limited to the short circuit current. In the first mode, MOS device 326 is in the OFF mode and I.sub.1 is zero. The adjustable voltage is equal to the current I.sub.2 flowing through the set of series-connected MOS devices 328, 332, 334 multiplied by the resistance R1 of resistor 366. This results in a clamping voltage that will limit the current through the output stage 290. The clamping voltage V.sub.CLAMP will remain relatively constant as output voltage falls until a threshold relationship between the threshold voltage and the drain voltage V.sub.DLV of the LV MOS device 297 is reached (e.g., V.sub.THRESH=V.sub.DLV).

[0031] FIG. 4 illustrates the operation of the dynamic current limit circuit 320 in the second mode because V.sub.DLV is less than the threshold voltage V.sub.THRESH. When V.sub.DLV is below the threshold voltage V.sub.THRESH the output voltage V.sub.OUT of the operational amplifier is low enough that the output current need not be limited to the short circuit current. In the second mode MOS device 326 is in the ON mode and I.sub.1 is not zero (as depicted in FIG. 4). The current I.sub.1 will increase as the output voltage falls. The adjustable voltage V.sub.ADJ is equal to the sum of I.sub.1 and I.sub.2 multiplied by the resistance R1 of resistor 366. This results in a higher clamping voltage V.sub.CLAMP (as compared to V.sub.CLAMP when V.sub.OUT>V.sub.THRESH) that will allow for increased current through the output stage 290.

[0032] When the MOS device 326 is in the ON mode, a positive feedback loop is created in which the clamping voltage V.sub.CLAMP increases as the drain voltage of the LV MOS device 297 decreases. The gain of this positive feedback loop may be controlled to be less than 1 as described below.

[0033] FIG. 5 illustrates the dynamic current limit circuit 320 with a hypothetical break 302 (indicated by the X) in the positive feedback loop created when the MOS device 326 is in the ON mode. With the feedback loop thus cut, the gain of the dynamic current limit loop may be expressed as:

[00001]$\begin{array}{cc}\mathrm{Voltage}\mathrm{Gain}=\left(g_{M_{\mathrm{dcl\_eff}}}\right)\times R1\times \frac{g_{\mathrm{M\_op}\mathrm{\_LV}}}{g_{\mathrm{M\_op}\mathrm{\_HV}}}& \mathrm{EQ}.1\end{array}$

where g.sub.M.sub.dcl_eff is the gain of the dynamic current limit circuit when the MOS device 326 is ON.

[00002]$\begin{array}{cc}{g}_{M_{\mathrm{dcl\_eff}}}=\frac{g_{M_{dcl}}}{1+g_{M_{dcl}}.Math.R2}\approx \frac{1}{R2}& \mathrm{EQ}.2\end{array}$

Thus, the voltage gain can be simply approximated as:

[00003]$\begin{array}{cc}\mathrm{Voltage}\mathrm{Gain}\approx \frac{R1}{R2}\times \frac{g_{\mathrm{M\_op}\mathrm{\_LV}}}{g_{\mathrm{M\_op}\mathrm{\_HV}}}& \mathrm{EQ}.3\end{array}$

The values of R1 and R2 are chosen such that the voltage gain is less than 1 to make the positive feedback loop stable.

[0034] FIG. 6 is a current vs. voltage plot depicting the effects of the positive feedback loop on several design considerations for the output stage of the operational amplifier of FIGS. 3-5. Cases 1 and 2 illustrate the maximum current that will be allowed when the gain of the feedback loop is greater than 1 while Case 3 illustrates maximum current when the gain is less than one. In both Cases 1 and 2 the maximum current is greater than in Case 3 due to the larger feedback gain in Cases 1 and 2. Case 1 illustrates the scenario in which the HV DE-MOSFET 293 is not sized to support increased current. In this instance the LV MOS device 297 will operate in the triode mode and remain in the triode mode even when the operational amplifier goes into short circuit mode and the HV DE-MOSFET 293 may operate outside the SOA. Case 2 illustrates the scenario in which the size of the HV DE-MOSFET 293 has sufficient size to support the increased current. While the current is limited so that the HV DE-MOSFET 293 does not operate outside the SOA, increasing the size of the HV DE-MOSFET 293 in this manner leads to undesirable increases in cost and package size. As illustrated in Case 3, when the gain of the feedback loop is less than one, HV DE-MOSFET 293 operates within the SOA while allowing for increased current at lower voltages.

[0035] In the illustrated examples, all of the devices besides the HV DE-MOSFET 293 are low voltage MOS devices. This is advantageous in terms of size and cost.

[0036] As described above, dynamic current limit enables an operational amplifier to sink or source higher than a short circuit current when an output voltage of the operational amplifier is relatively low while sufficiently limiting the current sunk or sourced to protect a DE-MOSFET in the operational amplifier's output stage when the operational amplifier is near a short circuit condition.

[0037] The methods are illustrated and described above as a series of acts or events, but the illustrated ordering of such acts or events is not limiting. For example, some acts or events may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Also, some illustrated acts or events are optional to implement one or more aspects or embodiments of this description. Further, one or more of the acts or events depicted herein may be performed in one or more separate acts and/or phases. In some embodiments, the methods described above may be implemented in a computer readable medium using instructions stored in a memory.

[0038] In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. Accordingly, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled directly to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.

[0039] Modifications are possible in the described examples, and other implementations are possible, within the scope of the claims.