SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

Abstract

A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

Claims

1. A semiconductor memory device, comprising: a substrate; a transistor disposed on the substrate, wherein the transistor comprises a source doped region disposed in the substrate; a drain doped region disposed in the substrate and spaced apart from the source doped region; a channel region in the substrate between the source doped region and the drain doped region; and a gate over the channel region; a data storage region in proximity to the transistor and recessed into the substrate, wherein the data storage region comprises at least one ridge and at least one V-shaped groove; a bottom electrode layer conformally covering the at least one ridge and at least one V-shaped groove within the data storage region; a resistive-switching layer conformally covering the bottom electrode layer; and a top electrode layer covering the resistive-switching layer.

2. The semiconductor memory device according to claim 1 further comprising: a diffusion region surrounding the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

3. The semiconductor memory device according to claim 1 further comprising: a metal silicide layer between the substrate and the bottom electrode layer.

4. The semiconductor memory device according to claim 3, wherein the metal silicide layer comprises nickel silicide.

5. The semiconductor memory device according to claim 1, wherein the at least one V-shaped groove is completely filled with the bottom electrode layer, the resistive-switching layer, and the top electrode layer.

6. The semiconductor memory device according to claim 1, wherein the bottom electrode layer comprises titanium nitride or tantalum nitride.

7. The semiconductor memory device according to claim 1, wherein the resistive-switching layer comprises metal oxide.

8. The semiconductor memory device according to claim 1, wherein the resistive-switching layer comprises hafnium oxide, tantalum oxide, titanium oxide or aluminum oxide.

9. The semiconductor memory device according to claim 1, wherein the top electrode layer comprises titanium nitride or tantalum nitride.

10. The semiconductor memory device according to claim 1, wherein the top electrode layer comprises tungsten.

11. A method for forming a semiconductor memory device, comprising: providing a substrate; forming a transistor on the substrate, wherein the transistor comprises a source doped region disposed in the substrate; a drain doped region disposed in the substrate and spaced apart from the source doped region; a channel region in the substrate between the source doped region and the drain doped region; and a gate over the channel region; forming a data storage region in proximity to the transistor and recessed into the substrate, wherein the data storage region comprises at least one ridge and at least one V-shaped groove; conformally depositing a bottom electrode layer over the at least one ridge and at least one V-shaped groove within the data storage region; conformally forming a resistive-switching layer on the bottom electrode layer; and forming a top electrode layer on the resistive-switching layer.

12. The method according to claim 11 further comprising: forming a diffusion region surrounding the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

13. The method according to claim 11 further comprising: forming a metal silicide layer between the substrate and the bottom electrode layer.

14. The method according to claim 13, wherein the metal silicide layer comprises nickel silicide.

15. The method according to claim 11, wherein the at least one V-shaped groove is completely filled with the bottom electrode layer, the resistive-switching layer, and the top electrode layer.

16. The method according to claim 11, wherein the bottom electrode layer comprises titanium nitride or tantalum nitride.

17. The method according to claim 11, wherein the resistive-switching layer comprises metal oxide.

18. The method according to claim 11, wherein the resistive-switching layer comprises hafnium oxide, tantalum oxide, titanium oxide or aluminum oxide.

19. The method according to claim 11, wherein the top electrode layer comprises titanium nitride or tantalum nitride.

20. The method according to claim 11, wherein the top electrode layer comprises tungsten.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 to FIG. 13 are schematic diagrams illustrating a method of forming a semiconductor memory device according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0028] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0029] Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0030] Please refer to FIG. 1 to FIG. 13, which are schematic diagrams of a method for forming a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, first, a substrate 100 is provided, for example, a semiconductor substrate such as a silicon substrate. According to an embodiment of the present invention, the substrate 100 includes a transistor forming region TR and a data storage region DR. The data storage region DR is adjacent to the transistor forming region TR.

[0031] As shown in FIG. 2, next, a lithography process and an etching process are performed to form isolation trenches 102 on the surface of the substrate 100, which define an active area, and several grooves 104 are formed in the data storage region DR.

[0032] As shown in FIG. 3, next, a patterned photoresist layer 110 is formed on the substrate 100. The patterned photoresist layer 110 includes an opening 110a exposing the grooves 104 in the data storage region DR. Then, using a wet etching method, the surface of the grooves 104 in the data storage region DR is etched to form ridges 112 and V-shaped grooves 114.

[0033] The aforementioned wet etching method can be performed using tetramethylammonium hydroxide (TMAH) to etch the substrate 100 between the grooves 104 in the data storage region DR into a structure having a spire-shaped or triangular profile.

[0034] As shown in FIG. 4, the patterned photoresist layer 110 is then removed. Subsequently, a dielectric layer, for example, a silicon oxide layer, is deposited on the substrate 100 in a blanket manner. A chemical mechanical polishing (CMP) process is then used for planarization to form a trench isolation structure TI and a buried oxide layer BI filled into the V-shaped grooves 114 in the data storage region DR.

[0035] As shown in FIG. 5, a gate electrode GE, for example, a polysilicon gate is formed on the substrate 100 in the transistor forming region TR. According to an embodiment of the present invention, the spacer SP may be formed on the sidewall of the gate electrode GE. According to an embodiment of the present invention, a gate dielectric layer GD may be formed between the gate electrode GE and the substrate 100. According to an embodiment of the present invention, the gate electrode GE is adjacent to the data storage region DR.

[0036] As shown in FIG. 6, next, a patterned photoresist layer 210 is formed on the substrate 100. The patterned photoresist layer 210 includes an opening 210a that exposes the buried oxide layer BI in the data storage region DR. An ion implantation process 250 is then performed, and dopants, such as N-type dopants, are implanted into the substrate 100 through the opening 210a. Am annealing process is then performed to form a diffusion region DF, such as an N.sup.+ diffusion region.

[0037] As shown in FIG. 7, next, a patterned photoresist layer 310 is formed on the substrate 100. The patterned photoresist layer 310 includes an opening 310a that exposes the transistor forming region TR and the gate electrode GE located in the transistor forming region TR.

[0038] An ion implantation process 350 is then performed to form a source doped region SS and a drain doped region DD in the substrate 100 on both sides of the gate electrode GE, respectively, so that the fabrication of the transistor T is completed. A channel region CH is formed in the substrate 100 between the source doped region SS and the drain doped region DD of the transistor T. The gate electrode GE is located above the channel region CH. According to an embodiment of the present invention, the source doped region SS and the drain doped region DD may be N.sup.+ doped regions. According to an embodiment of the present invention, the drain doped region DD and the diffusion region DF are connected and merged together.

[0039] As shown in FIG. 8, next, a patterned photoresist layer 410 is formed on the substrate 100. The patterned photoresist layer 410 includes an opening 410a that exposes the buried oxide layer BI in the data storage region DR. Next, an etching process, such as dry etching or wet etching, is performed to remove the buried oxide layer BI and the ridges 112 and the V-shaped grooves 114 are exposed.

[0040] As shown in FIG. 9, next, a metal silicide layer SIC may be formed on the gate electrode GE, the source doped region SS, the drain doped region DD, and the data storage region DR. According to an embodiment of the present invention, for example, the metal silicide layer SIC may include nickel silicide, but is not limited thereto. The metal silicide layer SIC can be formed using a self-alignment method.

[0041] A bottom electrode layer BE is conformally deposited on the ridges 112 and the V-shaped grooves 114 in the data storage region DR. Then, a resistive-switching layer RS is conformally formed on the bottom electrode layer BE. Next, a top electrode layer TE is formed on the resistive-switching layer RS. According to an embodiment of the present invention, the V-shaped grooves 114 are completely filled by the bottom electrode layer BE, the resistive-switching layer RS, and the top electrode layer TE.

[0042] According to an embodiment of the present invention, the bottom electrode layer BE may include titanium nitride or tantalum nitride. According to an embodiment of the present invention, the resistive-switching layer RS may include a metal oxide. According to an embodiment of the present invention, for example, the resistive-switching layer RS may include hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide. According to an embodiment of the present invention, the top electrode layer TE may include titanium nitride or tantalum nitride. According to another embodiment of the present invention, the top electrode layer TE may include tungsten.

[0043] As shown in FIG. 10, next, a patterned photoresist layer 510 is formed on the substrate 100 in the data storage area DR to define the location and pattern of a data storage structure. Then, an etching process such as an anisotropic dry etching process is performed to etch away the top electrode layer TE, the resistive-switching layer RS and the bottom electrode layer BE not covered by the patterned photoresist layer 510, thereby forming the data storage structure DSS. According to an embodiment of the present invention, the diffusion region DF surrounds the bottom electrode layer BE of the data storage structure DSS.

[0044] As shown in FIG. 11 to FIG. 13, subsequent steps include deposition and planarization of the dielectric layer IL (FIG. 11), replacement metal gate (RMG) process (FIG. 12), and contact plug fabrication (FIG. 13). As shown in FIG. 11, a chemical vapor deposition (CVD) process is first performed, and a dielectric layer IL, such as a silicon oxide layer, is deposited on the surface of the substrate 100 in a blanket manner. Then, a chemical mechanical polishing (CMP) process is performed to planarize the dielectric layer IL until the gate electrode GE is exposed. Subsequently, as shown in FIG. 12, a metal gate replacement process is performed to form a metal gate MG. As shown in FIG. 13, contact plugs CS, CG, and CD are formed in the dielectric layer IL, which are electrically connected to the source doped region SS, gate electrode GE, and drain doped region DD, respectively, thereby forming a semiconductor memory device MC.

[0045] Structurally, as shown in FIG. 13, the semiconductor memory device MC of the present invention includes a substrate 100 and a transistor T disposed on the substrate 100. The transistor T includes a source doped region SS disposed in the substrate 100, a drain doped region DD disposed in the substrate 100 and spaced apart from the source doped region SS, a channel region CH in the substrate 100 between the source doped region SS and the drain doped regions DD, and a metal gate MG above the channel region CH. A data storage region DR is adjacent to the transistor T and is recessed into the substrate 100.

[0046] According to an embodiment of the present invention, the data storage region DR includes at least one ridge 112 and at least one V-shaped groove 114. According to an embodiment of the present invention, the bottom electrode layer BE conformally covers the ridges 112 and the V-shaped grooves 114 in the data storage region DR. According to an embodiment of the present invention, the resistive-switching layer RS conformally covers the bottom electrode layer BE. According to an embodiment of the present invention, the top electrode layer TE covers the resistive-switching layer RS.

[0047] According to an embodiment of the present invention, the semiconductor memory device MC further includes a diffusion region DF surrounding the bottom electrode layer BE, wherein the drain doped region DD is merged with the diffusion region DF.

[0048] According to an embodiment of the present invention, the semiconductor memory device MC further includes a metal silicide layer SIC located between the substrate 100 and the bottom electrode layer BE. According to an embodiment of the present invention, the metal silicide layer includes nickel silicide.

[0049] According to an embodiment of the present invention, the V-shaped grooves 114 are completely filled by the bottom electrode layer BE, the resistive-switching layer RS, and the top electrode layer TE. According to an embodiment of the present invention, the bottom electrode layer BE includes titanium nitride or tantalum nitride. According to an embodiment of the present invention, the resistive-switching layer RS includes a metal oxide. According to an embodiment of the present invention, the resistive-switching layer RS includes hafnium oxide, tantalum oxide, titanium oxide or aluminum oxide. According to an embodiment of the present invention, the top electrode layer TE includes titanium nitride or tantalum nitride. According to an embodiment of the present invention, the top electrode layer TE includes tungsten.

[0050] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.