Solid-state imaging device and method of manufacturing the same, and imaging apparatus

Abstract

A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion.

Claims

1. An imaging device, comprising: a semiconductor substrate including an effective pixel region and an optical black region, wherein the effective pixel region of the semiconductor substrate includes a photoelectric conversion region, and wherein the semiconductor substrate has a first side and a second side opposite the first side; a first trench disposed entirely in the optical black region of the semiconductor substrate in a cross-sectional view; a first film disposed in the first trench in the cross-sectional view, wherein the first film includes a metal; and a second film disposed in the first trench in the cross-sectional view, wherein the second film is disposed above the first side and extends outside of the first trench toward a side of the effective pixel region in the cross-sectional view.

2. The imaging device according to claim 1, wherein the first film is comprised of tungsten.

3. The imaging device according to claim 1, wherein the second film is comprised of a high-dielectric insulating film.

4. The imaging device according to claim 1, wherein the first film is disposed above the second film in the cross-sectional view.

5. The imaging device according to claim 1, wherein the first film is disposed above the first side in the optical black region.

6. The imaging device according to claim 1, further comprising: a second trench disposed in the effective pixel region of the semiconductor substrate in the cross-sectional view.

7. The imaging device according to claim 6, wherein a width of the first trench is larger than a width of the second trench in the cross-sectional view.

8. The imaging device according to claim 1, wherein the second film is comprised of a metallic oxide.

9. The imaging device according to claim 6, wherein the second film extends into the second trench in the cross-sectional view.

10. The imaging device according to claim 1, further comprising: a wiring layer disposed adjacent to the second side.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic configuration diagram illustrating an example of a CMOS-type solid-state imaging device applied to each embodiment of the present disclosure;

(2) FIG. 2 is a schematic diagram illustrating a cross-sectional structure of an example of the CMOS-type solid-state imaging device applied to each embodiment of the present disclosure;

(3) FIG. 3 is a schematic diagram illustrating a first embodiment of the solid-state imaging device according to the present disclosure;

(4) FIG. 4 is a schematic diagram illustrating a modification of the first embodiment of the solid-state imaging device according to the present disclosure;

(5) FIGS. 5A to 5C are schematic diagrams (1) illustrating a method of manufacturing the solid-state imaging device of the first embodiment;

(6) FIGS. 6A and 6B are schematic diagrams (2) illustrating a method of manufacturing the solid-state imaging device of the first embodiment;

(7) FIG. 7 is a schematic diagram illustrating a second embodiment of the solid-state imaging device according to the present disclosure;

(8) FIG. 8 is a schematic diagram illustrating a light-shielding of an optical black region in a case where embedded light-shielding is not performed;

(9) FIG. 9 is a schematic diagram illustrating a modification of the second embodiment of the solid-state imaging device according to the present disclosure;

(10) FIGS. 10A to 10D are schematic diagrams (1) illustrating a method of manufacturing the solid-state imaging device of the second embodiment;

(11) FIGS. 11A to 11D are schematic diagrams (2) illustrating a method of manufacturing the solid-state imaging device of the second embodiment;

(12) FIG. 12 is a schematic diagram illustrating a third embodiment of the solid-state imaging device according to the present disclosure;

(13) FIG. 13 is a schematic diagram illustrating a modification of the third embodiment of the solid-state imaging device according to the present disclosure;

(14) FIGS. 14A to 14D are schematic diagrams (1) illustrating a method of manufacturing the solid-state imaging device of the third embodiment;

(15) FIGS. 15A to 15D are schematic diagrams (2) illustrating a method of manufacturing the solid-state imaging device of the third embodiment;

(16) FIG. 16 is a schematic diagram illustrating a fourth embodiment of the solid-state imaging device according to the present disclosure;

(17) FIG. 17 is a schematic diagram illustrating a modification of the fourth embodiment of the solid-state imaging device according to the present disclosure;

(18) FIGS. 18A to 18D are schematic diagrams (1) illustrating a method of manufacturing the solid-state imaging device of the fourth embodiment;

(19) FIGS. 19A to 19D are schematic diagrams (2) illustrating a method of manufacturing the solid-state imaging device of the fourth embodiment;

(20) FIG. 20 is a schematic diagram illustrating an example of an imaging apparatus to which the present disclosure is applied;

(21) FIG. 21 is a schematic diagram illustrating a modification of the first embodiment;

(22) FIGS. 22A and 22B are schematic diagrams illustrating an example of a planar arrangement (coding) of an organic photoelectric conversion film and an organic color filter layer;

(23) FIG. 23 is a schematic diagram illustrating an example of a circuit configuration of a unit pixel;

(24) FIG. 24 is a schematic diagram illustrating a CMOS-type solid-state imaging device of a front-surface irradiation type in the related art; and

(25) FIG. 25 is a schematic diagram illustrating a CMOS-type solid-state imaging device of a rear-surface irradiation type in the related art.

DETAILED DESCRIPTION

(26) Hereinafter, exemplary embodiments for carrying out the present disclosure (hereinafter, referred to as “embodiment”) will be described. Description will be made in the following order.

(27) 1. Schematic Configurational Example of CMOS-Type Solid-State Imaging Device

(28) 2. First Embodiment

(29) 3. Second Embodiment

(30) 4. Third Embodiment

(31) 5. Fourth Embodiment

(32) 6. Fifth Embodiment

(33) 7. Modification

1. Schematic Configurational Example of CMOS-Type Solid-State Imaging Device

(34) FIG. 1 shows a schematic configuration diagram of an example of a CMOS-type solid-state imaging device applied to each embodiment of the present disclosure. Here, as shown in FIG. 1, a solid-state imaging device 1 includes a pixel region (so-called imaging region) 3 in which pixels 2 including a plurality of photoelectric conversion devices are two-dimensionally disposed in a semiconductor substrate 11 (for example, a silicon substrate) in a regular manner, and a peripheral circuit section.

(35) Each of the pixels 2 includes for example, a photodiode serving as a photoelectric conversion device, and a plurality of pixel transistors (so-called MOS transistor). The plurality of pixel transistors may be composed of, for example, three transistors of a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to be composed of four transistors.

(36) FIG. 23 shows a schematic diagram illustrating an example of a circuit configuration of two unit pixels of the pixel 2.

(37) The unit pixel includes, for example, a photodiode 51 as the photoelectric conversion device, and includes four transistors of a transfer transistor 52, an amplification transistor 53, an address transistor 59, and a reset transistor 55 as active devices with respect to this one photodiode.

(38) The photodiode 51 photoelectrically converts incident light to electric charges (here, electrons) with an amount corresponding to an amount of light. The transfer transistor 52 is connected between the photodiode 51 and a floating diffusion FD. In addition, a driving signal is applied to a gate (transfer gate) of transfer transistor via a driving interconnection 56, such that electrons, which are photoelectrically converted at the photodiode 51, are transferred to the floating diffusion FD.

(39) A gate of the amplification transistor 53 is connected to the floating diffusion FD. The amplification transistor 53 is connected to a vertical signal line 57 via the address transistor 54, and makes up a source follower together with a constant current source I outside the pixel section. When an address signal is applied to a gate of the address transistor 54 via a driving interconnection 58 and the address transistor 54 is turned on, the amplification transistor 53 amplifies a potential of the floating diffusion FD and outputs a voltage corresponding to the potential to a vertical signal line 57. A voltage output from each pixel is output to an S/H.Math.CDS circuit through the vertical signal line 57.

(40) The reset transistor 55 is connected between a power source Vdd and the floating diffusion FD. A reset signal is applied to a gate of the reset transistor 55 via a driving interconnection 59, such that the potential of the floating diffusion FD is reset to the power source potential Vdd.

(41) Since each gate of the transfer transistor 52, the address transistor 54, and the reset transistor 55 is connected in a row unit, the above-described operations are simultaneously performed with respect to each pixel for one row.

(42) In addition, the pixel 2 may adopt a sharing pixel structure. This sharing pixel structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and each sharing other pixel transistors one by one.

(43) The peripheral circuit section includes a vertical driving circuit 4, column signal processing circuits 5, a horizontal driving circuit 6, an output circuit 7, a control circuit 8, or the like.

(44) The control circuit 8 receives data for giving an instruction such as an input clock and an operation mode, or outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal or a control signal that becomes a reference of an operation of the vertical driving circuit 4, the column signal processing circuits 5, the horizontal driving circuit 6, or the like, based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. In addition, these signals are input to the vertical driving circuit 4, the column signal processing circuits 5, the horizontal driving circuit 6, or the like.

(45) The vertical driving circuit 4 includes, for example, a shift register, selects a pixel driving interconnection, supplies a pulse for driving a pixel to the selected pixel driving interconnection, and drives the pixel in a row unit. That is, the vertical driving circuit 9 selectively scans each pixel 2 of the pixel region 3 in a row unit sequentially in a vertical direction, and supplies a pixel signal to the column signal processing circuits 5 via a vertical signal line 9 based on a signal charge generated according to an amount of light received, for example, in the photodiode serving as an electric conversion device of each pixel 2.

(46) The column signal processing circuits 5 are disposed, for example, for each column of the pixel 2, and perform a signal processing such as noise removal for each pixel column with respect to signals output from the pixels 2 of one row. That is, the column signal processing circuits 5 perform a signal processing such as a CDS for removing a fixed pattern noise unique to the pixel 2, signal amplification, and AD conversion. A horizontal selection switch (not shown) is connected and provided between output stages of the column signal processing circuits 5 and the horizontal signal line 10.

(47) The horizontal driving circuit 6 includes, for example, a shift register and sequentially outputs a horizontal scanning pulse, and thereby selects in order each of column signal processing circuits 5 and outputs a pixel signal supplied from each of the column signal processing circuit 5 to the horizontal signal line 10.

(48) The output circuit 7 performs a signal processing with respect to signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 10, and outputs the processed signals. For example, only buffering may be performed, or black level adjustment, row variation correction, various digital signal processes, or the like may be performed. An input and output terminal 12 exchanges a signal with the outside.

(49) FIG. 2 a schematic diagram illustrating a cross-sectional structure of an example a CMOS-type solid-state imaging device applied to each embodiment of the present disclosure. A CMOS-type solid-state imaging device 21 shown in FIG. 2 includes, for example, a pixel region (so-called an imaging region) 23 where a plurality of pixels are arranged, and a peripheral circuit section that is disposed at the periphery of the pixel region (not shown in FIG. 2), which are formed in a semiconductor substrate 22 made of, for example, silicon.

(50) The pixel region 23 includes an effective pixel region 23A that actually receives light, amplifies a signal charge generated by a photoelectric conversion, and reads out it by the column signal processing circuit 5, and an optical black region 23B for outputting an optical black that becomes a reference for the black level. In addition, the optical black region 23B is formed at an outer circumferential part of the effective pixel region 23A.

(51) The unit pixel 24 includes a photodiode PD serving as a photoelectric conversion section and a plurality of pixel transistors Tr. The photodiode PD is formed across the entire region in the thickness direction of the semiconductor substrate 22, and is configured as a pn conjunction type photodiode by an n-type semiconductor region 25 and a p-type semiconductor region 26 facing the front and rear surfaces of the substrate. In addition, the p-type semiconductor region facing the front and rear surfaces of the substrate also functions as a hole charge accumulation region for suppressing a dark current.

(52) Each pixel 24 including the photodiode PD and the pixel transistor Tr is separated by a device separating region 27 formed in the p-type semiconductor region. The pixel transistor Tr is configured by forming n-type source and drain regions (not shown) in p-type semiconductor well region 28 formed at a front-surface side 22A of the semiconductor substrate 22, and forming a gate electrode 29 on the front surface of the substrate between the n-type source and drain regions via a gate insulating film. In addition, in FIG. 2, a plurality of pixel transistors are represented by one pixel transistor Tr and are schematically shown by the gate electrode 29.

(53) On the front surface 22A of the semiconductor substrate 22, so-called multi-layered interconnection layer 33 where a plurality of interconnections 32 are disposed via an interlayer insulating film 31 is formed. Light is not incident to the multi-layered interconnection layer 33, such that the layout of the interconnections 32 can be freely set.

(54) In addition, on the rear surface 22B of the semiconductor substrate 22, an on-chip color filter 42 and an on-chip microlens 43 are sequentially formed. In addition, as the on-chip color filter 42, for example, a color filter of a Bayer array may be used, and the on-chip microlens 43 may be made of, for example, an organic material such as a resin.

(55) In addition, light L is incident from the rear-surface 22B side of the substrate, and is focused at the on-chip microlens 43 and is received by each photodiode PD.

2. First Embodiment

(56) [Configurational Example of Solid-State Imaging Device]

(57) FIG. 3 shows a schematic diagram illustrating a first embodiment of a solid-state imaging device according to the present disclosure. The solid-state imaging device according to this embodiment includes a first groove portion 61 that has a line width of 100 to 300 nm and that is formed in the device separating region 27 of the rear surface 22B side of the substrate, which serves as a light receiving plane 34 of the photodiode PD, from the rear-surface 22B side of the semiconductor substrate 22. In addition, the first groove portion 61 is formed in a lattice shape to surround each pixel 24 in a plan view.

(58) In addition, a high-dielectric material film 62 made of a hafnium oxide (HfO.sub.2) film is formed on the rear surface 22B of the semiconductor substrate 22, and the high-dielectric material film 62 is formed on a side surface and the bottom surface of the first groove portion 61. Furthermore, an insulating material 63 made of silicon dioxide is embedded in the first groove portion 61 via the high-dielectric material film 62.

(59) In the rear-surface irradiation type solid-state imaging device 21 according to the first embodiment, adjacent light receiving sections are physically separated by the first groove portion 61. Therefore, it is possible to suppress a signal charge, which is photoelectrically converted at a vicinity of the rear surface of the semiconductor substrate 22, from flowing to adjacent pixels and it is possible to diminish an optical color mixture that may occur between the adjacent pixels.

(60) In addition, in a case where the first groove portion 61 is formed in the device separating region 27, there is a possibility of a pinning deviation occurring at a peripheral part of the first groove portion 61 due to impurity activation through physical damage or ion irradiation onto a side wall and the bottom surface of the first groove portion 61. In regard to such a problem, in the rear-surface irradiation type solid-state imaging device 21 according to the first embodiment, the high-dielectric material film 62 having a substantial fixed charge is formed on the side wall and the bottom surface of the first groove portion 61, and thereby it is possible to suppress the pinning deviation.

(61) [Modification]

(62) In the first embodiment, description is made with respect to a case where the insulating material 63 is embedded in only the inside of the first groove 61 as an example, but as shown in FIG. 4, the insulating material 63 may be provided on the entire surface of the high-dielectric material film 62.

(63) [Example of Method of Manufacturing Solid-State Imaging Device]

(64) FIGS. 5A to 6B illustrate a method of manufacturing the solid-state imaging device 21 of the first embodiment. In addition, only a cross-sectional structure of a main part is shown in FIGS. 5A to 6B, and with respect to reference numerals of omitted parts, reference is made to FIG. 2.

(65) In the method of manufacturing the solid-state imaging device 21 of the first embodiment, first, the photodiodes PD corresponding to each pixel separated by the device separating region 27 of the p-type semiconductor region is formed in a region where a pixel region of the silicon semiconductor substrate 22 is to be formed.

(66) In addition, the photodiode PD is formed to have a pn conjunction composed of the n-type semiconductor region 25 formed across the entire region in the substrate thickness direction, and the p-type semiconductor region 26 that comes into contact with the n-type semiconductor region 25 and faces the front and rear surfaces 22A and 22B of the substrate.

(67) The p-type semiconductor well region 28, which comes into contact with the device separating region 27, is formed in a region of the front surface 22A of the substrate, which corresponds to each pixel, and a plurality of pixel transistors Tr are formed in the p-type semiconductor well region 28, respectively. In addition, each of the pixel transistors Tr is formed by source and drain regions, a gate insulating film, and a gate electrode 29.

(68) In addition, the multi-layered interconnection layer 33 where interconnections 32 of a plurality of layers are disposed via the interlayer insulating film 31 is formed above the front surface 22A of the substrate.

(69) Next, as shown in FIG. 5A, a positive-type photosensitive resist film 91 is formed on the rear surface 22B of the semiconductor substrate 22, and the patterning is performed using a general purpose photolithography technique in a manner such that an opening region having a line width of 100 to 300 nm is formed in the separating region 27.

(70) Subsequently, as shown in FIG. 5B, through a dry etching using SF.sub.6/O.sub.2-based gas, the semiconductor substrate 22 is dug to a depth of approximately 400 nm using the resist film 91 as a mask, and thereby the first groove portion 61 is formed. Then, the resist film 91 is removed.

(71) Next, as shown in FIG. 5C, a hafnium oxide film (high-dielectric material film 62) is formed on the rear surface 22B of the semiconductor substrate 22 with a thickness of 50 nm by using a sputtering method. Furthermore, as shown in FIG. 6A, a silicon dioxide film (insulating film 63) is formed with a thickness of 200 nm on the hafnium oxide film by using a CVD method. As a result thereof, the first groove portion 61 is embedded with the hafnium oxide film and the silicon dioxide film.

(72) Next, as shown in FIG. 6B, a dry etching using CF.sub.4/O.sub.2-based gas is performed, and thereby the silicon dioxide other than the silicon dioxide embedded in first groove portion 61 is removed.

(73) Then, the on-chip color filter 42 and the on-chip microlens 43 of, for example, a Bayer array are sequentially formed on the rear surface 22B of the semiconductor substrate 22. By doing so, it is possible to obtain the solid-state imaging device 21 of the first embodiment.

3. Second Embodiment

(74) [Configurational Example of Solid-State Imaging Device]

(75) FIG. 7 shows a schematic diagram illustrating a second embodiment of the solid-state imaging device according to the present disclosure. The solid-state imaging device according to this embodiment includes a first groove portion 61 that has a line width of 100 to 300 nm and that is formed in the device separating region 27 of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear-surface 22B side. In addition, the first groove portion 61 is formed in a lattice shape to surround each pixel 24 in a plan view.

(76) In addition, the solid-state imaging device according to this embodiment includes a second groove portion 64 that has a line width of approximately 500 μm and that is formed in the optical black region 23B of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear-surface 22B side of the semiconductor substrate 22.

(77) In addition, a high-dielectric material film 62 made of a hafnium oxide (HfO.sub.2) film is formed on the rear surface 22B of the semiconductor substrate 22, and the high-dielectric material film 62 is formed on a side surface and the bottom surface of the first groove portion 61, and a side surface and the bottom surface of the second groove 64.

(78) In addition, an insulating material 63 made of silicon dioxide is embedded in the first groove portion 61 via the high-dielectric material film 62. Meanwhile, an insulating material 63 made of silicon dioxide and a light shielding material 65 made of tungsten are embedded in the second groove portion 64 via the high-dielectric material film 62.

(79) In the rear-surface irradiation type solid-state imaging device 21 according to the second embodiment, the optical black region 23B is provided with an embedded light-shielding structure configured by embedding the light shielding material 65 in the second groove portion 64, such that the lowering of the height of the solid-state imaging device can be realized.

(80) That is, in a black level definition, it is necessary to forma film having a light shielding property in the optical black region 23B, and in a case where the embedded light-shielding is not performed, as shown in FIG. 8, it is necessary to form the light shielding film 66 on the rear surface 22B of the semiconductor substrate 22. In this case, due to the thickness of the light shielding film 66, the lowering of the height is interrupted. Conversely, in the rear-surface irradiation type solid-state imaging device 21 according to this embodiment, since the embedded light-shielding is adopted, the lowering of the height is realized, the distance from the on-chip microlens 43 to the photodiode PD becomes short, a light incidence efficiency is improved, and the prevention of the color mixture is further realized.

(81) In the rear-surface irradiation type solid-state imaging device 21 according to the second embodiment, since adjacent light receiving sections are physically separated by the first groove portion 61, the optical color mixture that may occur between adjacent pixels can be diminished similarly to the first embodiment.

(82) In addition, the high-dielectric material film 62 having a substantial fixed charge is formed on the side wall and the bottom surface of the first groove portion 61, and the side wall and the bottom surface of the second groove portion 64, such that it is possible to suppress the pinning deviation similarly to the first embodiment.

(83) [Modification]

(84) In the second embodiment, description is made with respect to a Case where the insulating material 63 and the light shielding material 65 are embedded in the second groove portion 64 via the high-dielectric material film 62 as an example, but the insulating material 63 is not necessarily required to be embedded. For example, as shown in FIG. 9, only the light shielding material 65 may be embedded in the second groove portion 64 via the high-dielectric material film 62.

(85) [Example of Method of Manufacturing Solid-State Imaging Device]

(86) FIGS. 10A to 11D illustrate a method of manufacturing the solid-state imaging device 21 of the second embodiment. In addition, only a cross-sectional structure of a main part is shown in FIGS. 10A to 11D, and with respect to reference numerals of omitted parts, reference is made to FIG. 2.

(87) In the method of manufacturing the solid-state imaging device 21 of the second embodiment, the photodiode PD separated by the device separating region 27, the p-type semiconductor well region 28, the pixel transistor Tr, and the multi-layered interconnection layer 33 are formed, similarly to the first embodiment.

(88) Next, as shown in FIG. 10A, after a positive-type photosensitive resist film 91 is formed on the rear surface 22B of the semiconductor substrate 22, the resist film 91 is patterned using a general purpose photolithography technique. Specifically, the patterning is performed in a manner such that an opening region having a line width of 100 to 300 nm is formed in the device separating region 27, and an opening region having a line width of approximately 500 μm is formed in the optical black region 23B.

(89) Subsequently, as shown in FIG. 10B, through a dry etching using SF.sub.6/O.sub.2-based gas, the semiconductor substrate 22 is dug in a depth of approximately 400 nm using the resist film 91 as a mask, and thereby the first groove portion 61 and the second groove portion 64 are formed. Then, the resist film 91 is removed.

(90) Next, as shown in FIG. 10C, a hafnium oxide film (high-dielectric material film 62) is formed on the rear surface 22B of the semiconductor substrate 22 with a thickness of 50 nm by using a sputtering method. Furthermore, as shown in FIG. 10D, a silicon dioxide film (insulating film 63) is formed with a thickness of 200 nm on the hafnium oxide film by using a CVD method. As a result thereof, the first groove portion 61 is embedded with the hafnium oxide film and the silicon dioxide film. In addition, the second groove portion 64 becomes a state of not being embedded.

(91) Subsequently, as shown in FIG. 11A, the silicon dioxide film (insulating film 63) that is formed on the bottom surface of the second groove portion 64 of the optical black region 23B is covered with a resist film 92, a dry etching using CF.sub.4/O.sub.2-based gas is performed, and thereby the resist film 92 is removed. As a result thereof, as shown in FIG. 11B, the silicon dioxide other than the silicon dioxide embedded in the first groove portion 61 and the second groove portion 64 is removed.

(92) Next, as shown FIG. 11C, a light shielding film 93 made of tungsten is formed with a thickness of approximately 300 nm by a CVD method, and the light shielding film 93 formed on the bottom surface of the second groove portion 64 of the optical black region 23B is covered with a resist film 94.

(93) Consequently, as shown in FIG. 11D, a dry etching by SF.sub.6/O.sub.2-based gas is performed using the resist film 94 as a mask, and the exposed light shielding film 93 is etched and is removed. As a result thereof, when the resist film 94 is removed, the second groove portion 64 of the optical black region 23B is embedded with the hafnium oxide film, the silicon dioxide film, and the light shielding film.

(94) Then, the on-chip color filter 42 and the on-chip microlens 43 of, for example, a Bayer array are sequentially formed on the rear surface 22B of the semiconductor substrate 22. By doing so, it is possible to obtain the solid-state imaging device 21 of the second embodiment.

4. Third Embodiment

(95) [Configurational Example of Solid-State Imaging Device]

(96) FIG. 12 shows a schematic diagram illustrating a third embodiment of the solid-state imaging device according to the present disclosure. The solid-state imaging device according to this embodiment includes a first groove portion 61 that has a line width of 100 to 300 nm and that is formed in the device separating region 27 of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear-surface 22B side of the semiconductor substrate 22. In addition, the first groove portion 61 is formed in a lattice shape to surround each pixel 24 in a plan view.

(97) In addition, the solid-state imaging device according to this embodiment includes a third groove portion 67 that is formed in a region between the effective pixel region 23A and the optical black region 23B of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear surface 22B of the semiconductor substrate 22.

(98) In addition, a high-dielectric material film 62 made of a hafnium oxide (HfO.sub.2) film is formed on the rear surface 22B of the semiconductor substrate 22, and the high-dielectric material film 62 is formed on a side surface and the bottom surface of the first groove portion 61, and a side surface and the bottom surface of the third groove 67.

(99) In addition, an insulating material 63 made of silicon dioxide is embedded in the first groove portion 61 via the high-dielectric material film 62. On the other hand, an insulating material 63 made of silicon dioxide and a light shielding material 65 made of tungsten are embedded in the third groove portion 67 via the high-dielectric material film 62.

(100) In rear-surface irradiation type solid-state imaging device 21 according to the third embodiment, the region between the effective pixel region 23A and the optical black region 23B is provided with an embedded light-shielding structure configured by embedding the light shielding material 65 in the third groove portion 67, such that it is possible to realize an increase in the black level. Specifically, the embedded light-shielding structure is provided between the effective pixel region 23A and the optical black region 23B, such that it is possible to suppress the sneaking of light into the optical black region 23B, and thereby the black level can be improved.

(101) In addition, in the rear-surface irradiation type solid-state imaging device 21 according to the third embodiment, since adjacent light receiving sections are physically separated by the first groove portion 61, the optical color mixture that may occur between adjacent pixels can be diminished similarly to the first embodiment.

(102) In addition, the high-dielectric material film 62 having a substantial fixed charge is formed on the side wall and the bottom surface of the first groove portion 61, and the side wall and the bottom surface of the third groove portion 67, such that it is possible to suppress the pinning deviation similarly to the first embodiment.

(103) [Modification]

(104) In the third embodiment, description is made with respect to a case where the insulating material 63 and the light shielding material 65 are embedded in the third groove portion 67 via the high-dielectric material film 62 as an example, but the insulating material 63 is not necessarily required to be embedded. For example, as shown in FIG. 13, only the light shielding material 65 may be embedded in the third groove portion 67 via the high-dielectric material film 62.

(105) [Example of Method of Manufacturing Solid-State Imaging Device]

(106) FIGS. 14A to 15C illustrate a method of manufacturing the solid-state imaging device 21 of the third embodiment. In addition, only a cross-sectional structure of a main part is shown in FIGS. 14A to 15C, and with respect to reference numerals of omitted parts, reference is made to FIG. 2.

(107) In the method of manufacturing the solid-state imaging device 21 of the third embodiment, the photodiode PD separated by the device separating region 27, the p-type semiconductor well region 28, the pixel transistor Tr, and the multi-layered interconnection layer 33 are formed, similarly to the first embodiment.

(108) Next, as shown in FIG. 14A, after a positive-type photosensitive resist film 91 is formed on the rear surface 22B of the semiconductor substrate 22, the resist film 91 is patterned using a general purpose photolithography technique. Specifically, the patterning is performed in a manner such that an opening region having a line width of 100 to 300 nm is formed in the device separating region 27, and an opening region is formed between the effective pixel region 23A and the optical black region 23B.

(109) Subsequently, as shown in FIG. 14B, through a dry etching using SF.sub.6/O.sub.2-based gas, the semiconductor substrate 22 is dug in a depth of approximately 400 nm using the resist film 91 as a mask, and thereby the first groove portion 61 and the third groove portion 67 are formed. Then, the resist film 91 is removed.

(110) Next, as shown in FIG. 14C, a hafnium oxide film (high-dielectric material film 62) is formed on the rear surface 22B of the semiconductor substrate 22 with a thickness of 50 nm by using a sputtering method. Furthermore, as shown in FIG. 14D, a silicon dioxide film (insulating film 63) is formed with a thickness of 200 nm on the hafnium oxide film by using a CVD method. As a result thereof, the first groove portion 61 is embedded with the hafnium oxide film and the silicon dioxide film. In addition, the third groove portion 67 becomes a state of not being embedded.

(111) Subsequently, as shown in FIG. 15A, the silicon dioxide film (insulating film 63) that is formed on the bottom surface of the third groove portion 67 is covered with a resist film 92, a dry etching using CF4/O.sub.2-based gas is performed, and then the resist film 92 is removed. As a result thereof, as shown in FIG. 15B, the silicon dioxide other than the silicon dioxide embedded in the first groove portion 61 and the third groove portion 67 is removed.

(112) Next, as shown in FIG. 15C, a light shielding film 93 made of tungsten is formed with a thickness of approximately 300 nm by a CVD method, and then, as shown in FIG. 15D, the light shielding film 93 formed on the bottom surface of the third groove portion 67 is covered with a resist film 94.

(113) Next, a dry etching by SF.sub.6/O.sub.2-based gas is performed using the resist film 94 as a mask, and the exposed light shielding film 93 is etched and is removed. As a result thereof, when the resist film 94 is removed, the third groove portion 67 is embedded with the hafnium oxide film, the silicon dioxide film, and the light shielding film.

(114) Then, the on-chip color filter 42 and the on-chip microlens 43 of, for example, a Bayer array are sequentially formed on the rear surface 22B of the semiconductor substrate 22. By doing so, it is possible to obtain the solid-state imaging device 21 of the third embodiment.

5. Fourth Embodiment

(115) [Configurational Example of Solid-State Imaging Device]

(116) FIG. 16 shows a schematic diagram illustrating a fourth embodiment of the solid-state imaging device according to the present disclosure. The solid-state imaging device according to this embodiment includes a first groove portion 61 that has a line width of 100 to 300 nm and that is formed in the device separating region 27 of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear-surface 22B side of the semiconductor substrate 22. In addition, the first groove portion 61 is formed in a lattice shape to surround each pixel 24 in a plan view.

(117) In addition, the solid-state imaging device according to this embodiment includes a second groove 64 that has a line width of approximately 500 μm and that is formed in the optical black region 23B of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear surface 22B side of the semiconductor substrate 22.

(118) In addition, the solid-state imaging device according to this embodiment includes a third groove portion 67 that is formed in a region between the effective pixel region 23A and the optical black region 23B of the rear surface 22B of the substrate, which serves as the light receiving plane 34 of the photodiode PD, from the rear surface 22B of the semiconductor substrate 22.

(119) In addition, a high-dielectric material film 62 made of a hafnium oxide (HfO.sub.2) film is formed on the rear surface 22B of the semiconductor substrate 22, and the high-dielectric material film 62 is formed on a side surface and the bottom surface of the first groove portion 61, a side surface and the bottom surface of the second groove 64, and a side surface and the bottom surface of the third groove 67.

(120) In addition, an insulating material 63 made of silicon dioxide is embedded in the first groove portion 61 via the high-dielectric material film 62. On the other hand, an insulating material 63 made of silicon dioxide and a light shielding material 65 made of tungsten are embedded in the second groove 64 and the third groove portion 67 via the high-dielectric material film 62.

(121) In addition, in the rear-surface irradiation type solid-state imaging device 21 according to the fourth embodiment, since adjacent light receiving sections are physically separated by the first groove portion 61, the optical color mixture that may occur between adjacent pixels can be diminished similarly to the first embodiment.

(122) In addition, the high-dielectric material film 62 having a substantial fixed charge is formed on the side wall and the bottom surface of the first groove portion 61, the side wall and the bottom surface of the second groove portion 64, and the side wall and the bottom surface of the third groove portion 67, such that it is possible to suppress the pinning deviation similarly to the first embodiment.

(123) In addition, in the rear-surface irradiation type solid-state imaging device 21 according to the fourth embodiment, the embedded light-shielding structure is formed in the optical black region 23B, such that the lowering of the height of the solid-state imaging device can be realized similarly to the second embodiment.

(124) In addition, in the rear-surface irradiation type solid-state imaging device 21 according to the fourth embodiment, the embedded light-shielding configured by embedding the light shielding material 65 in the third groove portion 67 is provided, such that it is possible to realize an increase in the black level similarly to the third embodiment.

(125) [Modification]

(126) In the fourth embodiment, description is made with respect to a case where the insulating material 63 and the light shielding material 65 are embedded in the second groove portion 69 and the third groove portion 67 via the high-dielectric material film 62 as an example, but the insulating material 63 is not necessarily required to be embedded. For example, as shown in FIG. 17, only the light shielding material 65 may be embedded in the second groove portion 69 and the third groove portion 67 via the high-dielectric material film 62.

(127) [Example of Method of Manufacturing Solid-State Imaging Device]

(128) FIGS. 18A to 19D illustrate a method of manufacturing the solid-state imaging device 21 of the fourth embodiment. In addition, only a cross-sectional structure of a main part is shown in FIGS. 18A to 19D, and with respect to reference numerals of omitted parts, reference is made to FIG. 2.

(129) In the method of manufacturing the solid-state imaging device 21 of the fourth embodiment, the photodiode PD separated by the device separating region 27, the p-type semiconductor well region 28, the pixel transistor Tr, and the multi-layered interconnection layer 33 are formed, similarly to the first embodiment.

(130) Next, as shown in FIG. 18A, after a positive-type photosensitive resist film 91 is formed on the rear surface 22B of the semiconductor substrate 22, the resist film 91 is patterned using a general purpose photolithography technique. Specifically, the patterning is performed in a manner such that an opening region having a line width of 100 to 300 nm is formed in the device separating region 27, and an opening region having a line width of approximately 500 μm is formed in the optical black region 23B. In addition, when the patterning is performed simultaneously, an opening region is also formed between the effective pixel region 23A and the optical black region 23B.

(131) Subsequently, as shown in FIG. 18B, through a dry etching using SF.sub.6/O.sub.2-based gas, the semiconductor substrate 22 is dug in a depth of approximately 400 nm using the resist film 91 as a mask, and thereby the first groove portion 61, the second groove portion 64, and the third groove portion 67 are formed. Then, the resist film 91 is removed.

(132) Next, as shown in FIG. 18C, a hafnium oxide film (high-dielectric material film 62) is formed on the rear surface 22B of the semiconductor substrate 22 with a thickness of 50 nm by using a sputtering method. Furthermore, as shown in FIG. 18D, a silicon dioxide film (insulating film 63) is formed with a thickness of 200 nm on the hafnium oxide film by using a CVD method. As a result thereof, the first groove portion 61 is embedded with the hafnium oxide film and the silicon dioxide film. In addition, the second groove portion 64 and the third groove portion 67 become a state of not being embedded.

(133) Subsequently, as shown in FIG. 19A, the silicon dioxide film (insulating film 63) that is formed on the bottom surface of each of the second groove portion 64 and the third groove portion 67 is covered with a resist film 92, a dry etching using CF.sub.4/O.sub.2-based gas is performed, and thereby the resist film 92 is removed. As a result thereof, as shown in FIG. 19B, the silicon dioxide other than the silicon dioxide embedded in the first groove portion 61, the second groove portion 64, and the third groove portion 67 is removed.

(134) Next, as shown FIG. 19C, a light shielding film 93 made of tungsten is formed with a thickness of approximately 300 nm by a CVD method, and as shown in FIG. 19D, light shielding film 93 formed on the bottom surface of each of the second groove portion 64 and the third groove portion 67 is covered with resist film 94.

(135) Next, a dry etching by SF.sub.6/O.sub.2-based gas is performed using the resist film 94 as a mask, and the exposed light shielding film 93 is etched and is removed. As a result thereof, when the resist film 94 is removed, the second groove portion 64 of the optical black region 23B is embedded with the hafnium oxide film, the silicon dioxide film, and the light shielding film. In addition, the third groove portion 67 that is formed in a region between the effective pixel region 23A and the optical black region 23B is also embedded by the hafnium oxide film, the silicon dioxide film, and the light shielding film.

(136) Then, the on-chip color filter 42 and the on-chip microlens 43 of, for example, a Bayer array are sequentially formed on the rear surface 22B of the semiconductor substrate 22. By doing so, it is possible to obtain the solid-state imaging device 21 of the second embodiment.

6. Fifth Embodiment

(137) [Configuration of Camera]

(138) FIG. 20 shows a schematic diagram illustrating a camera 77 that is an example of an imaging apparatus to which the present disclosure is applied. In addition, the camera 77 shown in FIG. 20 uses the above described solid-state imaging device of the first to fourth embodiments as an imaging device.

(139) In the camera 77 to which the present disclosure is applied, light from an object (not shown), is incident to an imaging area of a solid-state imaging device 73 via an optical system such as the lens 71, and a mechanical shutter 72. In addition, the mechanical shutter 72 blocks out the incidence of light to the imaging area of the solid-state imaging device 73 and determines an exposure period.

(140) Here, as the solid-state imaging device 73, the above-described solid-state imaging device 1 according to the first to fourth embodiments is used, and the solid-state imaging device 73 is driven by a driving circuit 74 including a timing generating circuit, a driving system, or the like.

(141) In addition, an output signal of the solid-state imaging device 73 is subjected to various signal processes by a next stage signal processing circuit 75, and is derived to the outside as an imaging signal, the derived imaging signal is stored in a storage medium such as a memory, and is output to a monitor.

(142) In addition, an opening and closing control of the mechanical shutter 72, a control of the driving circuit 74, a control of the signal processing circuit 75, or the like is performed by a system controller 76.

(143) In the camera to which the present disclosure is applied, the solid-state imaging device to which the above-described present disclosure is applied is adopted, such that it is possible to suppress the occurrence of an optical color mixture, and it is possible to obtain a pickup image having a high image quality.

7. Modification

(144) [In Regard to Color Filter]

(145) In the above-described first to fifth embodiments, description is made with respect to a case where the color filter 42 arranged in a RGB Bayer array is used, but an organic photoelectric conversion film may be used to realize a solid-state imaging device with high accuracy by improving color reproducibility.

(146) FIG. 21 shows a schematic diagram illustrating a modification of the first embodiment. In the solid-state imaging device 21 shown in FIG. 21, an organic photoelectric conversion film 82 is formed on the rear surface 22B of the semiconductor substrate 22, and an organic color filter layer 84 is further formed via a separation layer 83.

(147) The organic color filter layer 84 is formed correspondingly to the photodiode PD, and for example, to read out blue (B) and red (R), an organic color filter layer 84C of Cyan and organic color filter layer 84Y of Yellow are disposed in a checkerboard pattern. In addition, an on-chip microlens 43, which focuses the incident light to each photodiode PD, is formed on the organic color filter layer 84.

(148) As the green (G)-based dye of the organic photoelectric conversion film 82, rhodamine-based dye, phthalocyanine derivative, quinacridone, eosin-Y, meracyanine-based dye, or the like may be exemplified as an example thereof.

(149) In the solid-state imaging device 21 of this modification, green (G) is extracted from the organic photoelectric film 82, blue (B) and red (R) are extracted from a combination of the organic color filter layers 84 of Cyan and Yellow.

(150) Hereinafter, an example of a planar arrangement (coding) of the organic photoelectric conversion film 82 and the organic color filter layer 84 will be described with reference to FIGS. 22A and 22B.

(151) As shown in FIG. 22A, green (G) made of the organic photoelectric conversion film 82 is arranged in all pixels. In addition, as shown in FIG. 22B, Cyan and Yellow are arranged in a so-called checkerboard pattern. A spectroscopy of blue (B) and red (R) is accomplished by the following principle.

(152) Specifically, in regard to blue (B), a red (R) component is absorbed by the organic color filter layer 84C of Cyan and is removed, and then a green (G) component is absorbed by the organic photoelectric conversion film 82 of green (G) and is removed, and accordingly, the blue (B) can be extracted as a remaining blue (B) component.

(153) On the other hand, in regard to red (R), a blue component (B) is absorbed by the organic color filter layer 84Y of Yellow and is removed, and then a green (G) component is absorbed by the organic photoelectric conversion film 82 of green (G) and is removed, and accordingly, the red (R) can be extracted as a remaining red (R) component.

(154) By the above-described configuration, a color signal separated into green (G), blue (B), and red (R) can be output.

(155) In addition, since the organic color filter layer 84C of Cyan and the organic color filter layer 84Y of Yellow are arranged in a so-called checkerboard pattern, a spatial brightness or a chromatic resolution is diminished a little. However, it is possible to remarkably improve the color reproducibility.

(156) [In Regard to Semiconductor Substrate]

(157) In the above-described first to fourth embodiments, description is made with respect to a case where the semiconductor substrate is made of silicon as an example, but the semiconductor substrate is not necessarily required to be a silicon substrate, and the semiconductor substrate may be made another semiconductor material.

(158) [In Regard to High-Dielectric Material Film]

(159) In the above-described first to fourth embodiments, description is made with respect to a case where a hafnium oxide film is used as the high-dielectric material film 62 as an example, but it is not necessarily required to use the hafnium oxide film. That is, as long as the pinning deviation caused by the forming of the first groove portion 61, the second groove portion 64, or the third groove portion 67 can be sufficiently suppressed, it is not necessarily required to use the hafnium oxide film. For example, a tantalum pentoxide (Ta.sub.2O.sub.5) film, a zirconium dioxide (ZrO.sub.2) film, or the like may be used.

(160) [In Regard to Embedded Light-Shielding]

(161) In the above-described second to fourth embodiments, description is made with respect to a case where tungsten is used as the light shielding material 65 as an example, but is the use of tungsten not necessarily required. That is, as long as the embedded light-shielding structure can be sufficiently configured, for example, aluminum or the like may be embedded.

(162) The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-169911 filed in the Japan Patent Office on Jul. 29, 2010, the entire contents of which is hereby incorporated by reference.

(163) It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.