Memory cell layout for low current field-induced MRAM

Abstract

Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

Claims

1. A magnetic random access memory (MRAM) circuit comprising: a cell; a bottom electrode located entirely within the cell; a magnetic tunnel junction (MTJ) structure located in the cell and above the bottom electrode; and an access transistor including a first terminal, a second terminal, and a gate terminal; wherein: the MTJ structure is centered at the center of the cell; the bottom electrode is not centered at the center of the cell; and as viewed from directly above the bottom electrode, the first terminal of the access transistor is entirely underneath the bottom electrode.

2. The MRAM circuit of claim 1, wherein a ratio of a length of the bottom electrode along an axis to a length of the MTJ structure along the same axis is equal to or greater than 1.9.

3. The MRAM circuit of claim 2, wherein the ratio is 2.1 when the MRAM circuit is fabricated at a 32 nm complementary metal-oxide semiconductor (CMOS) process technology.

4. The MRAM circuit of claim 2, wherein the ratio is 1.9 when the MRAM circuit is fabricated at a 45 nm CMOS process technology.

5. The MRAM circuit of claim 2, wherein the ratio is 2.0 when the MRAM circuit is fabricated at a 65 nm CMOS process technology.

6. A magnetic random access memory (MRAM) circuit comprising: a cell; a bottom electrode located entirely within the cell; a magnetic tunnel junction (MTJ) structure located in the cell and above the bottom electrode; and an access transistor including a first terminal, a second terminal, and a gate terminal; wherein: the MTJ structure is centered at the center of the cell and the bottom electrode is not centered at the center of the cell; as viewed from directly above the bottom electrode, the first terminal of the access transistor is entirely underneath the bottom electrode; and a ratio of a length of the bottom electrode along an axis to a length of the MTJ structure along the same axis is equal or greater than 1.9.

7. The MRAM circuit of claim 6, wherein the ratio is 2.1 when the MRAM circuit is fabricated at a 32 nm complementary metal-oxide semiconductor (CMOS) process technology.

8. The MRAM circuit of claim 6, wherein the ratio is 1.9 when the MRAM circuit is fabricated at a 45 nm CMOS process technology.

9. The MRAM circuit of claim 6, wherein the ratio is 2.0 when the MRAM circuit is fabricated at a 65 nm CMOS process technology.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic drawing showing Level 1 of a MRAM cell layout, in accordance with one embodiment of the invention.

(2) FIG. 2 is a schematic drawing showing Level 2 of the MRAM cell layout, in accordance with one embodiment of the invention.

(3) FIG. 3 is a schematic drawing showing Level 3 of the MRAM cell layout, in accordance with one embodiment of the invention.

(4) FIG. 4 is a schematic drawing showing a combination of Levels 1-3 of the MRAM cell layout.

(5) FIG. 5 is a schematic drawing of a MRAM cell based on a MRAM cell layout, in accordance with one embodiment of the invention

DETAILED DESCRIPTION

(6) In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form only in order to avoid obscuring the invention.

(7) Reference in this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearance of the phrase in one embodiment in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

(8) Although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to said details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention.

(9) Field-induced MRAM relies on a magnetic field generated around metal lines to switch the magnetization of a MTJ. In most embodiments each cell has two crossing metal lines for this purpose. These lines are the bit line and the word line, respectively. The MTJ is located at the intersection of these two lines and at least the bit line is in contact with the MTJ.

(10) In some embodiments of MRAM, the memory cell also comprises an access transistor connected to the MTJ. The final cell size may be defined by the metal lines' pitch and/or by the access transistor size.

(11) Embodiments of the present invention disclose different MRAM cell layouts, and MRAM structures (cell and devices) based on said cell layouts. Each MRAM cell layout is optimized for a given level of CMOS process technology.

(12) For clarity, the MRAM cell layout is divided into three levels. FIG. 1 shows the first level, FIG. 2 shows the second level, and FIG. 3 shows the third level. In the figures, M1 refers to a first level of metallization, M2 a second level, and M3 a third level.

(13) FIG. 1, shows the layout for two cells at the CMOS transistor level, in plan view. Referring to FIG. 1, reference numeral 1 refers to a gate formed between contacts 2. The gate may be of poly-silicon, in one embodiment. Reference numeral 3 indicates an active area for the MRAM cell. Reference numeral 4 indicates the cell border. Reference numeral 5 indicates a metal 1 (M1) island. Reference numeral 6 indicates a via, referred to as via 1 Reference numeral 7 indicates a metal 1 line. Reference numeral 8 indicates a MTJ. Reference numeral 9 indicates a bottom electrode. Reference numerals 10 and 11 indicate a metal 2 line and a metal 3 line, respectively. The via 1 connects M2 and M1.

(14) The second level depicted in FIG. 2 shows the MRAM cell layout from the M1 layer up to via 1, in plan view. Metal line 7 connecting the source is common for both transistors (left and right).

(15) Referring to FIG. 3, the third level shows the magnetic region of the cell in plan view. The magnetic region includes layers: bottom electrode (9), MTJ (8), metal 2 (10) and metal 3 (11). The bottom electrode is also a seed layer for the MTJ-and connects the MTJ (8) to via 1 (6), which is the element connected to the access transistor through M2 (10) and Interface via (12). This electrode is shaped so that the MTJ (8) can be placed at the center of the cell, as shown in FIG. 3. In this way the magnetic interaction between neighboring cells is minimized, which is important to reduce variation in the switching field of the MTJ's.

(16) FIG. 4 shows all levels of the cell combined.

(17) FIG. 5 shows a side view of the MRAM cell, fabricated in accordance with the MRAM cell layout described above.

(18) The final cell size depends on available CMOS manufacturing process capability. According to current manufacturing process a list of dimensions of the different elements of the cell and distances between some of those elements (as numbered in FIGS. 1 to 4) is provided in Table 1. The table covers MRAM cell layouts for CMOS nodes 65 nm, 45 nm and 32 nm.

(19) TABLE-US-00001 TABLE 1 MRAM Cell Layout for 32 nm CMOS process technology Size (nm) Element Description 32 nm node cell 1 Poly-Si gate 18 2 Contact 54 54 3 Active area 70 width 4 Cell border 180 140 5 Metal 1 island 67 84 6 Via 1 54 54 7 Metal 1 line 58 8 MTJ 46 46 9 Bottom 95 66 electrode 10 Metal 2 line 58 12 Interface via 54 54 11 Metal 3 line 58 d1 35 d2 114 d3 21 d4 21 d5 56 d6 114 d7 90 d8 57

(20) TABLE-US-00002 TABLE 2 MRAM Cell Layout for 45 nm CMOS process technology Size (nm) Element Description 45 nm node cell 1 Poly-Si gate 25 2 Contact 70 70 3 Active area 80 width 4 Cell border 250 160 5 Metal 1 island 90 80 6 Via 1 70 70 7 Metal 1 line 80 8 MTJ 65 65 9 Bottom 125 80 electrode 10 Metal 2 line 80 12 Interface via 70 70 11 Metal 3 line 80 d1 40 d2 160 d3 35 d4 30 d5 80 d6 160 d7 125 d8 85

(21) TABLE-US-00003 TABLE 3 MRAM Cell Layout for 65 nm CMOS process technology Size (nm) Element Description 65 nm node cell 1 Poly-Si gate 35 2 Contact 100 100 3 Active area 110 width 4 Cell border 350 220 5 Metal 1 island 130 110 6 Via 1 100 100 7 Metal 1 line 110 8 MTJ 100 100 9 Bottom 195 130 electrode 10 Metal 2 line 120 12 Interface via 100 100 11 Metal 3 line 120 d1 55 d2 235 d3 50 d4 50 d5 110 d6 230 d7 175 d8 110

(22) In one embodiment, the MRAM cell layouts specified above may be stored in a format that supports data exchange of integrated circuit layouts. For example, the MRAM cell layouts may be stored in a Graphic. Database System (GDS) format such as in GDSII format stored a computer-readable medium. Examples of computer-readable media include but are not limited to recordable type media such as volatile and non-volatile memory devices, floppy and other removable disks, hard disk drives, optical disks (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disks, (DVDs), etc.).

(23) Although the present invention has been described with reference to specific example embodiments, it will be evident that various modifications and changes can be made to these embodiments without departing from the broader spirit of the invention.