DRIVER CIRCUIT FOR PHASE-CHANGE MEMORY CELLS AND METHOD OF DRIVING PHASE-CHANGE MEMORY CELLS

Abstract

In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.

Claims

1. A circuit comprising: a plurality of memory cells, wherein each memory cell in the plurality of memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal; a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors in the plurality of memory cells, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses; and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.

2. The circuit of claim 1, wherein each memory cell in the plurality of memory cells includes a respective electronic switch coupled in series with the phase-change memory storage element and the current-modulating transistor, the respective electronic switches being configured to receive a control signal and to be activated in response to the control signal thereby enabling injection of the programming currents into the phase-change memory storage elements.

3. The circuit of claim 2, further comprising a logic circuit configured to assert a compensation activation signal in response to the control signal, wherein the at least one current generator circuit is configured to receive the compensation activation signal and to inject the compensation current into the common control node in response to the compensation activation signal.

4. The circuit of claim 3, wherein the logic circuit is configured to de-assert the compensation activation signal upon expiry of a compensation time interval.

5. The circuit of claim 3, wherein the at least one current generator circuit comprises a first transistor and a second transistor coupled in series between the supply voltage node and the common control node, and wherein the first transistor is selectively activatable as a function of a respective selection signal and the second transistor is selectively activatable as a function of the compensation activation signal.

6. The circuit of claim 1, further comprising a plurality of current generator circuit selectively activatable to modulate a magnitude of the compensation current injectable into the common control node.

7. The circuit of claim 6, wherein the current generator circuits in the plurality of current generator circuits are selectively activatable as a function of N memory cells in the plurality of memory cells.

8. The circuit of claim 7, wherein a number of activated current generator circuits in the plurality of current generator circuits is proportional to the N memory cells in the plurality of memory cells.

9. The circuit of claim 1, wherein the at least one current generator circuit is trimmed as a function of process variations.

10. The circuit of claim 1, further comprising a process detector circuit configured to detect process variations during an operating life of the circuit, and wherein the at least one current generator circuit is trimmed as a function of the detected process variations.

11. A method for driving a plurality of memory cells, wherein each memory cell in the plurality of memory cells includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, and wherein control terminals of the current-modulating transistor in the plurality of memory cells are coupled to a common control node, the method comprising: providing a drive signal at the common control node; receiving the drive signal at the control terminals of the current-modulating transistors; injecting respective programming currents into the respective phase-change memory storage elements as a function of the drive signal, wherein the drive signal modulates the programming currents to produce SET programming current pulses and RESET programming current pulses; and injecting a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.

12. The method of claim 11, wherein each memory cell in the plurality of memory cells includes a respective electronic switch coupled in series with the respective phase-change memory storage element and the respective current-modulating transistor, wherein the method further comprises: receiving, by the electronic switches, a control signal thereby activating the electronic switches; and enabling, by the respective electronic switches, injection of the programming currents into the phase-change memory storage elements.

13. The method of claim 12, further comprising: asserting, by a logic circuit, a compensation activation signal in response to the control signal; receiving, by at least one current generator circuit, the compensation activation signal; and injecting, by the at least one current generator circuit, the compensation current into the common control node in response to the compensation activation signal.

14. The method of claim 13, further comprising de-asserting, by the logic circuit, the compensation activation signal upon expiry of a compensation time interval.

15. The method of claim 13, wherein the at least one current generator circuit comprises a first transistor and a second transistor coupled in series between the supply voltage node and the common control node, and wherein the first transistor is selectively activatable as a function of a respective selection signal and the second transistor is selectively activatable as a function of the compensation activation signal.

16. The method of claim 13, wherein the at least one current generator circuit is trimmed as a function of process variations.

17. The method of claim 13, further comprising: detecting, by a process detector circuit, process variations during an operating life of the circuit comprising the plurality of memory cells; and trimming the at least one current generator circuit as a function of the detected process variations.

18. The method of claim 11, further comprising modulating, by selectively activating a plurality of current generator circuits, a magnitude of the compensation current injectable into the common control node.

19. The method of claim 18, wherein the current generator circuits in the plurality of current generator circuits are selectively activatable as a function of N memory cells in the plurality of memory cells.

20. The method of claim 19, wherein a number of activated current generator circuits in the plurality of current generator circuits is proportional to the N memory cells in the plurality of memory cells.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0028] FIG. 1 is a time diagram exemplary of the expected behavior of the programming current of a phase-change memory cell during a SET pulse;

[0029] FIG. 2 is a time diagram exemplary of the expected behavior of the programming current of a phase-change memory cell during a RESET pulse;

[0030] FIG. 3 is a circuit block diagram exemplary of a driver circuit for programming a phase-change memory;

[0031] FIG. 4 is a time diagram exemplary of signals in a driver circuit as exemplified in

[0032] FIG. 3;

[0033] FIG. 5 is a time diagram exemplary of the behavior of the programming current of a phase-change memory cell during a SET pulse in case of an overshoot event;

[0034] FIG. 6 is a time diagram exemplary of the behavior of the programming current of a phase-change memory cell during a RESET pulse in case of an overshoot event;

[0035] FIG. 7 is a circuit diagram exemplary of a driver circuit architecture for a phase-change memory comprising a plurality of memory cells;

[0036] FIG. 8 is a circuit block diagram exemplary of a driver circuit for programming a phase-change memory according to one or more embodiments of the present description;

[0037] FIG. 9 is a time diagram exemplary of signals in a driver circuit as exemplified in

[0038] FIG. 8;

[0039] FIG. 10 is a block diagram exemplary of a process for determining the value of a compensation current in one or more embodiments of the present description;

[0040] FIG. 11A is a time diagram exemplary of a comparison between a memory cell drive signal in the case of no compensation of the memory cell programming current and the same drive signal in the case of compensation of the memory cell programming current; and

[0041] FIG. 11B is a time diagram exemplary of a comparison between a memory cell programming current in the case of no compensation of the memory cell programming current and the same programming current in the case of compensation of the memory cell programming current.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0042] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0043] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0044] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0045] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.

[0046] As used herein, the word “asserted” means that a signal has the logic level required to turn on or activate the component to which it is passed. For example, an “asserted” signal turns on a transistor, regardless of whether the transistor is n-channel or p-channel; similarly, an “asserted” signal closes a switch.

[0047] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIGS. 1 to 7.

[0048] FIG. 1 is a time diagram exemplary of the expected behavior of the programming current I.sub.CELL of a phase-change memory cell during the SET pulse. The programming current I.sub.CELL during the SET pulse is expected to increase rapidly from zero to a plateau value I.sub.1, maintain the value I.sub.1 for a time interval t.sub.1P, and then slowly return (e.g., fall) to zero during a time interval t.sub.1F.

[0049] FIG. 2 is a time diagram exemplary of the expected behavior of the programming current I.sub.CELL of a phase-change memory cell during the RESET pulse. The programming current I.sub.CELL during the RESET pulse is expected to increase rapidly from zero to a plateau value I.sub.2 (e.g., higher than I.sub.1), maintain the value I.sub.2 for a time interval t.sub.2P(e.g., equal to t.sub.1P), and then rapidly return (e.g., fall) to zero.

[0050] In conventional applications, the current values I.sub.1 and I.sub.2 and the time intervals t.sub.1P, t.sub.1F and t.sub.2P may have the following exemplary values: I.sub.2=200 μA (e.g., for the first RESET pulse), I.sub.1=120 μA (e.g., for the first SET pulse), t.sub.1P=100 ns, t.sub.1F=2.8 μs, and t.sub.2P=100 ns.

[0051] FIG. 3 is a circuit block diagram exemplary of the architecture of a driver circuit for programming a phase-change memory. The driver circuit may comprise a current output digital-to-analog converter 30 (IDAC) coupled to a driver circuit 32 configured to produce a drive signal DRV_GATE. A memory cell C1 of the phase-change memory may comprise a first transistor PH1, a second transistor PC1 and a memory storage element E1 (e.g., including a phase-change material such as GST) coupled in series between a supply voltage node that supplies a voltage V.sub.SUPPLY (e.g., equal to 3.2 V during the first SET pulse, 3.9 V during the first RESET pulse, up to 4.7 V during the third RESET pulse) and a reference voltage node (not visible in the Figures annexed herein).

[0052] The first transistor PH1 may comprise a high gain transistor (e.g., a p-channel MOS transistor) and may receive the drive signal DRV_GATE at its control (e.g., gate) terminal. The second transistor PC1 may comprise a control transistor (e.g., a p-channel MOS transistor smaller than PH1) and may receive a control signal PGDRV_ON at its control (e.g., gate) terminal. The control signal PGDRV_ON may switch between a first, asserted value (e.g., logic 0) and a second, de-asserted value (e.g., logic 1) so as to enable (e.g., make conductive) and disable (e.g., make non-conductive), respectively, the current path between the memory storage element E1 and the supply voltage node, thereby enabling and disabling the write operation of the memory storage element E1. The control transistor PC1 may thus operate substantially as an enablement switch. The drive signal DRV_GATE may be modulated by the driver circuit 32 so as to produce the desired pulses of the programming current I.sub.CELL through the memory storage element E1 when the switch PC1 is conductive.

[0053] The person skilled in the art will understand that a single memory cell C1 is exemplified in FIG. 3 for the sake of ease of illustration only, and that in one or more embodiments a plurality of N memory cells C1, . . . , CN (all having the same structure as cell C1) may be driven in parallel by the driver circuit 32 (e.g., by propagating the same drive signal DRV_GATE to all the high gain transistors PH1, . . . , PHN in the memory cells C1, . . . , CN). The parallel memory cells C1, . . . , CN may receive respective control signals PGDRV_ON. A common signal (PDPULSE) may trigger the start of operation, and a decoding scheme may select the correct program drivers. In case N program drivers need to be enabled, a number N of control signals PGDRV_ON[N:1] may be provided.

[0054] FIG. 4 is a time diagram exemplary of signals in a conventional circuit as exemplified in FIG. 3. Signals PGDRV_ON and DRV_GATE are exemplary of the control and drive signals previously discussed, applied to transistors PC1 and PH1, respectively. Signals V.sub.A and V.sub.B are voltage signals as produced at nodes NA and NB, respectively, during operation of the circuit of FIG. 3. As exemplified in FIG. 4, due to the coupling effect of the (large) high gain transistor(s) PH1 to the output node of the driver circuit 32, the drive signal DRV_GATE received at the control terminal of the transistor(s) PH1 may be affected by an undershoot when the control transistor(s) PC1 is turned on in response to the control signal PGDRV_ON being asserted (e.g., driven to a low logic value). An undershoot of the drive signal DRV_GATE may result in an overshoot of the programming current I.sub.CELL, modifying the expected plateau values as exemplified in FIGS. 5 and 6. FIG. 5 is a time diagram exemplary of the behavior of the programming current I.sub.CELL of a phase-change memory cell during the SET pulse in case of an overshoot event, where the maximum (e.g., peak) current I.sub.1,over reached during the time interval t.sub.1P is higher than the expected plateau current I.sub.1. FIG. 6 is a time diagram exemplary of the behavior of the programming current I.sub.CELL of a phase-change memory cell during the RESET pulse in case of an overshoot event, where the maximum (e.g., peak) current I.sub.2,over reached during the time interval t.sub.2P is higher than the expected plateau current I.sub.2. Overshoot events in the SET and/or RESET current pulses may negatively affect the write process of the memory storage element(s) E1, e.g., causing loss of data.

[0055] It is noted that the higher is the number of memory cells C1, . . . , CN to program (e.g., write) in parallel, the higher can be the magnitude of the current overshoot (i.e., the difference between I.sub.1,over and I.sub.1 during a SET pulse, or between I.sub.2,over and I.sub.2 during a RESET pulse). Therefore, the programming current overshoot events may be opposed by resorting to a write process where the N memory cells to be written at the same time are programmed sequentially, one after the other, as exemplified in the circuit block diagram of FIG. 7.

[0056] As exemplified in FIG. 7, the high gain transistors PH1, PH2, . . . , PHN of a set of N memory cells C1, C2, . . . , CN to be programmed at the same time may receive at their control (e.g., gate) terminals the same drive signal DRV_GATE. The control transistors PC1, PC2, . . . , PCN of the set of N memory cells C1, C2, . . . , CN may receive at their control (e.g., gate) terminals respective control signals PGDRV_ON[1], PGDRV_ON[2], . . . , PGDRV_ON[N]. By sequentially enabling the control transistors PC1, PC2, . . . , PCN via the control signals PGDRV_ON[i], PGDRV_ON[2], . . . , PGDRV_ON[N], the current overshoot events may be mitigated, but the overall write time is increased, since the N memory cells C1, C2, . . . , CN are not programmed in parallel. A delay may therefore be introduced in the write process of the phase-change memory.

[0057] FIG. 8 is a circuit block diagram exemplary of a driver circuit for phase-change memory cells according to one or more embodiments, which aim at reducing the current overshoot events without introducing a delay in the write process of plural memory cells.

[0058] Similarly to the architecture discussed with reference to FIG. 3, one or more embodiments may comprise a current output digital-to-analog converter 30 (IDAC) coupled to a driver circuit 32 configured to generate a drive signal DRV_GATE. A memory cell C1 of the phase-change memory may comprise a first transistor PH1, a second transistor PC1 and a memory storage element E1 (e.g., including a phase-change material such as GST) coupled in series between a supply voltage node that supplies a voltage V.sub.SUPPLY and a reference voltage node (not visible in the Figures annexed herein). The first transistor PH1 may comprise a high gain transistor (e.g., a p-channel MOS transistor) and may receive the drive signal DRV_GATE at its control (e.g., gate) terminal. The transconductance g.sub.m of the transistor PH1 may be, for instance, around 860 μA/V. Transistor PH1 may be a relatively large transistor, e.g., having a channel width of around 120 μm and a channel length of around 1.6 μm. For instance, transistor PH1 may comprise two transistors arranged in series, each having a channel width of around 120 μm and a channel length of around 0.85 μm. The second transistor PC1 may comprise a control transistor (e.g., a p-channel MOS transistor smaller than PH1) and may receive the control signal PGDRV_ON at its control (e.g., gate) terminal. Transistor PC1 may be a relatively small transistor, e.g., having a channel width of around 30 μm and a channel length of around 0.35 μm. The control signal PGDRV_ON may switch between a first, asserted value (e.g., logic 0) and a second, de-asserted value (e.g., logic 1) so as to enable (e.g., make conductive) and disable (e.g., make non-conductive), respectively, the current path between the memory storage element E1 and the supply voltage node, thereby enabling and disabling the write operation of the memory storage element E1. The control transistor PC1 may thus operate substantially as an enablement switch. The drive signal DRV_GATE may be modulated by the driver circuit 32 so as to produce the desired pulses of the programming current I.sub.CELL through the memory storage element E1 when the switch PC1 is conductive.

[0059] Again, the person skilled in the art will understand that a single memory cell C1 is exemplified in FIG. 8 for the sake of ease of illustration only, and that in one or more embodiments a plurality of N memory cells C1, . . . , CN (all having the same structure as cell C1) may be driven in parallel by the driver circuit 32 (e.g., by propagating the same drive signal DRV_GATE to all the high gain transistors PH1, . . . , PHN in the memory cells C1, . . . , CN).

[0060] As exemplified in FIG. 8, one or more embodiments may comprise compensation circuitry 80 configured to compensate undershoot events of the drive signal DRV_GATE and in turn mitigate overshoot events of the programming current of the memory storage elements in the cells C1, . . . , CN.

[0061] The compensation circuitry 80 may comprise a set of current generator circuits 82.sub.1, 82.sub.2, . . . , 82.sub.M (e.g., a number M of current generator circuits, equal to or different from the number N of memory cells C1, . . . , CN driven in parallel by the driver circuit 32) configured to selectively inject respective currents into the control (e.g., gate) terminals of the high gain transistors PH1, . . . , PHN of the memory cells C1, . . . , CN.

[0062] For instance, as exemplified in FIG. 8, each current generator circuit 82 may comprise a first transistor 84 (84.sub.1, 84.sub.2, . . . , 84.sub.M) and a second transistor 86 (86.sub.1, 86.sub.2, . . . , 86.sub.M) coupled in series between the supply voltage node that supplies voltage V.sub.SUPPLY and a control node N.sub.c. The control node N.sub.c is coupled to the (gate) control terminals of the transistors PH1, . . . , PHN and is driven by the output of the driver circuit 32. The transistors 84.sub.1, 84.sub.2, . . . , 84.sub.M may comprise p-channel MOS transistors and may receive respective selection signals SEL[1], SEL[2], . . . , SEL[M] at their control (e.g., gate) terminals. The transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M may comprise p-channel MOS transistors and may receive a same compensation activation signal CMPST_ON at their control (e.g., gate) terminals.

[0063] The compensation activation signal CMPST_ON may switch between a first, asserted value (e.g., logic 0) and a second, de-asserted value (e.g., logic 1) so as to enable or disable all the current generator circuits 82.sub.1, 82.sub.2, . . . , 82.sub.M (i.e., substantially enabling and disabling the programming current compensation function). The selection signals SEL[1], SEL[2], . . . , SEL[M] may switch between a first, asserted value (e.g., logic 0) and a second, de-asserted value (e.g., logic 1) so as to enable or disable the respective current generator 82.sub.1, 82.sub.2, . . . , 82.sub.M (i.e., substantially allowing modulation of the compensation current I.sub.DRV_GATE injected into node N.sub.c by the compensation circuitry 80).

[0064] Therefore, in one or more embodiments a compensation current I.sub.DRV_GATE can be injected in the control node N.sub.c to compensate undershoot events of the drive signal DRV_GATE. The compensation current may be injected for a defined time interval that may be shorter than the duration of the whole SET pulse or RESET pulse. By way of example, the compensation time interval may last some nanoseconds (1 ns=10.sup.−9 s), e.g., 3 ns to 5 ns. Substantially, the compensation activation signal CMPST_ON may be asserted (e.g., asserted low) for a certain time interval (e.g., fixed or programmable) in response to a falling edge of the control signal PGDRV_ON. While the compensation activation signal CMPST_ON is asserted (low) and the current generators 82.sub.1, 82.sub.2, . . . , 82.sub.M are consequently enabled, a compensation current I.sub.DRV_GATE is injected into node N.sub.c to reduce the undershoot of the drive signal DRV_GATE and facilitate a fast recovery of the expected level of the drive signal DRV_GATE, thereby controlling the plateau of the programming current I.sub.CELL flowing through the memory storage elements E1, . . . , EN.

[0065] Operation as discussed above is exemplified in FIG. 9, which includes time diagrams exemplary of the following signals: [0066] DRV_GATE.sub.w/o: drive signal at node N.sub.c if compensation of the programming current I.sub.CELL is disabled; [0067] DRV_GATE.sub.w: drive signal at node N.sub.c if compensation of the programming current I.sub.CELL is enabled; [0068] PGDRV_ON: control signal received at one or more of the control transistors PC1, . . . , PCN of the memory cells C1, . . . , CN; [0069] CMPST_ON: active-low compensation activation signal received at transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M of the current generators 82.sub.1, 82.sub.2, . . . , 82.sub.M; and [0070] I.sub.DRV_GATE: overall compensation current injected into node N.sub.c by the current generators 82.sub.1, 82.sub.2, . . . , 82.sub.M (i.e., by the compensation circuit 80).

[0071] In one or more embodiments, the magnitude of the compensation current I.sub.DRV_GATE may be selected as a function of certain parameters. It is noted that the magnitude of the undershoot of the drive signal DRV_GATE may depend mainly on two factors—the number N of memory cells C1, . . . , CN to be written (e.g., programmed) in parallel, and the process variations. The faster the process and the higher the number N of memory cells to write, the higher may be the undershoot of the drive signal DRV_GATE, resulting in a higher overshoot of the SET/RESET current pulses.

[0072] Therefore, in one or more embodiments where a plurality of M current generators 82.sub.1, 82.sub.2, . . . , 82.sub.M is provided in the compensation circuit 80, one or more of said current generators may be enabled at the same time by properly driving the selection signals SEL[1], SEL[2], . . . , SEL[M] as a function of the number of memory cells to write in parallel. Generally, the higher the number of memory cell, the higher the number of enabled current generators, e.g., according to a proportionality relationship.

[0073] For instance, if a single memory cell C1 is driven by the driver circuit 32, a single current generator 82.sub.1 may be enabled by setting SEL[1]=0 and all the other selection signals SEL[2], . . . , SEL[M]=1. If two memory cells C1, C2 are driven by the driver circuit 32, two current generators 82.sub.1, 82.sub.2 may be enabled by setting SEL[1], SEL[2]=0 and all the remaining selection signals SELL[3], . . . , SEL[M]=1. In general, the relationship between the number of cells to write in parallel and the number of enabled current generators 82 may vary in different embodiments. For instance, a certain number of memory cells can be grouped to be programmed while activating a single compensation current generator 82. Purely by way of example, one or more embodiments may comprise M=5 current generators 82, corresponding to five different groups of memory cells. For instance, fourteen, fifteen or sixteen memory cells in parallel may receive the same compensation current injection from a single current generator 82.

[0074] Additionally or alternatively, in one or more embodiments, the transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M may have a trimmable channel width (e.g., by providing plural transistors in parallel, each of which has a channel width W). For instance, transistor 86.sub.1 may have a channel width of W*N.sub.1, transistor 86.sub.2 may have a channel width of W*N.sub.2, and so on up to transistor 86.sub.M that may have a channel width of W*N.sub.M. In one or more embodiments, the values of parameters N.sub.1, N.sub.2, . . . , N.sub.M may be selected to trim the width of the corresponding transistors so as to compensate process variation.

[0075] In one or more embodiments, trimming of transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M may be performed at the end of the fabrication process by doing certain measurements of the transistor's electrical characteristics. Additionally or alternatively, a process detector provided on board of the device may adjust the width of transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M during the life of the device.

[0076] FIG. 10 is a block diagram exemplary of a process for determining the value of the compensation current I.sub.DRV_GATE in one or more embodiments. As exemplified in FIG. 10, a logic circuit 100 (e.g., included in the memory driver circuit) may receive as input the number N of memory cells C1, . . . , CN to be written (e.g., programmed) in parallel by the driver circuit 32. The logic circuit 100 may produce (e.g., assert and de-assert) the selection signals SEL[1], SEL[2], . . . , SEL[M] as a function of the input number N (e.g., setting to an “enable” state one or more of the selection signals SEL, possibly proportionally to N). Additionally or alternatively, a process detector circuit 102 may detect process variations and may determine the values of parameters N.sub.1, N.sub.2, . . . , N.sub.M suitable to trim the width of the transistors 86.sub.1, 86.sub.2, . . . , 86.sub.M. The compensation circuit 80 may thus be driven and/or trimmed as a function of the selection signals SEL[1], SEL[2], . . . , SEL[M] and/or the trimming parameters N.sub.1, N.sub.2, . . . , N.sub.M.

[0077] FIG. 11A is a time diagram that exemplifies a comparison between the drive signal DRV_GATE when no compensation of the programming current is applied (solid line, signal DRV_GATE.sub.w/o) and the drive signal DRV_GATE when the compensation of the programming current is applied (dashed line, signal DRV_GATE.sub.w) during a SET pulse in an exemplary case of a 16-bit memory (i.e., a memory including 16 memory cells driven in parallel by the same driver circuit 32). As exemplified in FIG. 11A, the drive signal DRV_GATE may drop from 2.36 V to about 2.29 V if no compensation is applied, and from 2.36 V to about 2.32 V if compensation is applied.

[0078] FIG. 11B is a time diagram that exemplifies a comparison between the programming current I.sub.CELL when no compensation of the programming current is applied (solid line, signal I.sub.CELL,w/o) and the programming current I.sub.CELL when the compensation of the programming current is applied (dashed line, signal I.sub.CELL,w) during a SET pulse in an exemplary case of a 16-bit memory (i.e., a memory including 16 memory cells driven in parallel by the same driver circuit 32). As exemplified in FIG. 11B, the programming current I.sub.CELL may increase from the expected plateau value 120 μA to about 145 μA (+21%) if no compensation is applied, and from 120 μA to about 128 μA (+6.5%) if compensation is applied. Therefore, one or more embodiments may reduce the programming current overshoot, e.g., from +21% to +6.5%.

[0079] One or more embodiments may thus provide one or more of the following advantages: [0080] reducing the programming current overshoot without introducing a delay in the write process of the phase-change memory; [0081] small area of the circuitry that compensates the programming current; and [0082] high reliability of the write process of the phase-change memory.

[0083] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0084] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.