Filamentary type non-volatile memory device

Abstract

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Claims

1. A filament-type non-volatile memory device, comprising a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being adapted to have: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, said filament having a low electric resistance, and a highly resistive state, in which said filament is broken, said filament having a high electric resistance,  the device comprising a shunt resistance electrically connected in parallel to said active layer, between the first electrode and the second electrode, in which: an electrically insulating spacer layer, partly covers the first electrode, a cavity being provided in this spacer layer, said cavity having a bottom, consisting of a part of the first electrode which is not covered with the spacer layer, the cavity having at least one side face which, in the spacer layer, laterally delimits the cavity, the shunt resistance is at least partially formed of a resistive material layer applied against the side face of the cavity, the active layer of the device extends parallel to the bottom of the cavity and further extends by covering said resistive material layer,  wherein the second electrode partially covers the spacer layer and fills at least part of said cavity, covering the active layer, and  wherein a layer of dielectric material is interleaved between the active layer and said resistive material layer.

2. A filament-type non-volatile memory device, comprising a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being adapted to have: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, said filament having a low electric resistance, and a highly resistive state, in which said filament is broken, said filament having a high electric resistance,  the device comprising a shunt resistance electrically connected in parallel to said active layer, between the first electrode and the second electrode, in which: an electrically insulating spacer layer, partly covers the first electrode, a cavity being provided in this spacer layer, said cavity having a bottom, consisting of a part of the first electrode which is not covered with the spacer layer, the cavity having at least one side face which, in the spacer layer, laterally delimits the cavity, the shunt resistance is at least partially formed of a resistive material layer applied against the side face of the cavity, the active layer of the device extends parallel to the bottom of the cavity and further extends by covering said resistive material layer,  wherein the second electrode partially covers the spacer layer and fills at least part of said cavity, covering the active layer, and  wherein said resistive material layer further extends on the bottom of the cavity, between the active layer and the bottom of the cavity.

3. A filament-type non-volatile memory device, comprising a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being adapted to have: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, said filament having a low electric resistance, and a highly resistive state, in which said filament is broken, said filament having a high electric resistance,  the device comprising a shunt resistance electrically connected in parallel to said active layer, between the first electrode and the second electrode, in which: an electrically insulating spacer layer, partly covers the first electrode, a cavity being provided in this spacer layer, said cavity having a bottom, consisting of a part of the first electrode which is not covered with the spacer layer, the cavity having at least one side face which, in the spacer layer, laterally delimits the cavity, the shunt resistance is at least partially formed of a resistive material layer applied against the side face of the cavity, the active layer of the device extends parallel to the bottom of the cavity and further extends by covering said resistive material layer,  wherein the second electrode partially covers the spacer layer and fills at least part of said cavity, covering the active layer, and an electrically insulating block which divides the cavity into at least a first sub-cavity and a second sub-cavity, and a third electrode, electrically insulated from the second electrode,  and wherein the second electrode fills the first sub-cavity whereas the third electrode fills the second sub-cavity.

4. The device according to claim 1, wherein the active layer comprises a conducting filament, which electrically interconnects the first electrode to the second electrode, the device having: a low resistive state, in which the conducting filament uninterruptedly extends from end to end through the active layer, said filament having a low electric resistance, and a highly resistive state, in which said filament is broken, said filament having a high electric resistance, said shunt resistance being electrically connected in parallel to said filament, between the first electrode and the second electrode.

5. The device according to claim 1, wherein the shunt resistance is lower than or equal to the high resistance of the filament.

6. The device according to claim 4, wherein the shunt resistance is higher than or equal to the low resistance of the filament.

7. The device according to claim 1, wherein the shunt resistance is lower than 100 kiloOhms.

8. The device according to claim 1, wherein the shunt resistance is higher than 12.9 kiloOhms.

9. The device according to claim 1, wherein the active layer, which extends from the first electrode to the second electrode, is laterally delimited by at least one side face, and wherein the resistive material layer, which forms at least part of the shunt resistance, extends from the first electrode to the second electrode, in parallel to the side face of the active layer.

10. The device according to claim 9, wherein the dielectric material layer is interleaved between the side face of the active layer and said resistive material layer.

11. The device according to claim 7, wherein said resistive material has an electric conductivity between 0.1 ohm×centimetre and 10 ohms×centimetres.

12. The device according to claim 7, wherein the active layer is formed by a metal oxide.

13. The device according to claim 2, wherein the active layer comprises a conducting filament, which electrically interconnects the first electrode to the second electrode, the device having: a low resistive state, in which the conducting filament uninterruptedly extends from end to end through the active layer, said filament having a low electric resistance, and a highly resistive state, in which said filament is broken, said filament having a high electric resistance, said shunt resistance being electrically connected in parallel to said filament, between the first electrode and the second electrode.

14. The device according to claim 13, wherein the shunt resistance is higher than or equal to the low resistance of the filament.

15. The device according to claim 2, wherein the shunt resistance is lower than or equal to the high resistance of the filament.

16. The device according to claim 2, wherein the shunt resistance is lower than 100 kiloOhms.

17. The device according to claim 2, wherein the shunt resistance is higher than 12.9 kiloOhms.

18. The device according to claim 2, wherein said resistive material has an electric conductivity between 0.1 ohm×centimetre and 10 ohms×centimetres.

19. The device according to claim 2, wherein the active layer is formed by a metal oxide.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The figures are set out by way of indicating and in no way limiting purposes.

(2) FIG. 1 schematically represents a filament type memory cell, more precisely of the OxRam type, in a cross-section view,

(3) FIG. 2 shows median values of the low resistances R.sub.L and high resistances R.sub.H of a conducting filament of 200 memory cells of FIG. 1, obtained during 10 million successive writing and resetting cycles of the memory cells,

(4) FIG. 3 represents an electric circuit equivalent to a filament type memory device, the device being in a highly resistive state,

(5) FIG. 4 represents an electric circuit equivalent to the same filament type memory device, the device being in a low resistive state,

(6) FIG. 5 schematically represents a first embodiment of the memory device in question, in a cross-section view,

(7) FIG. 6 schematically represents a second embodiment of the memory device, in a cross-section view,

(8) FIG. 7 schematically represents a third embodiment of the memory device, in a cross-section view,

(9) FIG. 8 schematically represents a fourth embodiment of the memory device, in a cross-section view,

(10) FIG. 9 schematically represents a fifth embodiment of the memory device, in a cross-section view.

DETAILED DESCRIPTION

(11) As already mentioned, the present technology relates to a filament type non-volatile memory device, for example an OxRam type, or CB-RAM type device, in which fluctuations in the high resistance of the device R.sub.TOT,H, from one resetting cycle to the other, are made particularly low by virtue of a shunt resistance R.sub.//, electrically connected in parallel to the conducting filament present in the active layer of the device.

(12) Different embodiments of this device, which respectively bear reference numerals 61; 71; 81; 91; 101, are schematically represented in FIGS. 5 to 9. Geometry and arrangement of some elements of the device vary, from one embodiment to the other, but these different embodiments have numerous common features. From one embodiment to the other, identical or corresponding elements will therefore be referred to using the same reference signs and will not necessarily be described each time.

(13) In each of these embodiments, the device 61; 71; 81; 91; 101 comprises: a first electrode 62; 72, a second electrode 63; 73; 103, and an active layer 64; 74; 140, 140′ which extends between the first electrode and the second electrode, the abovementioned conducting filament 641; 741; 141, 141′ passing through this active layer to electrically interconnect the first electrode to the second electrode.

(14) The active layer is electrically insulating, except at the filament in question.

(15) The term layer can for example refer to a stretch of material delimited by two opposite surfaces parallel to each other, or substantially parallel to each other (that is parallel within 15 degrees).

(16) As indicated above, the device 61; 71; 81; 91; 101 also comprises a shunt resistance R.sub.//, electrically connected in parallel to the filament 641; 741; 141, 141′, between the first electrode and the second electrode. In the embodiments represented in the figures, this shunt resistance is formed of one or more layers 65; 75; 95; 105, 105′ of slightly electrically conductive, resistive material. The resistive material layer(s) each extend from the first electrode to the second electrode.

(17) The first electrode 62; 72 and the second electrode 63; 73; 103 are electrically conducting. They are for example formed of one or more metal materials, such as Titanium Ti or platinum Pt. The electrodes can in particular comprise one or more metal layers.

(18) In the case where the device is an OxRam type device, the active layer 64; 74; 140, 140′ is more precisely formed of a metal oxide, for example tantalum or hafnium oxide. And in the case where the device is a CB-RAM type device, the active layer is formed of a solid electrolyte, in which metal cations can be relocated and reduced to form the conducting filament. The active layer can have a thickness e between 3 and 50 nanometres.

(19) In addition to the abovementioned metal layer(s), the first electrode 62; 72 and/or the second electrode 63; 73; 103 can comprise, on the side of the active layer, one or more auxiliary layers (not represented in the figures) such as a reservoir layer likely to exchange oxygen vacancies with the active layer, or such as a protective layer preventing oxygen from migrating.

(20) The device 61; 71; 81; 91; 101 has: a low resistive state, in which the conducting filament 641; 741; 141, 141′ uninterruptedly extends from end to end through the active layer 64; 74; 140, 140′, the filament having a low electric resistance R.sub.L, and a highly resistive state, in which the filament 641; 741; 141, 141′ is broken, the filament having a high electric resistance R.sub.H.

(21) As will be detailed in the following, the shunt resistance R.sub.// is selected higher than the low resistance of the filament R.sub.L.

(22) As explained in the part entitled “summary” and as illustrated by FIG. 3, in its highly resistive state, the total electric resistance of the device, R.sub.TOT,H, is that of an equivalent electric circuit comprising the shunt resistance R.sub.//, and, connected in parallel, the high resistance of the filament, R.sub.H. The high resistance of the device R.sub.TOT,H is therefore equal to 1/(1/R.sub.//+1/R.sub.H).

(23) By virtue of the shunt resistance R.sub.//, relative fluctuations in the high resistance of the device R.sub.TOT,H, from one resetting cycle to the other for a same device, are therefore lower than relative fluctuations in the high resistance of the filament R.sub.H (more explanations about it will be given in the part setting out the “summary”). Thus limiting variations in the high resistance of the device R.sub.TOT,H makes data storage in the device more reliable, and makes stored data reading simpler to perform.

(24) Variations in the high resistance of the device R.sub.TOT,H, from one resetting cycle to the other, are all the more strongly reduced as the ratio R.sub.///R.sub.H is small. This is the reason why the shunt resistance R.sub.// is here selected lower than the high resistance of the filament R.sub.H. Here, the shunt resistance R.sub.// is more precisely lower than the average of the high resistance of the filament R.sub.H (resistance of which it is reminded that it fluctuates from one resetting cycle to the other).

(25) When the device is an OxRam type device, the device can for example be manufactured so that the shunt resistance R.sub.// is lower than 100 kiloOhms. In this type of device, the high resistance of the filament R.sub.H has an average value which is generally higher than or equal to 100 kiloOhms (ref. FIG. 2). Manufacturing the device so that the shunt resistance R.sub.// is lower than 100 kOhms therefore generally ensures that the shunt resistance is lower than the average of the high resistance of the filament R.sub.H.

(26) In its low resistive state, the device 61; 71; 81; 91; 101 has a total electric resistance, R.sub.TOT,L which is that of an equivalent electric circuit comprising the shunt resistance R.sub.//, and, being connected in parallel, the low resistance of the filament R.sub.L (see FIG. 4). The low resistance of the device, R.sub.TOT,L, is therefore equal to 1/(1/R.sub.//+1/R.sub.L).

(27) The deviation R.sub.TOT,H-R.sub.TOT,L between the high resistance of the device R.sub.TOT,H and its low resistance R.sub.TOT,L is all the lower as the shunt resistance R.sub.// is low.

(28) This decrease in the deviation between R.sub.TOT,H and R.sub.TOT,L, when the shunt resistance R.sub.// decreases, is well understood in the particular case for which the shunt resistance R.sub.// is both much smaller than the high resistance of the filament R.sub.H, and much larger than the low resistance of the filament R.sub.L. Indeed, in this case, the high resistance of the device, R.sub.TOT,H, is nearly equal to the shunt resistance R.sub.//, whereas the low resistance of the device, R.sub.TOT,L is nearly equal to the low resistance of the filament R.sub.L. In this situation, it is well understood that decreasing the shunt resistance R.sub.//, by making it approaching the low resistance of the filament R.sub.L, makes the high resistance of the device R.sub.TOT,H closer to the low resistance of the device R.sub.TOT,L.

(29) A significant deviation between R.sub.TOT,H and R.sub.TOT,L facilitates the reading operation of the device, since the highly resistive and low resistive states of the device then correspond to resistance levels much different from each other.

(30) So, to keep a significant deviation R.sub.TOT,H-R.sub.TOT,L, the shunt resistance R.sub.// is here selected higher than the low resistance of the filament R.sub.L.

(31) In practice, when the device is of the OxRAM type, the low resistance of the filament R.sub.L is about a few kiloOhms.

(32) The low resistance of the filament R.sub.L obtained at the end of the manufacturing of the device, after the “forming” step, can vary quite significantly from one device to the other, even if the devices are initially identical.

(33) But even if the value of the low resistance of the filament R.sub.L, which will be obtained at the end of manufacturing, cannot be accurately predicted, it is known that it remains lower than 12.9 kiloOhms. This value is that of the resistance quantum Ro, equal to h/(2e.sup.2), h being Planck constant and e an electron charge. This resistance value corresponds, within a few variations, to the electric resistance of an elementary junction between two atoms of a conducting material, in contact with each other. When the conducting filament has been reformed (after a SET step), the resistance of the filament is therefore still lower than 12.9 kiloOhms (since at least one atom of the upper part of the filament then comes in contact with an atom of the lower part of the filament).

(34) In the embodiments set forth here, the device 61; 71; 81; 91; 101 is manufactured so that the shunt resistance R.sub.// is higher than 12.9 kiloOhms. As explained above, this generally ensures that the shunt resistance R.sub.// is higher than the low resistance of the filament R.sub.L (in spite of the abovementioned variability of the value of R.sub.L from one device to the other).

(35) As already indicated, the shunt resistance R.sub.// will also enable stability of the low resistive state of the device to be improved.

(36) Indeed, part of the electric current which will pass through the device will then pass through the shunt resistance R.sub.//, thus reducing the intensity of current which will pass through the filament, and therefore its temperature rise. In this regard, it will be noted that a bias voltage is generally applied to the memory device (when the memory is electrically powered), and that the total electric current which passes through the device then has a more or less fixed value (typically of a few hundred microAmperes). Since this total current has a substantially fixed value, adding the shunt resistance will therefore actually enable the electric current in transit through the filament to be reduced, by diverting a substantial part of the total electric current towards the shunt resistance R.sub.//, thus reducing the temperature rise in question.

(37) The geometric structure of the device 61; 71; 81; 91; 101 is now set forth in more detail, with reference to FIGS. 5 to 9.

(38) In these embodiments, the active layer 64; 74; 140, 140′ and the second electrode 63; 73; 103 are stacked on the first electrode 62; 72, which is planar. In a direction perpendicular to the main surface of the first electrode 62; 72, the active layer is delimited by the first and second electrodes; the active layer is interleaved, and even sandwiched between these two electrodes 67, 72, 63, 73. And laterally, the active layer 64; 74; 140, 140′ is delimited by side faces 643, 643′; 743, 743′; 143, 143′. Stated differently, the extension of the active layer, in a plane parallel to the first electrode, is limited by these side faces. In the embodiments represented in the figures, these side faces 643, 643′; 743, 743′; 143, 143′ extend in planes perpendicular to the first electrode 62; 72.

(39) In the embodiment illustrated by FIG. 5, the second electrode 63 of the device 61 is planar, and is disposed parallel to the first electrode 62. The active layer 64, which extends between these two electrodes, is also planar and extends in a plane parallel to the first electrode 62. And the shunt resistance R.sub.// is formed of a same resistive material layer 65 which forms a one-piece coating extending throughout the perimeter of the active layer 64, by surrounding it laterally. The active layer 64 has for example a cylindrical shape and is surrounded by the resistive layer 65 forming the shunt resistance. The cross-section of the cylinder can be circular, square or rectangular for example.

(40) In this case, the resistive material layer 65 is directly applied against the side faces 643, 643′ of the active layer 64. It is here understood that in the case of a circular cross-section cylindrical structure such as described above, there is only one continuous wall forming the resistive material layer 65 and laterally coming against the active layer. Mentioning several side faces is therefore in no way limiting and above all aims at facilitating understanding of the cross-section view figures.

(41) Alternatively, a layer of electrically insulating dielectric material, could however be interposed between the side faces 643, 643′ of the active layer 64 and the layer 65 of resistive material, as is the case in the embodiments of FIGS. 6 to 8 described later.

(42) In the embodiments illustrated by FIGS. 6 to 8, the shunt resistance R.sub.// is also made as a resistive material layer 75; 95 forming a one-piece coating which extends throughout the periphery of the active layer 74 by surrounding it laterally (this type of coating is sometimes called “liner” in the field of microelectronics). This configuration is well adapted to manufacturing techniques used in micro-electronics, as well as that of FIG. 5.

(43) In the case of FIG. 6, the layer 75 of resistive material is directly applied against the side faces 743, 743′ of the active layer 74, in contact with the same.

(44) And in the case of FIGS. 7 and 8, the resistive material layer 75; 95 is separated from these side faces 743, 743′ by a dielectric material layer 87, that is of an electrically insulating material.

(45) Just like the embodiment of FIG. 5, in the embodiments of FIGS. 7 and 8, the resistive material layer which forms the shunt resistance could be formed of a resistive material layer which only extends on some of the side faces of the active layer. The shunt resistance could also be formed by two resistive material layers disjoined from each other, and which extend on two different side faces of the active layer.

(46) In the embodiment illustrated by FIG. 9, the device 101 comprises two memory cells, and therefore can store two binary data, independently of each other. It therefore comprises a first active layer 140 and a second active layer 140′. A conducting filament 141, 141′, such as described above, is formed in each of these active layers 140, 140′. The device 101 also comprises a first shunt resistance and a second shunt resistance respectively formed by a first resistive material layer 105, and of a second resistive material layer 105′. The first resistive material layer 105 extends along a side face 143 of the first active layer 140, parallel to this side face. And the second resistive material layer 105′ extends along a side face 143′ of the second active layer 140′, parallel to this side face.

(47) In the embodiments represented in the figures, each layer 65; 75; 95; 105, 105′ of resistive material extends perpendicular relative to the first electrode 62; 72.

(48) In the embodiments of FIGS. 6 to 9, the device 71; 81; 91; 101 has a particular geometric structure, well adapted to manufacturing techniques used in micro-electronics, and conducive to obtaining small dimensions memory devices (typically occupying a surface area lower than a few square microns). This particular structure is set forth below.

(49) In the embodiments of FIGS. 6 to 9, the second electrode 73; 103; 103′ is separated of the first electrode 72 by an electrically insulating spacer layer 76. A cavity 762, which forms a kind of bowl, is provided in this spacer layer 76. The active layer 74; 140, 140′ then extends along the walls of this cavity, at the bottom as well as on the edges of the cavity. The active layer 74; 140, 140′ at least partly lines the walls of the cavities 762. As for the second electrode 73; 103, it partly covers the spacer layer and at least partly fills the cavity 762 in question to cover the active layer.

(50) This configuration enables the active layer 74; 140, 140′ to be easily made through conformal deposition, and with a large freedom regarding the thickness of this layer. The thickness of the active layer 74; 140, 140′, and even the total thickness of all the layers comprising the active layer and possible abovementioned auxiliary layers (reservoir layer and protective layer, for example), can in particular have a much smaller thickness than the thickness h of the spacer layer, for example lower than half or the third of the thickness h.

(51) Incidentally, the active layer 74; 140, 140′, the resistive material layer (75; 95; 105, 105′), and/or the dielectric material layer can have a low thickness relative to the extension (dimensions) of the layer considered, parallel to this layer (small thickness of the layer relative to its surfacic extent).

(52) The spacer layer 76 partly covers the first electrode 72. The bottom 764 of the cavity 762 consists of a part of the first electrode 72 which is not covered with the spacer layer 76. The cavity also has side faces 763, 763′, which laterally delimit the cavity. Here, these side faces are perpendicular to the first electrode 72.

(53) In the case of FIGS. 6 to 8, the resistive material layer 75; 95, which forms the shunt resistance R.sub.//, is applied on all the side faces 763, 763′ of the cavity (and thus forms a one-piece coating which covers the side face of the cavity throughout its periphery). As previously explained, the plurality of side faces 763, 763′ is here given by way of example to illustrate the cross-section views, it being understood that the resistive material layer 75, 95 generally has a single face in the case of a substantially circular cross-section cylinder (or 4 faces in the case of a square or rectangular cross-section cylinder) which surrounds the active layer.

(54) In the embodiments of FIGS. 6 and 7, the layer 75 of resistive material covers the side faces 763, 763′ of the cavity, but not its bottom 764.

(55) And in the embodiment illustrated by FIG. 8, the layer 95 of resistive material, applied to the side faces 763, 763′ of the cavity, is continued to the bottom of the cavity 762 by covering the first electrode 72. The resistive material layer 95 then forms a one-piece coating which lines all the walls of the cavity 762, that is both the bottom 764 of the cavity and its side walls 763, 763′. At the bottom 764 of the cavity, the resistive material is directly in contact with the first electrode 72, and is covered with the active layer 74.

(56) Regarding now the active layer 74, in the embodiments of FIGS. 6 to 8, it extends parallel to the bottom 764 of the cavity, on the whole surface of the bottom, and then is continued, perpendicular to the bottom of the cavity, by covering the resistive material layer 75; 95 (which is applied against the side walls 763, 763′ of the cavity).

(57) In the embodiments of FIGS. 6 to 8, the second electrode 73 partly covers the spacer layer 76, and fills the part of the cavity 762 left free by the abovementioned 74, 75; 95, and possibly 87 layers. In particular, the metal(s), which form at least part of the second electrode 76, fills in at least a part of this cavity.

(58) In the embodiment illustrated by FIG. 6, the active layer 74 is directly applied against the bottom 764 of the cavity, in contact with the first electrode 72. And the part of the active layer 74 which extends perpendicular to the bottom of the cavity, and which covers the resistive material layer 75, is directly applied against the resistive material layer 75, in contact with it.

(59) In the device 71 illustrated by FIG. 6, during the “forming” step, the filament 741 is formed between the first electrode 72 and the second electrode 73, generally in the part of the active layer 74 which extends parallel to the bottom of the cavity (part of the active layer 74 applied against the first electrode 72).

(60) But, in this device 71, the filament can sometimes be formed (with a lower probability) between the second electrode 73 and the resistive material layer 75, in the part of the active layer 74 which extends transversally, perpendicular to the first electrode 72. The value of the shunt resistance, which is finally connected in parallel to the filament, is thereby modified, and furthermore, this adds a resistance in series with the filament, the value of which can be quite large. When the filament is formed this way, the values of the high and low resistances of the device can therefore be modified relative to what would be expected given the dimensions h and a of the resistive material layer 75. The operation of the device may therefore be no longer the optimum.

(61) The probability that the filament is formed in the part of the active layer 74 which extends vertically, that is perpendicular to the first electrode 72, is however low. Nevertheless, it is interesting to avoid for sure forming the filament in this part of the active layer 74.

(62) For this reason, it is provided, in the embodiments illustrated by FIGS. 7 and 8 (as well as in that illustrated by FIG. 9), interposing the dielectric material layer 87 between the resistive material layer 75; 95 on the one hand, and the part of the active layer 74 which extends vertically on the other hand. This is to ensure that the filament 741 is formed in the part of the active layer 74 which extends parallel to the bottom of the cavity 762. Moreover, the dielectric material layer 87 enables the resistive material layer 75; 95 to be protected, by avoiding putting it directly in contact with the active layer 74 (active layer which can for example contain oxygen). The layer 87 of dielectric material can for example be made of silicon nitride Si.sub.3N.sub.4, which makes up an efficient chemical (and electrical) barrier.

(63) The device 81 of the embodiment of FIG. 7 is identical to the device 71 of FIG. 6, except that it comprises the abovementioned layer 87 of dielectric material.

(64) The device 91 of the embodiment of FIG. 8 is identical to the device 81 of FIG. 7, except that the layer 95 of resistive material extends not only on the side walls 763, 763′ of the cavity, but also on the bottom 764 of the cavity, as already indicated. At the bottom of the cavity, the layer 95 of resistive material is therefore interposed between the active layer 74 and the first electrode 72. From an electric point of view, this results in adding an additional electric resistance, in series with the resistance of the filament 71. This additional resistance is low (in the order of the kiloOhms or less), compared to the low resistance of the filament R.sub.L, as well as compared to the shunt resistance R.sub.//, and therefore does not modify the operation of the device. But it enables the “forming” step, which is like a kind of intentional breakdown of the active layer, to be less violent from an electric point of view. Thus, electric stress experienced by the active zone will be lessened, by virtue of this additional resistance. Besides, before the forming operation, the electric field is mainly located across the active zone, but after creating the filament, there is a large field across a brittle filament. Consequently, adding this additional resistance in series enables the electrical field to be distributed on the filament and additional resistance in series. It will be noted incidentally that the active layer 741 electrically interconnects the first electrode 72 to the second electrode 73 indirectly, through this small additional resistance located between the active layer 74 and the first electrode 72. It will also be noted that this structure, with the layer 95 of resistive material that extends not only on the side wall(s), but also on the bottom of the cavity, further facilitates manufacturing the device, since it is not necessary in this case to etch the layer of resistive material, after conformally depositing the same (indeed, in this case, it is not necessary to remove the part of this layer which extends parallel to the bottom).

(65) Regarding the device 101 of FIG. 9, it is similar to that of FIG. 7, but the cavity 762 is divided into a first sub-cavity 765, and a second sub-cavity 765′ by an electrically insulating block 108, for example a filling oxide. This enables two memory cells to be made in the same cavity. Here, the electrically insulating block 108 is applied against the first electrode 72, and extends up to the top of the cavity 762.

(66) In the first sub-cavity 765, the side face 763 of the cavity is covered with the first abovementioned layer 105 of resistive material (which forms the first shunt resistance of the device). Here, this layer extends only on this side face 763. A first dielectric material layer 107 covers the first resistive material layer 105. The first active layer 140 extends horizontally, on the bottom of the first sub-cavity 765, and, vertically, against the first dielectric material layer 107. The second electrode 103 partly covers the spacer layer 76, and fills the part of the first sub-cavity 765 left free by the abovementioned layers 105, 107 and 140, covering the first active layer 140. In particular, the metal(s), which form at least a part of the second electrode, fills in at least a part of the first sub-cavity. The ensemble of elements located between the first electrode 72 and the second electrode 103 forms the first memory cell of the device.

(67) The structure of the device at the second sub-cavity 765′ is similar to what has just been set forth for the first sub-cavity 765.

(68) More precisely, in the second sub-cavity 765′, the side face 763′ of the cavity is covered with the second resistive material layer 105′ (which forms the second shunt resistance of the device). Here, this layer only extends on this side face 763′. A second dielectric material layer 107′ covers the second resistive material layer 105′. The second active layer 140′ extends horizontally, on the bottom of the second sub-cavity 765′, and, vertically, against the second dielectric material layer 107′. A third electrode 103′, electrically insulated from the second electrode 103 (so that both memory cells can be addressed independently) partly covers the spacer layer 76 and fills the part of the second sub-cavity 765′ left free by the abovementioned layers 105′, 107′ and 140′, covering the second active layer 140′. The ensemble of elements located between the second electrode 72 and the third electrode 103′ forms the second memory cell of the device 101.

(69) Alternatively, the device of FIG. 10 could comprise more than two distinct memory cells.

(70) In the different embodiments represented in FIGS. 6 to 9, the spacer layer 76 has a thickness h. The resistive material layer 75; 95; 105, 105′ which forms the shunt resistance therefore has a length, in the direction followed by electric current, equal to the height h. The resistive material layer 75; 95; 105 beside has a thickness a, and a cross-sectional area a×b (inlet cross-sectional area into the layer, at the second electrode 73; 103).

(71) The value of the shunt resistance R.sub.// is therefore given, as a good approximation, by the following formula F2:

(72) $\begin{array}{cc}{R}_{//}=\frac{\rho h}{a\times b}& \left(\mathrm{F2}\right)\end{array}$

(73) where ρ is the resistivity of the resistive material in question.

(74) In practice, the height h of the spacer layer 76 can for example be between 30 and 100 nanometres, the thickness a of the active layer can be between 3 and 30 nanometres, and the “width” b of the layer (transverse extension of the layer) is typically 10 times larger than its thickness a. The amount h/(a×b) is then in the order of 10.sup.8 metres. To obtain the order of magnitude desired for the shunt resistance R.sub.//, typically between 10 and 100 kiloOhms, a resistive material having a resistivity ρ in the order of 1 Ohm×centimetre is therefore well adapted.

(75) More generally, a resistive material having a resistivity p between 0.1 Ohm×centimetre and 10 Ohm×centimetres enables a value well adapted for the shunt resistance R.sub.// to be obtained, for small size memory devices such as described above, made by techniques of thin film deposition.

(76) The resistive material can be a semi-conductor material, which enables a device to be conveniently manufactured.

(77) But the resistivity of a semiconductor material varies quite strongly with temperature. Thus, if the device is to be used in an environment subjected to strong temperature variations, for example in an engine compartment of automobile vehicle, the layer of resistive material will rather be made, for example, of metal carbide (carbon proportion being adjusted so as to obtain the desired resistivity value), which enables a resistivity value, and therefore a shunt resistance R.sub.//, stable over an extended temperature range, to be obtained. The embodiments of the device 71; 81; 91; 101, respectively represented in FIGS. 6 to 9, can be each produced by means of a manufacturing method comprising, inter alia, the following steps, performed in this order: S1: making the first electrode 72, S2: depositing the spacer layer 76 onto the first electrode 72, S3: making the cavity 762, by etching the spacer layer, S4: conformally depositing the resistive material for forming the shunt resistance R.sub.//, against the bottom 764 and the side face 763 (or side faces) of the cavity 762, S6: conformally depositing the active layer 74; 140, 140′, the active layer then extending parallel to the bottom 764, and continuing parallel to the side face of the cavity (or parallel to the side faces of the cavity) by covering the resistive material layer, S7: making the second electrode 73; 103, 103′, this step here comprising the following sub-steps: S71: making a part of the second electrode 73; 103, this part filling the whole volume let free in the cavity 762, or in the first sub-cavity 105, and covering the active layer 74; 140, this part of the second electrode being made by depositing one or more electrically conducting materials, S72: planarising the free upper surface of the device, for example by chemical mechanical polishing (CMP), S73: depositing another part of the second electrode 73; 103, which covers the cavity 762 or the first sub-cavity 105, and which also covers a part of the spacer layer 76.

(78) Optionally, step S4 can comprise an anisotropic etching sub-step for removing the horizontal part of the layer of resistive material (that is the part of this layer which extends parallel to the bottom 764 of the cavity). This etching is made before depositing the active layer. This sub-step is made when it is desired to manufacture a memory device such as 71 or 81 of FIG. 6 or of FIG. 7, in which the resistive material layer is not interposed between the active layer 74 and the first electrode 72.

(79) The method can also comprise a step S5 of making the above-described dielectric material layer 87; 107, 107′, this step being carried out after step S4, and before step S6. Step S5 comprises the following sub-steps: conformally depositing the layer 87; 107, 107′ of dielectric material, so that this layer extends parallel to the bottom 764 of the cavity (against the bottom, or against the horizontal part of the resistive layer) and continues parallel to the side face 763 (or side faces), by covering the resistive material layer 75; 95; 105, 105′ and etching the layer 87; 107, 107′ of dielectric material, through anisotropic etching, so as to remove the part of this layer which extends parallel to the bottom of the cavity 762.

(80) Optional step S5 is carried out when it is desired to obtain a memory device such as 81; 91; 101 of FIGS. 7 to 9, for example.

(81) In the embodiments of FIGS. 6 to 8, the active layer 74 is as a single piece and covers the bottom as well as the side face, or all of the side faces of the cavity 762. It can be made conveniently, through conformal deposition. Thus, upon manufacturing the device 71; 81; 91 in question, the manufacturing method does not include an intermediate step of modifying the tactive layer conformation, between step S6 and step S7.

(82) The method which has just been described can include other steps, for example a “forming” step, in addition to those described above.