Method for improving digital radio mondiale (DRM) acquisition time

Abstract

A system and method for improving the DRM (Digital Radio Mondiale) signal acquisition time stores the demodulated DRM signal and accesses it from memory in order to avoid the additional time taken in waiting for service description channel (SDC) data. The system includes an antenna to receive a DRM signal. A tuner tunes the frequency of receiver to a desired range. An asynchronous sample rate converter (ASRC) converts the sampling rate of the received signal to a demodulator sampling rate. A demodulator demodulates the received signal. A memory stores the demodulated signal for reuse. A channel splitter splits the received signal into a fast access channel (FAC), a service description channel (SDC), and a main service channel (MSC). A channel decoder decodes the channel split data. A middleware and an application parses and processes the data in order to output the processed data.

Claims

1. A system for improving acquisition time of a digital radio mondiale (DRM) receiver (100), comprising: a. an antenna (10) to receive a digital radio signal; b. a tuner (20) to tune said receiver (100) to a frequency to receive said digital radio signal; c. a processor (30) to process said digital radio signal, wherein said processor (30) comprises: i. a demodulator (32) to demodulate said digital radio signal received at said receiver at said frequency and store the demodulated radio signal in a memory unit; ii. a channel splitter (33) to split the demodulated radio signal into multiple separate channels; iii. one or more channel decoders (34) to decode the data of the demodulated radio signal split to a corresponding channel of said multiple separate channels from said channel splitter (33); and iv. a middleware (351) and application (352) to parse the decoded data, and to process the parsed decoded data to send as audio and data; d. one or more memory units (40) including the memory unit to store the demodulated radio signal from said demodulator (32) prior to being split by said channel splitter, wherein the processor loads the stored demodulated radio signal based upon a result provided by the one or more channel decoders for processing by the channel splitter; and e. one or more output devices (50) to output said processed audio and data.

2. The system as claimed in claim 1, wherein said processor (30) further comprises an Asynchronous Sample Rate Converter (ASRC) (31) to convert the sampling rate of said received digital radio signal to a sample rate of said demodulator.

3. The system as claimed in claim 1, wherein said channel splitter (33) splits the demodulated radio signal into a Fast Access Channel, a Service Description Channel and a Main Service Channel.

4. The system as claimed in claim 1, wherein said one or more channel decoders (34) includes a fast access channel (FAC) decoder (341), a service description channel (SDC) decoder (342) and a main service channel (MSC) decoder (343).

5. A method for improving acquisition time of a digital radio mondiale (DRM) receiver, the method comprising the steps of: tuning said receiver to a frequency using a tuner to obtain a DRM signal; receiving the DRM signal through an antenna (10) at said receiver (100); converting the sample rate of said DRM signal to a demodulator sample rate using an asynchronous sample rate converter (ASRC) (31); demodulating the converted signal from said ASRC (31) using a demodulator (32); storing the demodulated signal in a memory-1 (40) for reuse; splitting the demodulated signal into a fast access channel (FAC), a service description channel (SDC), and a main service channel (MSC) using a channel splitter (33); decoding channel split data for the split demodulated signal of each channel using channel decoders (34); accessing the memory-1 (40) to retrieve the stored demodulated signal when a first received frame ID is Frame-0 without SDC data, Frame-1 or Frame-2; using said channel splitter to split the retrieved demodulated signal from said memory-1 (40) when the SDC data is not available and to store MSC data into a memory-2 (40); parsing said decoded channel split data from the channel decoders and processing the parsed channel split data as audio and data in middleware (351); sending the processed data to output devices through an application (352); and outputting the processed data through one or more output devices (50).

6. The method as claimed in claim 5, wherein said decoding using channel decoders includes using a FAC decoder (341), a SDC decoder (342) and a MSC decoder (343).

7. The method as claimed in claim 6, wherein said first received frame ID is obtained by parsing FAC decoded data from said FAC decoder (341).

8. The method as claimed in claim 6, wherein said MSC decoder (343) decodes the stored MSC data from memory-2 (40), if present, and decodes the MSC data from a current frame.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The objective of the present invention will now be described in more detail with reference to the accompanying drawings, in which:

(2) FIG. 1 shows a block diagram of DRM receiver of the present invention;

(3) FIG. 2 shows a detailed block diagram of DRM receiver with internal components of the processor unit;

(4) FIG. 3 shows the structure of DRM transmission super frame in case of robustness modes A, B, C, D;

(5) FIG. 4A shows a portion of the overall flow of the present invention;

(6) FIG. 4B shows a portion of the overall flow of the present invention;

(7) FIG. 5A shows a graphical representation of time taken for executing frames under condition (i) where the first received transmission frame is Frame-0 and SDC is absent in case of long interleaving for Robustness Modes A, B, C, D;

(8) FIG. 5B shows a graphical representation of time taken for executing frames under condition (ii) where the first received transmission frame is Frame-1 in case of long interleaving for Robustness Modes A, B, C, D; and

(9) FIG. 5C shows a graphical representation of time taken for executing frames under condition (iii) where the first received transmission frame is Frame-2 in case of long interleaving for Robustness Modes A, B, C, D.

REFERENCE NUMERALS

(10) 100: DRM receiver 10: Antenna 20: Tuner 30: Processor 31: Asynchronous Sample Rate Converter (ASRC) 32: Demodulator 33: Channel splitter 34: Channel decoder 341: FAC decoder 342: SDC decoder 343: MSC decoder 35: Middleware & Application 351: Middleware 352: Application 40: Memory (memory-1 & memory-2) 50: Output devices

DETAILED DESCRIPTION OF THE PRESENT INVENTION

(11) The present invention proposes an effective system and method for improving the acquisition time of the DRM signal at DRM receiver in order to enhance the user experience.

(12) In general, Digital Radio Mondiale (DRM) is a digital radio standard used in all frequency bands (AM and VHF) above and/or below 30 MHz. The DRM is a high quality digital replacement of analogue radio broadcasts in AM and FM bands. One of the major performance differentiator of DRM Receiver is the acquisition time.

(13) The present invention provides a system for improving the acquisition time in DRM receiver (100). The system comprises components such as: a) an antenna (10) to receive radio signal from a transmission station, b) a tuner (20) to tune the receiver (100) to a frequency, c) a processor (30) to process the tuned signal, d) one or more memory/storage units (40) to store the signal data and e) one or more output devices (50) (such as display/speaker) to output the processed data and audio.

(14) According to the present invention, the signal from any of the transmission stations is received by the antenna (10) located at the receiver end (100) which is tuned to receive the desired frequency. The obtained DRM signal is processed by a processor which comprises: a) an asynchronous sample rate converter (ASRC) (31) to convert the sample rate of input signal to demodulator sample rate, b) a demodulator (32) to demodulate the information/data for further processing, c) a channel splitter (33) to split the demodulated data into Fast Access Channel (FAC), Service Description Channel (SDC) and Main Service Channel (MSC), d) a channel decoder (34) to decode the information from each channel and e) a middleware (351) to parse the decoded channel data and process as audio and data and applications (352) to send processed data to output devices (50) such as speaker and display.

(15) FIG. 1 illustrates a basic block diagram of the DRM receiver (100). The receiver (100) comprises: a) an antenna (10), b) a tuner (20), c) a processor unit (30), d) one or more memory units (40) and e) one or more output devices (50). According to FIG. 1, a DRM signal received by the antenna (10) at the receiver end (100) is tuned to a certain frequency using tuner (20) and the tuned DRM signal is processed at the processor unit (30). The processed signal data is stored in the memory (40) and outputted through the output devices (50) as audio and data.

(16) Referring to FIG. 2, a detailed block diagram of the DRM receiver (100) in accordance with the present invention is illustrated. It includes a processor (30) comprising: an ASRC (31), a demodulator (32), a channel splitter (33), a channel decoder (34) and a middleware & application unit (35). The sample rate of tuned DRM radio signal is converted to demodulator sample rate using ASRC (31). The demodulated data is stored in memory-1 and split into three channels of DRM such as Fast Access Channel (FAC), Service Description Channel (SDC) and Main Service Channel (MSC) using channel splitter (33). This data from channel splitter (33) is decoded by the channel decoder (34). Now, the middleware (351) parses the channel decoded data and processes as audio and data. The processed data is then provided to output devices (50) connected in the circuitry through application unit (352). The output devices (50) include a display device and/or a speaker but not limited to it.

(17) FIG. 3 illustrates the structure of transmission super frame of DRM signal. The duration of one transmission super frame is 1200 ms. Each transmission super frame contains a set of consecutive transmission frames. Referring to FIG. 3, the transmission super frame consists of three transmission frames (Frame-0, Frame-1 and Frame-2). The duration of each transmission frame is 400 ms. The transmission frame further contains Fast Access Channel (FAC), Service Description Channel (SDC) and Main Service Channel (MSC). The Fast Access Channel (FAC) and Main Service Channel (MSC) are available on each frame whereas the Service Description Channel (SDC) is available only in Frame-0 represented by first two or three symbols. FAC contains the transmission frame ID and necessary information to find the service details and also to decode SDC and MSC. SDC which is available at the starting of each super frame contains information to decode the data contained in MSC. MSC has two types of interleaving depths, short and long. Based on interleaving depth, MSC multiplex frame is spread in one frame for short and five frames for long. The MSC has 800 ms delay for short interleaving and 2400 ms delay for long interleaving respectively. It is known in the art that the radio data stream (both audio and data) is contained in the MSC. The time taken to output audio for decoding after receiving SDC will be the delay of multiplex frame based on whether it is short or long. Also, as the processor (30) needs SDC channel information to start MSC processing, the acquisition or processing time will change based on the first received transmission frame.

(18) There are three conditions that exists during the reception of the transmission frames, namely (i) the first received transmission frame is Frame-0, (ii) the first received transmission frame is Frame-1 and (iii) the first received transmission frame is Frame-2.

(19) According to FIG. 4A and FIG. 4B, the flow steps of the present invention are disclosed. In step 402, the demodulated output from DRM demodulator (32) is sent to memory-1 (40) for storage as well as to channel splitter (33) in step 404 for splitting the data into FAC, SDC and MSC. The FAC data from channel splitter (33) is decoded by FAC decoder (341) in step 408 and the FAC parser parses the frame ID in step 410. In step 412, the DRM receiver (100) checks whether the received frame is a first received frame. If it is a first received frame, the receiver (100) further checks the frame ID whether the frame is frame-0 in step 414. If step 412 is no, then step 416 checks the availability of SDC data in the current frame. If step 416, is yes, then flow proceeds to step 420. If step 416 is no, then flow proceeds to step 422. If the first received frame is frame-0 in step 414, the receiver (100) then checks the availability of SDC in the current frame (i.e. frame-0) in step 418; else (i.e. not frame-0), step 419 loads demodulated output from memory-1 (40) for re-splitting. If SDC is available fully on the currently received frame in step 418, the SDC decoder (342) starts SDC data decoding in step 420; else, it loads demodulated output from memory-1 (40) for re-splitting in step 419. The receiver checks the availability of SDC parameters in step 422. If the SDC parameters are available, the receiver (100) then checks the availability of MSC data on memory-2 (40) in step 424; else it stores MSC data to memory-2 (40) in step 426. If MSC data is available on memory-2 (40) in step 424, then the receiver (100) loads the MSC data of previously stored frame from memory-2 (40) in step 428 for decoding to provide audio output in step 430; else, the MSC data of the current frame is decoded to provide audio output in step 432.

(20) FIG. 5A depicts the graphical representation of time taken for executing frames according to the present invention under condition (i) where the first received transmission frame is Frame-0 and SDC is absent. In traditional method, when the first received frame is Frame-0 and SDC is not available, the receiver (100) waits for 1146 ms-1150 ms to receive SDC data and then waits for MSC data to be available to process the frame for providing the output. With the system of present invention, once it is identified that the first received frame is Frame-0 and SDC is not available, the processor (30) fetches demodulated data from memory-1 (40) and re-splits the data to obtain MSC data and stores it into memory-2 (40). Once SDC data is available, the MSC data stored in memory-2 (40) and the MSC data from current frame is decoded without any delay to provide audio output. Thus, reduces the delay of 1146 ms-1150 ms for providing the output in case of long interleaving.

(21) FIG. 5B depicts the graphical representation of time taken for executing frames according to the present invention under condition (ii) where, the first received transmission frame is Frame-1. In traditional method, when the first received frame is Frame-1, the receiver (100) waits for 800 ms to receive the SDC data and then waits for MSC data to be available to process the frames for providing the output. With the system of present invention, once it is identified that the first received frame is Frame-1 and not Frame-0, the processor (30) fetches demodulated data from memory-1 (40) and re-splits the data to obtain MSC data and stores it into memory-2 (40). Once SDC data is available, the MSC data stored in memory-2 and the MSC data from current frame is decoded without any delay to provide audio output. Thus, reduces the delay of 800 ms for providing the output in the case of long interleaving. In case of short interleaving, a similar method is adapted and delay of up to 400 ms is reduced.

(22) FIG. 5C depicts the graphical representation of time taken for executing frames according to the present invention under condition (iii) where, the first received transmission frame is Frame-2. In traditional method, when the first received frame is Frame-2, the receiver (100) waits for 400 ms to receive the SDC data and then processes the frames to provide the output. With the system of present invention, once it is identified that the first received frame is Frame-2 and not Frame-0, the processor (30) fetches demodulated data from memory-1 (40) and re-splits the data to obtain MSC data and stores it into memory-2 (40). Once SDC data is available, the MSC data stored in memory-2 (40) and the MSC data from current frame is decoded without any delay to provide audio output. Thus, reduces the delay of 400 ms in providing the output in the case of long interleaving. In case of short interleaving, a similar method is adapted and delay of up to 400 ms is reduced.

(23) Hence, the present solution avoids the additional time taken of a) 1146 ms-1150 ms used in condition (i), where the first received transmission frame is Frame-0 without SDC, b) 800 ms used in condition (ii), where the first received transmission frame is Frame-1 and c) 400 ms used in condition (iii), where the first received transmission frame is Frame-2 in case of long interleaving depth as DRM channel splitter (33) stores the demodulator (32) output in memory (40). In case of short interleaving, a similar method is adapted and delay of up to 400 ms is reduced. If the first received frame is other than Frame-0 (i.e. Frame-1 or Frame-2), then on next loop the channel splitter (33) re-splits the data stored in memory (40) and starts MSC channel decoding after obtaining SDC parameters, thus enhancing the user experience by improving the acquisition time.

(24) While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.