Dual-floating gates optoelectronic self-exciting synaptic memristor

Abstract

A dual-floating gates optoelectronic self-exciting synaptic memristor includes a bottom gate, a barrier layer coated on a surface of the bottom gate, a quantum dot layer coated on a surface of a middle portion of the barrier layer, two inverted L-shaped electron or hole tunneling layers coated on a surface of two end portions of the quantum dot layer respectively, two inverted L-shaped floating gate storage layers coated on the electron or hole tunneling layers respectively, two electron or hole blocking layers coated on the two floating gate storage layers respectively, an inverted L-shaped source electrode and an inverted L-shaped drain electrode coated on the two electron or hole blocking layers respectively, a photosensitive material layer coated on a surface of a middle portion of the quantum dot layer, and a top gate coated on the photosensitive material layer.

Claims

1. A dual-floating gates optoelectronic self-exciting synaptic memristor, comprising a bottom gate, a barrier layer coated on a surface of the bottom gate, a quantum dot layer coated on a surface of a middle portion of the barrier layer, two inverted L-shaped electron or hole tunneling layers coated on a surface of two end portions of the quantum dot layer respectively, two inverted L-shaped floating gate storage layers coated on the electron or hole tunneling layers respectively, two electron or hole blocking layers coated on the two floating gate storage layers respectively, an inverted L-shaped source electrode and an inverted L-shaped drain electrode coated on the two electron or hole blocking layers respectively, a photosensitive material layer coated on a surface of a middle portion of the quantum dot layer, and a top gate coated on the photosensitive material layer.

2. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 1, wherein the bottom gate for providing holes is made from ITO (indium tin oxide) or fluorine-doped SnO.sub.2 transparent conductive glass.

3. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 1, wherein the quantum dot layer, which acts as a light source, is made from at least one member selected from the group consisting of CdTe, CdSe, InP, ZnS, CdS, PbS, CdS and perovskite.

4. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 3, wherein a light-emitting process of the quantum dot layer is realized by applying an external electric field with different voltage intensities between one of the source electrode and the drain electrode and the bottom gate. Driven by the electric field, the one of the source electrode and the drain electrode and the bottom gate provide electrons and holes respectively to migrate to the quantum dot layer for forming excitons, so that the quantum dots emit light.

5. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 1, wherein the photosensitive material layer is made from perovskite or a two-dimensional material; the two-dimensional material is MoS.sub.2, MoO.sub.x, MoS.sub.xO.sub.2-x, MoSe, MoSSe, BN, BP, graphene, or heterostructures thereof; the perovskite is one or two members selected from the group consisting of MAPbI3, FAPbI.sub.3, (PEA)PbI.sub.3, CsPbI.sub.3, CsPbBr.sub.3, CsPbCl.sub.3, MASnI.sub.3, Cs.sub.3Bi.sub.2I.sub.9, and Rb.sub.3Bi.sub.2I.sub.9.

6. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 1, wherein the source and drain electrodes, dielectric layers and the floating gate storage layer form a source structure and a drain structure respectively; the two electron or hole tunneling layers and the two electron or hole blocking layers act as the dielectric layers.

7. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 6, wherein the source electrode and the drain electrode for providing electrons are made from Ag, Cu or Al.

8. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 6, wherein each of the dielectric layers comprises an electron or hole tunneling layer and an electron or hole blocking layer, and is made from SiO.sub.2 or Al.sub.2O.sub.3.

9. The dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 6, wherein the floating gate storage layer at one side where the source electrode is provided is configured to store the electrons, the floating gate storage layer at another side where the drain electrode is provided is configured to store the holes.

10. A manufacturing method of the dual-floating gates optoelectronic self-exciting synaptic memristor according to claim 1, wherein: the dual-floating gates optoelectronic self-exciting synaptic memristor is manufactured on a substrate from bottom to top in a layer-by-layer manner by dry etching, wet etching, ultrasonic dispersion, transfer, magnetron sputtering, photoetching, or atomic layer deposition; the manufacturing method comprises steps of: (A) depositing the barrier layer on the bottom gate which is smooth and clean through atomic layer deposition technology; (B) coating the quantum dot layer on a surface of the barrier layer through spin coating technology as a light source; (C) depositing two electron or hole tunneling layers, two floating gate storage layers and two electron or hole blocking layers at a surface of two end portions of the quantum dot layer respectively by pulsed laser from bottom to top in sequence, wherein the two electron or hole tunneling layers and the two electron or hole blocking layers act as dielectric layers, the step (C) comprises: (C1) depositing two first inverted L-shaped Al.sub.2O.sub.3 films as the two electron or hole tunneling layers at the surface of the two end portions of the quantum dot layer respectively through atomic layer deposition technology; (C2) preparing the two inverted L-shaped floating gate storage layers on the two electron or hole tunneling layers respectively; and (C3) depositing two second inverted L-shaped Al.sub.2O.sub.3 films as the two electron or hole blocking layers on the two inverted L-shaped floating gate storage layers respectively through atomic layer deposition technology, wherein the two electron or hole tunneling layers and the two electron or hole blocking layers encapsulate the two floating gate storage layers respectively; (D) preparing two inverted L-shaped Ag films as the source electrode and the drain electrode on the two electron or hole blocking layers by magnetron sputtering technology respectively; (E) preparing a MoS.sub.2 film as the photosensitive material layer on a surface of the quantum dot layer through transfer technology; and (F) preparing the top gate, which is made from Au, on a surface of the photosensitive material layer through magnetron sputtering technology.

11. A dual-floating gates optoelectronic self-exciting synaptic memristor array, which comprises N×M (N≥1 and M≥1) dual-floating gates optoelectronic self-exciting synaptic memristors according to claim 1, M source electrode connecting lines, M drain connecting electrode lines, M top gate connecting lines, and N bottom gate connecting lines, wherein M memristors on each row in the memristor array share a bottom gate connecting line, N memristors on each column in the memristor array share a top gate connecting line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG. 1 is a structurally schematic diagram of a dual-floating gates optoelectronic self-exciting synaptic memristor provided by the present invention.

[0047] FIG. 2 is a structurally schematic diagram of a dual-floating gates optoelectronic self-exciting synaptic memristor array provided by the present invention.

[0048] FIG. 3a is a schematic diagram of the conduction mechanism of a dual-floating gates optoelectronic self-exciting device along a vertical direction.

[0049] FIG. 3b is a schematic diagram of the conduction mechanism of the dual-floating gates optoelectronic self-exciting device along a horizontal direction.

[0050] In the drawings, 101: top gate; 102: bottom gate; 103a: source electrode; 103b: drain electrode; 104: photosensitive material layer; 105: quantum dot layer; 106: floating gate storage layer; 107a: electron or hole tunneling layer; 107b: electron or hole blocking layer; 108: barrier layer; 201: source electrode connecting line; 202: top gate connecting line; 203: bottom gate connecting line; 204: dual-floating gates optoelectronic self-exciting synaptic memristor; 205: drain electrode connecting line; 301: hole; 302: electron.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0051] The present invention is further explained in detail with reference to embodiments and drawings as follows. The embodiments are intended to facilitate the understanding of the present invention, and the specific structural and functional details are only for the purpose of describing the exemplary embodiments and have no limitation on the present invention. Therefore, the present invention may be embodied in various forms, and the present invention should not be construed as limited only to the exemplary embodiments set forth again, but should cover all changes, equivalents and alternatives falling within the protective scope of the present invention.

[0052] First Embodiment:

[0053] FIG. 1 shows a dual-floating gates optoelectronic self-exciting synaptic memristor, which comprises a bottom gate 102, a barrier layer 108 coated on a surface of the bottom gate 102, a quantum dot layer 105 coated on a surface of a middle portion of the barrier layer 108, two inverted L-shaped electron or hole tunneling layers 107a coated on a surface of two end portions of the quantum dot layer 105 respectively, two inverted L-shaped floating gate storage layers 106 coated on the electron or hole tunneling layers 107a respectively, two electron or hole blocking layers 107b coated on the two floating gate storage layers 106 respectively, an inverted L-shaped source electrode 103a and an inverted L-shaped drain electrode 103b coated on the two electron or hole blocking layers 107b respectively, a photosensitive material layer 104 coated on a surface of a middle portion of the quantum dot layer 105, and a top gate 101 coated on the photosensitive material layer 104.

[0054] The bottom gate 102 is made from ITO (indium tin oxide) and has a thickness of 175 μm, the barrier layer 108 is made from SiO.sub.2 and has a thickness in a range of 1 to 2 nm, the quantum dot layer 105 is made from PbS and has a thickness in a range of 5 to 10 nm, the photosensitive material layer 104 is made from MoS.sub.2 and has a thickness in a range of 5 to 10 nm, the top gate 101 is made from Au and has a thickness of 50 nm, both of the source electrode 103a and the drain electrode 103b are made from Ag and have a thickness of 40 nm, both the electron or hole tunneling layers 107a and the electron or hole blocking layers 107b are made from Al.sub.2O.sub.3 and have a thickness in a range of 1 to 3 nm, and the floating gate storage layers 106 have a thickness in a range of 2 to 10 nm.

[0055] Second Embodiment:

[0056] The dual-floating gates optoelectronic self-exciting synaptic memristor according to the first preferred embodiment of the present invention is manufactured on a substrate from bottom to top in a layer-by-layer manner by dry etching, wet etching, ultrasonic dispersion, transfer, magnetron sputtering, photoetching, atomic layer deposition and other methods. The manufacturing process comprises steps of:

[0057] (A) depositing a barrier layer 108 on a bottom gate 102 which is smooth and clean through atomic layer deposition technology;

[0058] (B) coating a quantum dot layer 105 on a surface of the barrier layer 108 through spin coating technology as a light source;

[0059] (C) depositing two electron or hole tunneling layers 107a, two floating gate storage layers 106 and two electron or hole blocking layers 107b at a surface of two end portions of the quantum dot layer 105 respectively by pulsed laser from bottom to top in sequence, wherein the two electron or hole tunneling layers 107a and the two electron or hole blocking layers 107b act as dielectric layers, and the step (C) comprises:

[0060] (C1) depositing two first inverted L-shaped Al.sub.2O.sub.3 films as the two electron or hole tunneling layers 107a at the surface of the two end portions of the quantum dot layer 105 respectively through atomic layer deposition technology;

[0061] (C2) preparing the two inverted L-shaped floating gate storage layers 106 on the two electron or hole tunneling layers 107a respectively; and

[0062] (C3) depositing two second inverted L-shaped Al.sub.2O.sub.3 films as the two electron or hole blocking layers 107b on the two inverted L-shaped floating gate storage layers 106 respectively through atomic layer deposition technology, wherein the two electron or hole tunneling layers 107a and the two electron or hole blocking layers 107b encapsulate the two floating gate storage layers 106 respectively;

[0063] (D) preparing two inverted L-shaped Ag films as a source electrode 103a and a drain electrode 103b on the two electron or hole blocking layers 107b by magnetron sputtering technology respectively;

[0064] (E) preparing a MoS.sub.2 film as a photosensitive material layer 104 on a surface of the quantum dot layer 105 through transfer technology; and

[0065] (F) preparing a top gate 101, which is made from Au and has a thickness of 50 nm, on a surface of the photosensitive material layer 104 through magnetron sputtering technology.

[0066] Third Embodiment:

[0067] A method for realizing optoelectronic memristor effect with the dual-floating gates optoelectronic self-exciting synaptic memristor according to the first preferred embodiment of the present invention is illustrated. The method comprises steps of:

[0068] (a) as shown in FIG. 3a, during a writing process, a bottom gate 102 generating holes and one of a source electrode 103a and a drain electrode 103b generating electrons by applying a write signal between the one of the source electrode 103a and the drain electrode 103b and the bottom gate 102; driven by an electric field, the holes and the electrons entering a quantum dot layer 105 from two floating gate storage layers 106 for tunneling; forming excitons by coupling the holes with the electrons, quantum dots emitting light, controlling a luminous intensity of the quantum dots by writing pulse parameters at the source electrode 103a and the drain electrode 103b to achieve a change in a conductance of a photosensitive material layer 104, applying a forward bias voltage of 0 V to a top gate 101, and reading a current value of the memristor, thus realizing conductance regulation of the device, wherein:

[0069] the stronger the luminous intensity of the quantum dots, the greater the change in the conductance of the photosensitive material layer 104; the voltage at the source electrode 103a and the drain electrode 103b is in a range of 0 V to 4V; and (b) as shown in FIG. 3b, during an erasing process, decoupling the electrons and the holes by applying a reverse voltage between the source electrode 103a and the drain electrode 103b, separating the electrons from the holes under a drive of the reverse voltage, storing the electrons and the holes in two floating gate storage layers 106 respectively, the quantum dot quenching, and photocurrent gradually disappearing, thereby completing an activation.

[0070] This process well mimics the plasticity of neurobiological synapses.

[0071] By controlling the input electrical pulses parameter, such as number, pulse width, pulse period and pulse amplitude, the memristor provided by the present is able to adjust the value of high-resistance state and low-resistance state respectively, and simulate the corresponding synaptic functions, such as learning-forgetting behavior, spike-timing dependence plasticity (STDP) and other heterosynaptic plasticity.

[0072] The memristor provided by the present has high alignment and confinement in light control, and has obvious advantages in device energy consumption and neural function simulation.

[0073] Fourth Embodiment:

[0074] As shown in FIG. 4, a dual-floating gates optoelectronic self-exciting synaptic memristor array according to a fourth embodiment of the present invention is illustrated. The memristor array comprises N×M (N≥1 and M≥1) dual-floating gates optoelectronic self-exciting synaptic memristors 204, M source electrode connecting lines 201, M drain connecting electrode lines 205, M top gate connecting lines 202, and N bottom gate connecting lines 203. FIG. 2 shows a 4×4 dual-floating gates optoelectronic self-exciting synaptic memristor array. There are four dual-floating gates optoelectronic self-exciting synaptic memristors on each row in the memristor array, and the four memristors share a bottom gate connecting line 203. There are four memristors on each column in the memristor array, and the four memristors share a top gate connecting line 202. Accordingly, a cross array is formed.

[0075] The memristor array is able to simulate the corresponding synaptic function by combining multiple single-device functions, and realize applications such as logic operations, matrix operations, image recognition, and neuromorphic computing.

[0076] It should be noted that, in each embodiment of the present invention, in order to make those skilled in the art better understand the present invention, many technical details are put forward. However, even without these technical details and various changes and modifications based on the above embodiments, the technical solutions provided by in the present invention are able to be realized.