Abstract
An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.
Claims
1. An all-digital phase-locked loop (ADPLL), comprising: a digitally controlled oscillator (DCO), configured to generate a clock signal according to a frequency control signal; a time-to-digital converter (TDC), coupled to the DCO, configured to generate a digital output signal according to a phase error between the clock signal and a reference signal; and a normalization circuit, coupled to the TDC, configured to convert the digital output signal into a clock phase value according to a gain parameter and storing a plurality of candidate gain parameters; wherein the normalization circuit selects in response to the digital output signal one of the candidate gain parameters to be the gain parameter.
2. The ADPLL of claim 1, wherein the candidate gain parameters are generated by the normalization circuit according to a plurality of previous phase error values and a plurality of previous digital output signals.
3. The ADPLL of claim 2, wherein the normalization circuit generates each of the candidate gain parameters according to a product of one of the previous phase error values and one of the previous digital output signals.
4. The ADPLL of claim 3, wherein the normalization circuit comprises a least mean square (LMS) circuit, configured to generate a next gain parameter for a next cycle according to a product of the phase error value and the digital output signal and a current gain parameter utilized in a current cycle.
5. The ADPLL of claim 3, wherein the normalization circuit further comprises: a multiplexer (MUX), controlled by the digital output signal to output one of the candidate gain parameters as the gain parameter; a de-multiplexer (DEMUX), controlled by a delayed digital output signal, configured to receive a delayed gain parameter which is generated according to the delayed digital output signal, wherein the delayed gain parameter is configured to update a corresponding candidate gain parameter; a storage device, coupled to a plurality of input terminals of the MUX and a plurality of output terminals of the DEMUX, configured to store the candidate gain parameters; and a first delay circuit, coupled to the MUX and the DEMUX, configured to receive the digital output signal for generating the delayed digital output signal.
6. The ADPLL of claim 5, wherein the normalization circuit further comprises: a plurality of registers, configured to store the candidate gain parameters; a plurality of adders, respectively coupled to the registers and coupled to the DEMUX; and a plurality of second delayed circuits, respectively coupled to the registers and the adders.
7. A calibration method of an all-digital phase-locked loop (ADPLL), comprising: utilizing a digitally controlled oscillator (DCO) of the ADPLL to generate a clock signal according to a frequency control signal; utilizing a time-to-digital converter (TDC) of the ADPLL to generate a digital output signal according to a phase error between the clock signal and a reference signal; utilizing a normalization circuit of the ADPLL to convert the digital output signal into a clock phase value according to a gain parameter and storing a plurality of candidate gain parameters; and utilizing the normalization circuit to select in response to the digital output signal one of the candidate gain parameters to be the gain parameter.
8. The calibration method of claim 7, wherein the candidate gain parameters are generated by the normalization circuit according to a plurality of previous phase error values and a plurality of previous digital output signals.
9. The calibration method of claim 8, wherein the step of utilizing the normalization circuit of the ADPLL to convert the digital output signal into the clock phase value according to the gain parameter comprises: utilizing the normalization circuit to multiply the digital output signal by the gain parameter to generate the clock phase value.
10. The calibration method of claim 8, further comprising: utilizing the normalization circuit to generate each of the candidate gain parameters according to a product of one of the previous phase error values and one of the previous digital output signals.
11. The calibration method of claim 10, wherein the step of utilizing the normalization circuit to generate each of the candidate gain parameters according to a product of one of the previous phase error values and one of the previous digital output signals comprises: utilizing a least mean square (LMS) circuit of the normalization circuit to generate a next gain parameter for a next cycle according to a product of the phase error value and the digital output signal and a current gain parameter utilized in a current cycle.
12. The calibration method of claim 10, wherein the step of utilizing the normalization circuit to select one of the plurality of candidate gain parameters in response to the digital output signal for being utilized as the gain parameter comprises: delaying the digital output signal to generate a delayed digital output signal; controlling a multiplexer (MUX) by the digital output signal; controlling a de-multiplexer (DEMUX) by the delayed digital output signal; and controlling the MUX to output which one of the candidate gain parameters stored in a storage device, and utilizing the DEMUX to control the storage device to receive a delayed gain parameter generated according to the delayed digital output signal, wherein the delayed gain parameter is configured to update a corresponding candidate gain parameter.
13. The calibration method of claim 12, wherein updating the corresponding candidate gain parameter comprises: adding the corresponding candidate gain parameter of the candidate gain parameters stored in the storage device with the delayed again parameter to update the corresponding candidate gain parameter.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a diagram illustrating resolution of a time-to-digital converter (TDC) according to an embodiment of the present invention.
[0010] FIG. 2 illustrates a circuit architecture of a TDC according to an embodiment of the present invention.
[0011] FIG. 3 illustrates some signals which are involved in the circuit architecture shown in FIG. 2.
[0012] FIG. 4 is a diagram illustrating a normalization operation of a TDC according to an embodiment of the present invention.
[0013] FIG. 5 is a diagram illustrating an all-digital phase-locked loop (ADPLL) according to an embodiment of the present invention.
[0014] FIG. 6 illustrates some signals at a locked state under an ideal condition according to an embodiment of the present invention.
[0015] FIG. 7 illustrates some signals at a locked state when a TDC gain has −20% error according to an embodiment of the present invention.
[0016] FIG. 8 illustrates some signals at a locked state when a TDC gain has +20% error according to an embodiment of the present invention.
[0017] FIG. 9 is an example of a least mean square (LMS) circuit shown in FIG. 5 according to an embodiment of the present invention.
[0018] FIG. 10 is a diagram illustrating a working flow of a calibration method of an ADPLL according to an embodiment of the present invention.
[0019] FIG. 11 is a diagram illustrating an ADPLL according to another embodiment of the present invention.
[0020] FIG. 12 is a diagram illustrating a storage device according to an embodiment of the present invention.
DETAILED DESCRIPTION
[0021] Several embodiments are provided to explain the concept of the present invention. Note that the components in each embodiment can be implemented by hardware (e.g., apparatus or circuit) or by firmware (e.g., a microprocessor with at least one program therein). Additionally, in following embodiments, the terms “first”, “second”, etc. are only for defining different components, parameters, data, signals or steps, and are not meant to be a limitation of the order thereof.
[0022] In operations of an all-digital phase-locked loop (ADPLL), assume that a cycle period of a clock signal CKV output by a digitally controlled oscillator (DCO) is T.sub.V, and a time-to-digital converter (TDC) generates a digital output signal N.sub.r according to a phase error between the clock signal and a reference signal FREF (e.g., a time difference Δt.sub.r between a rising edge of the clock signal CKV and a rising edge of the reference signal FREF). The ADPLL needs to perform normalization on the digital output signal N.sub.r to convert the digital output signal N.sub.r into a value Ø.sub.DCO within a range from 0 to 1 (e.g., a value representing the phase error between the clock signal CKV and the reference signal FREF as Ø.sub.DCO times the cycle period T.sub.V) for subsequent operations. The result of the above normalization may be affected by resolution Δt.sub.res of the TDC (e.g., a time difference corresponding to a least significant bit (LSB) of the digital output signal of the TDC, or a unit delay of the TDC), where Ø.sub.DCO=N.sub.r×Δt.sub.res/T.sub.V, and the resolution Δt.sub.res of the TDC may vary due to process-voltage-temperature (PVT) variation of semiconductors. Thus, the operation of the normalization mentioned above needs to be calibrated in response to the varying resolution.
[0023] FIG. 1 is a diagram illustrating the resolution Δt.sub.res of a TDC according to an embodiment of the present invention. As shown in FIG. 1, the TDC may detect a time difference Δt.sub.r between a rising edge of the clock signal CKV and a rising edge of the reference signal FREF, and may further detect a time difference Δt.sub.f between a falling edge of the clock signal CKV and the rising edge of the reference signal FREF. As shown in FIG. 1, a difference value between Δt.sub.r and Δt.sub.f is a half cycle period T.sub.V/2 of the clock signal CKV, and the TDC (or subsequent processing circuit thereof) may utilize respective digital output signals which are respectively output according to Δt.sub.r and Δt.sub.f to roughly calculate the resolution Δt.sub.res of the TDC.
[0024] FIG. 2 illustrates a circuit architecture of a TDC 20 according to an embodiment of the present invention, and FIG. 3 illustrates some signals which are involved in the circuit architecture shown in FIG. 2. It should be noted that the circuit architecture shown in FIG. 2 is an example of the TDC 20 only, and is not meant to be a limitation of the present invention. As shown in FIG. 2, the TDC 20 may comprise multiple inverters connected in series to form an inverter chain. As each inverter of these inverters may cause a delay of a signal, respective output signals D<0>, D<1>, D<2>, . . . , D<L−1> and D<L> of these inverters may have corresponding delay periods relative to the clock signal CKV which is input to a first inverter of these inverters, as illustrated by D<0>, D<1>, D<2>, D<3>, D<4>, D<5>, D<6> and D<7> shown in FIG. 3, where a delay amount introduced by one inverter may be the resolution Δt.sub.res of the TDC 20. In this embodiment, each of the output signals D<0>, D<1>, D<2>, . . . , D<L− 1> and D<L> may be input to an input terminal (which is labeled “D”) of a flip-flop, and may be output from an output terminal (labeled “Q”) of the flip-flop when the flip-flop is triggered by the rising edge of the reference signal FREF, as illustrated by Q<0:L> shown in FIG. 3. In this embodiment, a portion of the output signals Q<0:L> which are changed from 0 to 1 (e.g., Q<1> is 0 and Q<2> is 1) may represent the falling edge of the clock signal CKV, and a portion of the output signals Q<0:L> which are changed from 1 to 0 (e.g., Q<5> is 1 and Q<6> is 0) may represent the rising edge of the clock signal CKV. The TDC 20 may utilize a pseudo-thermometer-code edge detector 22 (e.g., a detector configured to detect a change from 0 to 1 and a change from 1 to 0 in a digital sequence) therein to detect the output signals Q<0:L> and accordingly output digital output signals N.sub.r and N.sub.f in a binary format, for respectively representing the time difference Δt.sub.r between the rising edge of the clock signal CKV and the rising edge of the reference signal FREF and the time difference Δt.sub.f between the falling edge of the clock signal CKV and the rising edge of the reference signal FREF (e.g., Δt.sub.r≈N.sub.r×Δt.sub.res and Δt.sub.f≈N.sub.f×Δt.sub.res). In an example, N.sub.r=6 and N.sub.f=2. It should be noted that the circuit architecture of TDC 20 shown in FIG. 2 is for illustrative purposes only, and is not meant to be a limitation of the present invention. For example, a bit count of each of the output signals of the TDC may vary according to requirements of the system, and L may be any positive integer.
[0025] FIG. 4 is a diagram illustrating a normalization operation of the TDC 20 according to an embodiment of the present invention. As shown in FIG. 4, the TDC 20 may transmit the digital output signal N.sub.r and N.sub.f obtained from the above operations to a normalization circuit 30. Initially, the normalization circuit 30 may utilize a first calculating unit 31 (which is labeled “Period average” for better comprehension) to perform the calculation mentioned in the embodiment of FIG. 1 to obtain an average T.sub.y of a cycle period of the clock signal CKV and the resolution Δt.sub.res of the TDC 20, and then utilize a second calculating unit 32 (which is labeled
[00001]
for better comprehension) to output the reciprocal of T.sub.V/Δt.sub.res in a binary form (e.g., a signal PERINV). The normalization circuit 30 further utilizes a multiplier 33 to multiply the digital output signal N.sub.r by the signal PERINV to generate a W.sub.F-bit multiplied result (e.g., W.sub.F=15), and then finally transforms the multiplied result into an unsigned 2's complement form via a third calculating unit 34 (which is labeled “2{circumflex over ( )}W.sub.F−(x)”) to output a signal ε, where the W.sub.F-bit binary signal ε may be illustrated in a manner of discrete data (e.g., a k.sup.th set of data) as follows:
[00002]
[0026] It should be noted that when a duty cycle of the clock signal CKV is not 50%, the aforementioned operations of obtaining the average T.sub.V of the cycle period of the clock signal CKV and the resolution Δt.sub.res of the TDC 20 may need to be implemented by a more complex hardware. In addition, the estimation method mentioned above is limited by the resolution Δt.sub.res of the TDC 20, and estimation errors may exist, which degrades the performance of the ADPLL (e.g., output spur becomes too big).
[0027] For brevity, the following description takes values in a decimal form. FIG. 5 is a diagram illustrating an ADPLL 50 according to an embodiment of the present invention, where the ADPLL 50 may comprise a TDC 500, a digitally controlled oscillator (DCO) 510 (which is illustrated by a circle with a sine wave therein for better comprehension), a normalization circuit 520, an accumulator 530 (which is labeled “Σ” for better comprehension), a low pass filter 540 (which is illustrated by a box with a low pass response waveform therein for better comprehension) and an adder 550 (which is illustrated by a circle with “+” therein for better comprehension). In this embodiment, a parameter FCW_F may be set as a ratio value between a target frequency of the clock signal CKV and a frequency of the reference frequency FREF, and the accumulator 530 may continuously accumulate the parameter FCW_F to output an accumulated result as a reference phase. The TDC 500 may be coupled to the DCO 510, and may be configured to generate a digital output signal N.sub.r[k] (e.g.) according to a phase error between the clock signal CKV and the reference signal FREF. The normalization circuit 520 may be coupled to the TDC 500, and may be configured to convert the digital output signal N.sub.r[k] into a clock phase value Ø.sub.DCO[k] (e.g., a value of Ø.sub.DCO at the k.sup.th cycle of the reference signal FREF) according to a gain parameter K.sub.TDC, where the clock phase value Ø.sub.DCO[k] may be regarded as a result of performing normalization on the digital output signal N.sub.r[k]. The adder 550 may perform subtraction on the reference phase mentioned above with a real-time phase (e.g., an accumulated result of a real-time ratio value between a real-time frequency of the clock signal CKV and the frequency of the reference signal FREF) to obtain a phase error value Ø.sub.E[k] (e.g., a value of Ø.sub.E at the k.sup.th cycle of the reference signal FREF), and the low pass filter 540 may generate a frequency control signal according to the phase error value Ø.sub.E[k], in order to control the DCO 510 to generate the clock signal CKV according to the frequency control signal, and thereby make the real-time frequency of the clock signal CLK gradually approach the target frequency.
[0028] It should be noted that the digital output signal N.sub.r[k] generated by the TDC 500 and the clock phase value Ø.sub.DCO[k] after the normalization are merely configured to represent a fractional portion of the real-time phase, and an integer portion of the real-time phase may be calculated by a counter. As operations of utilizing the counter to generate the integer portion of the real-time phase are well-known by those skilled in this art, and do not affect implementation of calibration of the TDC 500 and the normalization circuit 520, the counter is not shown in FIG. 5 for brevity, and related details are omitted here for brevity. Similarly, a reference phase value Ø.sub.R[k] (e.g., a value of Ø.sub.R at the k.sup.th cycle of the reference signal FREF) output by the accumulator 530 shown in FIG. 5 merely represents a fractional portion of the reference phase mentioned above for brevity.
[0029] In the embodiment of FIG. 5, the normalization circuit 520 may comprise a multiplier 521, configured to multiply the digital output signal N.sub.r[k] by the gain parameter K.sub.TDC to generate the clock phase value Ø.sub.DCO[k], and a correct value of the gain parameter K.sub.TDC may be obtained by the following equation:
[00003]
where t.sub.res may represent resolution of the TDC 500 (e.g., Δt.sub.res mentioned above), and T.sub.DCO may represent a cycle period of the clock signal CKV output from the DCO 510 (e.g., T.sub.V or T.sub.V mentioned above). As the resolution t.sub.res of the TDC 500 is quite sensitive to the PVT variation (e.g., t.sub.res is 13 picoseconds (ps) when the temperature is 25° C., and t.sub.res is 10 ps when the temperature is 80° C.), the gain parameter K.sub.TDC may have gain error under different temperatures, and the gain error of the gain parameter may result in occurrence of unwanted frequency components such as fractional spur.
[0030] Assuming that the frequency of the reference signal FREF is 40 MHz, the ratio value FCW between the target frequency of the clock signal CKV and the frequency of the reference signal FREF is 125.25, the expected resolution t.sub.res is 10 μs, and the target frequency such as f.sub.DCO of the clock signal CKV, then the gain parameter is about 0.05.
[0031] FIG. 6 to FIG. 8 illustrate values of the clock phase Ø.sub.DCO, the reference phase Ø.sub.R, and the phase error Ø.sub.E, based on the frequencies of the clock signal CKV and the reference signal FREF under different conditions. As shown in FIG. 6, in respective cycles of the reference signal FREF, the digital output signal N.sub.r is sequentially 5, 10, 15 and 0, and the reference phase Ø.sub.R is sequentially 0.25, 0.5, 0.75 and 0. Under a condition where the gain parameter K.sub.TDC has no gain error (e.g., both a gain parameter corresponding to actual resolution t.sub.res (i.e., t.sub.res/T.sub.DCO) and the value of the gain parameter K.sub.TDC which is set in advance are 0.05), the clock phase Ø.sub.DCO is sequentially 0.25, 0.5, 0.75 and 0, and therefore the phase error Ø.sub.E is kept at 0. When the gain parameter K.sub.TDC set in advance has −20% error (e.g., 0.04), the clock phase Ø.sub.DCO is sequentially 0.2, 0.4, 0.6 and 0, which makes the phase error Ø.sub.E still have a positive phase error (e.g., 0.05, 0.1, 0.15 and 0) at a locked state as shown in FIG. 7. When the gain parameter K.sub.TDC set in advance has +20% error (e.g., 0.06), the clock phase Ø.sub.DCO is sequentially 0.3, 0.6, 0.9 and 0, which makes the phase error Ø.sub.E still have a negative phase error (e.g., −0.05, −0.1, −0.15 and 0) at a locked state as shown in FIG. 8.
[0032] According to the above example, it can be observed that the gain parameter K.sub.TDC has correlation with the digital output signal N.sub.r[k] and the phase error Ø.sub.E[k]. For example, a higher value of N.sub.r[k] may result in a high value of the phase error Ø.sub.E[k]. In another example, a positive gain error of the gain parameter K.sub.TDC may result in a negative phase error Ø.sub.E[k], and a negative gain error of the gain parameter K.sub.TDC may result in a positive phase error Ø.sub.E[k].
[0033] Thus, embodiments of the present invention provide a calibration method and an associated architecture which utilize the digital output signal N.sub.r[k] and/or the phase error Ø.sub.E[k] for calibrating the gain parameter K.sub.TDC.
[0034] As shown in FIG. 5, in addition to the multiplier 521, the normalization circuit 520 may further comprise a multiplier 522 and a least mean square (LMS) circuit 523 (which is labeled “LMS” for brevity), where the LMS circuit 523 is coupled between the multipliers 521 and 522. In this embodiment, the normalization circuit 520 may modify the gain parameter K.sub.TDC according to the phase error value Ø.sub.E[k] between the clock phase value Ø.sub.DCO[k] and the reference phase value Ø.sub.R[k]. In particular, when the phase error value Ø.sub.E[k] is positive (as shown in FIG. 7), it means the gain parameter K.sub.TDC has a negative error (e.g. the gain parameter is less than t.sub.res/T.sub.DCO), and the normalization circuit 520 may increase the gain parameter K.sub.TDC; and when the phase error value Ø.sub.E[k] is negative (as shown in FIG. 8), it means the gain parameter K.sub.TDC has a positive error (e.g. the gain parameter is greater than t.sub.res/T.sub.DCO), and the normalization circuit 520 may decrease the gain parameter K.sub.TDC.
[0035] In this embodiment, the normalization circuit 520 may modify the gain parameter K.sub.TDC according to the phase error value Ø.sub.E[k] and the digital output signal N.sub.r. For example, the normalization circuit 520 may modify the gain parameter K.sub.TDC according to a product Ø.sub.E[k]×N.sub.r of the phase error value Ø.sub.E[k] and the digital output signal N.sub.r. As shown in FIG. 5, the normalization circuit 520 may utilize the multiplier 522 to calculate the product Ø.sub.E[k]×N.sub.r of the phase error value Ø.sub.E[k] and the digital output signal N.sub.r, in order to make the LMS circuit 523 modify the gain parameter K.sub.TDC according to a calculation result of Ø.sub.E[k]×N.sub.r.
[0036] FIG. 9 is an example of the LMS circuit 523 shown in FIG. 5 according to an embodiment of the present invention. As shown in FIG. 9, the LMS circuit 523 may comprise a multiplier 524 and an accumulator 525 (which is labeled “X” for better comprehension). In this embodiment, the LMS circuit 523 may be configured to generate a next gain parameter K.sub.TDC[k] for a next cycle (e.g., the k.sup.th cycle of the reference signal FREF) according to the product Ø.sub.E[k]×N.sub.r of the phase error Ø.sub.E[k] value and the digital output signal N.sub.r and a current gain parameter K.sub.TDC[k−1] utilized in a current cycle (e.g., a (k−1).sup.th cycle of the reference signal FREF). For example, the multiplier 522 may multiply a 19-bit phase error value Ø.sub.E[k] by a 6-bit digital output signal N.sub.r[k] to generate a 25-bit product Ø.sub.E[k]×N.sub.r. The multiplier 524 may further multiply the product Ø.sub.E[k]×N.sub.r by a predetermined value μ, and the accumulator 525 may accumulate a multiplied result to the gain parameter K.sub.TDC[k−1] to obtain a 16-bit gain parameter K.sub.TDC[k], where the predetermined value may be any suitable constant value, and related calculation may be expressed in discrete data as follows:
K.sub.TDC[k]=K.sub.TDC[k−1]+μ{N.sub.r[k].Math.Ø.sub.E[k]}
[0037] It should be noted that the equation mentioned above and the architecture shown in FIG. 9 are merely an example of the LMS circuit 523 calibrating the gain parameter K.sub.TDC, and is not meant to be a limitation of the present invention. As long as the gain parameter K.sub.TDC may be gradually modified or converge to t.sub.res/T.sub.DCO according to the phase error value Ø.sub.E[k] and/or the digital output signal N.sub.r[k], alternative designs should belong to the scope of the present invention.
[0038] FIG. 10 is a diagram illustrating a working flow of a calibration method of an ADPLL according to an embodiment of the present invention, where the calibration method is applicable to the ADPLL 50 shown in FIG. 5. It should be noted that, as long as an overall result is not hindered, one or more steps may be added, deleted or modified in the working flow shown in FIG. 10, and these steps do not have to be executed in the exact order shown in FIG. 10.
[0039] In Step 1010, the ADPLL 50 utilizes the DCO 510 to generate the clock signal CKV according to a frequency control signal.
[0040] In Step 1020, the ADPLL 50 utilizes the TDC 500 to generate the digital output signal N.sub.r[k] according to a phase error between the clock signal CKV and the reference signal FREF.
[0041] In Step 1030, the ADPLL 50 utilizes the normalization circuit 520 to convert the digital output signal N.sub.r[k] into the clock phase value Ø.sub.DCO[k] according to the gain parameter K.sub.TDC.
[0042] In Step 1040, the ADPLL 50 utilizes the normalization circuit 520 to modify the gain parameter K.sub.TDC according to the phase error value Ø.sub.E[k] between the clock phase value Ø.sub.DCO[k] and the reference phase value Ø.sub.R[k].
[0043] To summarize, the embodiments of the present invention provide an ADPLL and a calibration method thereof, which can determine a direction or tendency of an error of the gain parameter K.sub.TDC according to the phase error value Ø.sub.E[k] and the signal N.sub.r output from a TDC, and establish a feedback calibration mechanism to make the gain parameter K.sub.TDC gradually converge to a correct value. In addition, the calibration mechanism of the present invention is not limited to resolution of the TDC, and more particularly, the accuracy and the precision of the calibration may be determined according to the design of the number of bits of calculating units (e.g., the multiplier 521 and 522, and the LMS circuit 523) within the normalization circuit 520. Thus, the present invention can make parameters related to the TDC (e.g., the gain parameter K.sub.TDC of the TDC) converge to a correct or optimized value.
[0044] In the previous embodiment, the normalization circuit 520 calibrates the gain parameter K.sub.TDC in real time. A current gain parameter K.sub.TDC may be affected by a previous gain parameter K.sub.TDC and a current phase error Ø.sub.E[k], however. Even if the digital output signal N.sub.r remains the same, the gain parameter K.sub.TDC may be generated to have a greater error, and the linearity of the TDC 500 may be accordingly impacted.
[0045] Thus, the present invention further provides an ADPLL and a calibration method thereof, which select one of a plurality of candidate gain parameters in response to the digital output signal N.sub.r, for being utilized as the gain parameter. In one embodiment, the candidate gain parameters are generated by the normalization circuit 520 according to a plurality of phase error values and a plurality of previous digital output signals. For example, a candidate gain parameter K.sub.TDC[n−2] is generated according to a phase error value Ø.sub.E[n−2] and a digital output signal N.sub.r[n−2], a candidate gain parameter K.sub.TDC[n−1] is generated according to a phase error value Ø.sub.E[n−1] and a digital output signal N.sub.r[n−1], and a candidate gain parameter K.sub.TDC[n] is generated according to a phase error value Ø.sub.E[n] and a digital output signal N.sub.r[n]. The gain parameters K.sub.TDC[n−2], K.sub.TDC[n−1] and K.sub.TDC[n] may be stored in the normalization circuit 520. When the value of the digital output signal N.sub.r is N.sub.r[n] again, the candidate gain parameter K.sub.TDC[n] may be selected from the plurality of the stored gain parameters and output to the multiplier 521, rather than generating the gain parameter K.sub.TDC in real time as illustrated in the embodiment of FIG. 5.
[0046] FIG. 11 is a diagram illustrating an ADPLL according to another embodiment of the present invention. In the embodiment of FIG. 11, in addition to the components shown in FIG. 5, a normalization circuit 1100 may further comprise a multiplexer (MUX) 1101, a storage device 1103, a de-multiplexer (DEMUX) 1105 and a first delay circuit 1107. The multiplexer 1101 is controlled by the digital output signal N.sub.r[k]. The DEMUX 1105 is controlled by a delayed digital output signal N.sub.r[k.sub.d], and the DEMUX 1105 is coupled to an output terminal of the LMS circuit 523. The storage device 1103 is coupled to a plurality of input terminals of the MUX 1101 and a plurality of output terminals of the DEMUX 1105, and is configured to store the candidate gain parameters. In one embodiment, the storage device 1103 comprises multiple registers for storing the candidate gain parameters. The first delay circuit 1107 is coupled to the MUX 1101 and the DEMUX 1105, and is configured to receive the digital output signal N.sub.r[k] to generate the delayed digital output signal N.sub.r[k.sub.d].
[0047] In the embodiment of FIG. 11, the MUX 1101 may select a corresponding candidate gain parameter according to the digital output signal N.sub.r[k] at first. The LMS circuit 523 then generates the candidate gain parameter corresponding to the delayed digital output signal N.sub.r[k.sub.d] according to the delayed digital output signal N.sub.r[k.sub.d] and the phase error Ø.sub.E[k]. The normalization circuit 1100 may update the candidate gain parameter corresponding to the digital output signal N.sub.r[k] stored in the storage device 1103 according to the candidate gain parameter corresponding to the delayed digital output signal N.sub.r[k.sub.d]. In one embodiment, the candidate gain parameters would not be updated, where after the candidate gain parameters have been generated according to the digital output signal N.sub.r[k], same values of these candidate gain parameters continue to be used without being changed.
[0048] FIG. 12 is a diagram illustrating the storage device 1103 according to an embodiment of the present invention, where the candidate gain parameters stored in the storage device 1103 may be updated. As shown in FIG. 12, the storage device 1103 comprises a plurality of registers Re1, Re2, . . . and Ren, a plurality of adders 1201-1, 1201-2, . . . and 1201-n, and a plurality of second delay circuits 1203-1, 1203-2, . . . and 1203-n. The registers Re1, Re2, . . . and Ren are configured to store candidate gain parameters K.sub.TDC1, K.sub.TDC2, . . . and K.sub.TDCn, respectively. The adders 1201-1, 1201-2, . . . and 1201-n are respectively coupled to the registers Re1, Re2, . . . and Ren, and are further coupled to the DEMUX 1105. The second delay circuits 1203-1, 1203-2, . . . and 1203-n are respectively coupled to the registers Re1, Re2, . . . and Ren, and are further respectively coupled to the adders 1201-1, 1201-2, . . . and 1201-n. In the embodiment of FIG. 12, the candidate gain parameters K.sub.TDC1, K.sub.TDC2, . . . and K.sub.TDCn which are originally stored in the registers Re1, Re2, . . . and Ren may be delayed by the second delay circuit 1203-1, 1203-2, . . . and 1203-n, respectively, and after being added to the gain parameters generated according to the delayed digital output signal N.sub.r[k.sub.d], new candidate gain parameters may be generated and updated into the registers Re1, Re2, . . . and Ren.
[0049] For example, if the TDC 500 shown in FIG. 11 generates a digital output signal N.sub.r[l], the MUX 1101 shown in FIG. 11 may be controlled by the digital output signal N.sub.r[l] and output the candidate gain parameter K.sub.TDC1 stored in the register Re1 for being utilized as the gain parameter K.sub.TDC. The digital output signal N.sub.r[k] may be delayed by the first delay circuit 1107 shown in FIG. 11 to generate a delayed digital output signal N.sub.r[l.sub.d] (not shown). The LMS circuit 523 may generate a delayed gain parameter K.sub.TDC1d according to the delayed digital output signal N.sub.r[l.sub.d] and a phase error Ø.sub.E[l], and the adder 1201_1 may add the delayed gain parameter K.sub.TDC1d with the candidate gain parameter K.sub.TDC1 and update the result into the register Re1.
[0050] Note that the embodiments of FIG. 11 and FIG. 12 are for illustrative purposes only, where any circuit architecture that is cable of reaching the same function should belong to the scope of the present invention. A calibration method of an ADPLL may be known according to the embodiments of FIG. 11 and FIG. 12. The calibration method comprises the following steps: utilizing a DCO of the ADPLL to generate a clock signal according to a frequency control signal; utilizing a TDC of the ADPLL to generate a digital output signal according to a phase error between the clock signal and a reference signal; utilizing a normalization circuit of the ADPLL to convert the digital output signal into a clock phase value according to a gain parameter; and utilizing the normalization circuit to select one of a plurality of candidate gain parameters in response to the digital output signal, for being utilized as the gain parameter. Other detailed steps may be deduced according to the previous embodiments, and are therefore omitted here for brevity.
[0051] The ADPLL and the calibration method thereof provided by the embodiments of the present invention can select corresponding gain parameters according to the digital output signal, to improve the linearity of the TDC. The calibration method of the present invention is not limited to resolution of the TDC. In addition, the ADPLL and the calibration method will not greatly increase additional costs. Thus, the present invention can solve the problem of the related art without introducing any side effect or in a way that is less likely to introduce side effects.
[0052] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
