Semiconductor Chip of Light Emitting Diode and Quantum Well Layer Thereof and Manufacturing Method Thereof

Abstract

A semiconductor chip of a light emitting diode includes a substrate, and an N-type gallium nitride layer, a quantum well layer, and a P-type gallium nitride layer stacked on the substrate successively, an N-type electrode electrically connected to the N-type gallium nitride layer, and a P-type electrode electrically connected to the P-type gallium nitride layer. The quantum well layer includes at least one quantum barrier and at least one quantum well stacked successively in sequence, wherein the growth pressure of the quantum barrier and the growth pressure of the quantum well are different, such that the interface crystal quality between the quantum well and the quantum barrier of the quantum well layer can be greatly improved to enhance the luminous efficiency of the semiconductor chip.

Claims

1. A semiconductor chip of a light emitting diode, comprising: a substrate; an N-type gallium nitride layer, which is stacked on said substrate; a quantum well layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer comprises one or more quantum barriers and one or more quantum wells stacked successively in sequence, wherein a growth pressure of said one or more quantum barriers and a growth pressure of said one or more quantum wells are different; a P-type gallium nitride layer, wherein said P-type gallium nitride layer is stacked on said quantum well layer; an N-type electrode, electrically connected to said N-type gallium nitride layer; and a P-type electrode, electrically connected to said P-type gallium nitride layer.

2. The semiconductor chip, as recited in claim 1, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells of said quantum well layer.

3. The semiconductor chip, as recited in claim 2, wherein a number of layers of said quantum barrier and a number of layers of said quantum well of said quantum well layer are both parameterized as N, having a value range of: 3N20.

4. The semiconductor chip, as recited in claim 1, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N (0<X1<1, 0<Y1<1), having a doped concentration of 1-51018 cm-3, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N (0<X2<1, 0<Y2<1).

5. The semiconductor chip, as recited in claim 4, wherein each of said one or more quantum barriers of said quantum well has a thickness ranging from 5 nm-15 nm, and each of said one or more quantum wells has a thickness ranging from 2 nm-5 nm.

6. The semiconductor chip, as recited in claim 3, wherein each of said one or more quantum barriers of said quantum well layer is a doped quantum barrier of Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N (0<X1<1, 0<Y1<1), having a doping concentration of 151018 cm3, wherein each of said one or more quantum wells of said quantum well layer is an undoped quantum well of Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N (0<X2<1, 0<Y2<1), wherein each of said one or more quantum barriers of said quantum well has a thickness ranging from 5 nm-15 nm, and each of said one or more quantum wells has a thickness ranging from 2 nm-5 nm.

7. The semiconductor chip, as recited in claim 1, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer.

8. The semiconductor chip, as recited in claim 7, wherein said buffer layer is selected from the group consisting of a GaN buffer layer and an AlN buffer layer.

9. The semiconductor chip, as recited in claim 6, further comprising a buffer layer, wherein said buffer layer is stacked on said substrate and said N-type gallium nitride layer is stacked on said buffer layer, wherein said buffer layer is selected from the group consisting of a GaN buffer layer and an AlN buffer layer.

10. The semiconductor chip, as recited in claim 1, further comprising a current spreading layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer is stacked on said current spreading layer.

11. The semiconductor chip, as recited in claim 10, wherein said current spreading layer is selected from the group consisting of an N-type current spreading layer, an AlGaN type current spreading layer, and an InGa current spreading layer.

12. The semiconductor chip, as recited in claim 6, further comprising a current spreading layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer is stacked on said current spreading layer, wherein said current spreading layer is selected from the group consisting of an N-type current spreading layer, an AlGaN type current spreading layer, and an InGaN current spreading layer.

13. The semiconductor chip, as recited in claim 9, further comprising a current spreading layer, which is stacked on said N-type gallium nitride layer, wherein said quantum well layer is stacked on said current spreading layer, wherein said current spreading layer is selected from the group consisting of an N-type current spreading layer, an AlGaN type current spreading layer, and an InGaN current spreading layer.

14. The semiconductor chip, as recited in claim 1, further comprising a protective layer, which is stacked on said quantum well layer and said P-type gallium nitride layer is stacked on said protective layer.

15. The semiconductor chip, as recited in claim 14, wherein further comprising an electron blocking layer, which is stacked on said protective layer, and said P-type gallium nitride layer is stacked on said electron blocking layer.

16. The semiconductor chip, as recited in claim 15, wherein said N-type electrode is stacked on said current spreading layer and said P-type electrode is stacked on said P-type gallium nitride layer.

17. The semiconductor chip, as recited in claim 6, further comprising a protective layer and an electron blocking layer, wherein said protective layer is stacked on said quantum well layer and said P-type gallium nitride layer is stacked on said protective layer, wherein said electron blocking layer is stacked on said protective layer, and said P-type gallium nitride layer is stacked on said electron blocking layer, wherein said N-type electrode is stacked on said current spreading layer and said P-type electrode is stacked on said P-type gallium nitride layer.

18. The semiconductor chip, as recited in claim 9, further comprising a protective layer and an electron blocking layer, wherein said protective layer is stacked on said quantum well layer and said P-type gallium nitride layer is stacked on said protective layer, wherein said electron blocking layer is stacked on said protective layer, and said P-type gallium nitride layer is stacked on said electron blocking layer, wherein said N-type electrode is stacked on said current spreading layer and said P-type electrode is stacked on said P-type gallium nitride layer.

19. The semiconductor chip, as recited in claim 13, further comprising a protective layer and an electron blocking layer, wherein said protective layer is stacked on said quantum well layer and said P-type gallium nitride layer is stacked on said protective layer, wherein said electron blocking layer is stacked on said protective layer, and said P-type gallium nitride layer is stacked on said electron blocking layer, wherein said N-type electrode is stacked on said current spreading layer and said P-type electrode is stacked on said P-type gallium nitride layer.

20. A manufacturing method of a semiconductor chip of a light emitting diode, comprising the steps of: (a) stacking an N-type gallium nitride layer on a substrate; (b) cyclically growing one or more quantum barriers and one or more quantum wells from said N-type gallium nitride layer to form a quantum well layer, wherein said one or more quantum barriers and said one or more quantum wells are stacked successively in sequence on said N-type gallium nitride layer, wherein a growth pressure of said quantum barrier and a growth pressure of said quantum well are different; (c) stacking a P-type gallium nitride layer on said quantum well layer; and (d) electrically connecting an N-type electrode to said N-type gallium nitride layer and electrically connecting a P-type electrode to said P-type gallium nitride layer.

21. The manufacturing method, as recited in claim 20, wherein said growth pressure of said one or more quantum barriers is lower than said growth pressure of said one or more quantum wells.

22. The manufacturing method, as recited in claim 21, wherein in the step (b), further comprises the steps of: (b.1) maintaining said substrate stacked with said N-type gallium nitride layer in a metal-organic chemical vapor deposition device; (b.2) introducing In source, Ga source, nitrogen source, and silane into said metal-organic chemical vapor deposition device to grow said doped quantum barrier of Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N (0<X1<1, 0<Y1<1) to form said one or more quantum barriers stacked on said N-type gallium nitride layer; (b.3) reducing a pressure of said metal-organic chemical vapor deposition device, and introducing said In source, said Ga source, and said nitrogen source to said metal-organic chemical vapor deposition device to grow said undoped quantum well of Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N (0<X2<1, 0<Y2<1) to form said one or more quantum wells stacked on said quantum barrier; and (b.4) circulating the step (b.2) and said step (b.3) to stack said quantum well layer on said N-type gallium nitride layer.

23. The manufacturing method, as recited in claim 20, before the step (a), further comprising a step of growing a buffer layer from said substrate, so that in the step (a), said N-type nitrogen gallium layer is grown on said buffer layer.

24. The manufacturing method, as recited in claim 20, before the step (b), further comprising a step of growing a current spreading layer from said N-type gallium nitride layer, so that in the step (b), said quantum well layer is grown on said current spreading layer.

25. The manufacturing method, as recited in claim 20, before the step (c), further comprising the steps of growing a protective layer from said quantum well layer and growing an electron blocking layer from said protective layer, so that in the step (c), said P-type gallium nitride layer is grown on said electron blocking layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG. 1 is a sectional view illustrating a step one of a manufacturing method of a semiconductor chip according to a preferred embodiment of the present invention.

[0056] FIG. 2 is a sectional view illustrating a step two of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0057] FIG. 3 is a sectional view illustrating a step three of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0058] FIG. 4 is a sectional view illustrating a step four of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0059] FIG. 5 is a sectional view illustrating a step five of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0060] FIG. 6 is a sectional view illustrating a step six of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0061] FIG. 7 is a sectional view illustrating a step seven of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0062] FIG. 8 is a sectional view illustrating a step eight of the manufacturing method of the semiconductor chip according to the above preferred embodiment of the present invention.

[0063] FIG. 9 is a sectional view illustrating the semiconductor chip and a step nine of the manufacturing method thereof according to the above preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0064] The following description is disclosed to enable any person skilled in the art to make and use the present invention. Preferred embodiments are provided in the following description only as examples and modifications will be apparent to those skilled in the art. The general principles defined in the following description would be applied to other embodiments, alternatives, modifications, equivalents, and applications without departing from the spirit and scope of the present invention.

[0065] As shown in FIGS. 1 to 9 of the present invention, a semiconductor chip of a light emitting diode according to a preferred embodiment of the present invention is disclosed and illustrated in the following description. The semiconductor chip comprises a substrate 10, an N-type gallium nitride layer 20, a quantum well layer 30, a P-type gallium nitride layer 40, an N-type electrode 50, and a P-type electrode 60, wherein the N-type gallium nitride layer 20 is stacked on the substrate 10, the quantum well layer 30 is stacked on the N-type gallium nitride layer 20, the P-type gallium nitride layer 40 is stacked on the quantum well layer 30, the N-type electrode 50 is electrically connected to the N-type gallium nitride layer 20, and the P-type electrode 60 is electrically connected to the P-type gallium nitride layer 40. When the N-type electrode 50 and the P-type electrode 60 of the semiconductor chip are respectively inputted with power source, a current flowing from the N-type electrode 50 into the semiconductor chip can enter the well layer 30 through the N-type gallium nitride layer 20, and a current flowing from the P-type electrode 60 into the semiconductor chip can enter the quantum well layer 30 through the P-type gallium nitride layer 40, such that the currents are combined at the quantum well layer 30 to produce light.

[0066] Specifically, the quantum well layer 30 comprises one or more quantum wells and one or more quantum barriers stacked successively in sequence, wherein an interface crystal quality between the quantum well and the quantum barrier of the quantum well layer 30 can be greatly improved to enhance the luminous efficiency of the semiconductor chip. More specifically, both the number of the quantum wells and the number of the quantum barrier of the quantum well layer 30 are defined as parameter N. That is, in the process of manufacturing the semiconductor chip, the quantum wells and quantum barriers are grown in N cycles to form the quantum well layer 30, such that the first quantum barrier of the quantum well layer 30 is stacked on the N-type gallium nitride layer 20, and the first quantum well of the quantum well layers 30 is stacked on the first quantum barrier, and that the second quantum barrier of the quantum well layer 30 is stacked on the first quantum well, and the second quantum well of the quantum well layers 30 is stacked on the second quantum well, and so on. The Nth quantum barrier of the quantum well layer 30 is stacked on the N-1th quantum well, and the Nth quantum well of the quantum well layer 30 is stacked on the Nth quantum barrier, wherein the interface crystal quality between the adjacent quantum well and the quantum barrier can be greatly improved, for enhancing the luminous efficiency of the semiconductor chip. For example, the uniformity of the interface crystal quality between the quantum well and the quantum barrier of the quantum well layer 30 can be improved, for enhancing the interface crystal quality between the quantum well and the quantum barrier.

[0067] In this preferred embodiment of the semiconductor chip, as shown in FIGS. 1 to 9, the parameter N has a value range of 3N20, that is, the quantum well layer 30 of the semiconductor chip comprises the quantum barriers and the quantum wells in 3 to 20 cycles (including 3 cycles and 20 cycles). In other words, the number of layers of the quantum barrier of the quantum well layer 30 of the semiconductor chip and the number of layers of the quantum well both are 3 to 20 layers (including 3 layers and 20 layers).

[0068] According to this preferred embodiment of the semiconductor chip of the present invention, the quantum barrier of the quantum well layer 30 and the quantum well have different growth pressures, depending on the material of the quantum barrier and the quantum well. A suitable pressure is selected in such a manner that the interface crystal quality between the quantum well and the quantum barrier can be greatly improved to enhance the luminous efficiency of the semiconductor chip.

[0069] Specifically, in a preferred embodiment of the semiconductor chip of the present invention, the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well to improve the interface crystal quality between the quantum well and the quantum barrier of the quantum well layer 30. In the process of growing the quantum well layer 30, when the quantum barrier of the quantum well layer 30 is grown in a lower pressure growth environment, atomic migration of the quantum barrier can be enhanced to promote the surface of the quantum barrier grown two-dimensionally, which facilitates the improvement of the well-barrier interface crystal quality between the quantum well and the quantum barrier.

[0070] Preferably, the N-type gallium nitride layer 20 of the semiconductor chip is a silicon (Si) doped gallium nitride layer, wherein the N-type gallium nitride layer 20 has a doping concentration of 11010.sup.18 cm.sup.3. More preferably, the N-type gallium nitride layer 20 of the semiconductor chip has a thickness ranging from 3 m to 6 m (including 3 m and 6 m).

[0071] Preferably, the P-type gallium nitride layer 40 of the semiconductor chip is a doped gallium nitride layer, wherein the P-type gallium nitride layer 40 has a doping concentration of 51010.sup.18 cm.sup.3. More preferably, the P-type gallium nitride layer 40 of the semiconductor chip has a thickness ranging from 100 nm to 200 nm (including 100 nm and 200 nm).

[0072] In addition, the material of the N-type electrode 50 is Ti (titanium) or Al (aluminum). Correspondingly, the material of the P-type electrode 60 is Ni (nickel) or Au (gold).

[0073] Further referring to FIGS. 1 to 9, the semiconductor chip further comprises a buffer layer 70, wherein the buffer layer 70 is stacked on the substrate 10 and the N-type gallium nitride layer 20 is stacked on the buffer layer 70. The N-type gallium nitride layer 20 is stacked on the substrate 10 such that the N-type gallium nitride layer 20 is stacked on the substrate 10. Accordingly, the N-type gallium nitride layer 20 is stacked on the buffer layer 70 and the buffer layer 70 is stacked on the substrate 10. In the semiconductor chip, the buffer layer 70 can avoid the problem of lattice mismatch in a manner of being retained between the N-type gallium nitride layer 20 and the substrate 10, so as to facilitate the assurance of the stability and reliability of semiconductor chips.

[0074] In a preferred embodiment of the semiconductor chip of the present invention, the buffer layer 70 is a gallium nitride buffer layer. For example, the buffer layer 70 may be, but not limited to, an undoped gallium nitride buffer layer. When the buffer layer 70 is an undoped gallium nitride buffer layer, the buffer layer 70 has a thickness ranging from 20 nm to 50 nm (including 20 nm and 50 nm). Alternatively, in other embodiments of the semiconductor chip of the present invention, the buffer layer 70 is an AlN buffer layer.

[0075] Please further referring to FIGS. 1-9, the semiconductor chip further comprises a current spreading layer 80, wherein the current spreading layer 80 is stacked on the N-type gallium nitride layer 20 and the quantum well layer 30 is stacked on the N-type gallium nitride layer 20. Accordingly, the quantum well layer 30 is stacked on the current spreading layer 80 and the current spreading layer 80 is stacked on the N-type gallium nitride layer 20. The N-type electrode 50 is electrically connected to the N-type gallium nitride layer 20 in a manner that the N-type electrode 50 is electrically connected to the current spreading layer 80 and the current spreading layer 80 is electrically connected to the N-type gallium nitride layer 20, such that a current flowing through the N-type electrode 50 can enter the quantum well layer 30 through the N-type gallium nitride layer 20 after being expanded and spread by the current spreading layer 80.

[0076] In a preferred embodiment of the semiconductor chip of the present invention, the current spreading layer 80 is an N-type current spreading layer. Alternatively, in another preferred embodiment of the semiconductor chip of the present invention, the current spreading layer 80 is AlGaN current spreading layer or InGaN current spreading layer.

[0077] Furthermore, when the current spreading layer 80 is an N-type current spreading layer, the current spreading layer 80 comprises at least one NGaN layer and at least one UGaN layer, wherein the NGaN layer and the UGaN layers are stacked one on another, such that the current spreading layer 80 can have a low resistance-high resistance-low resistance-high resistance . . . kind of resistance state in growth direction. Accordingly, on the one hand, the current spreading layer 80 causes the longitudinal resistance of the semiconductor chip to be increased to weaken the longitudinal current spreading capability of the semiconductor chip.

[0078] On the other hand, the current spreading layer 80 enables the horizontal current spreading capability of the semiconductor chip to be effectively improved. Thereby, it is advantageous for the current to be uniformly distributed and to improve the luminous efficiency, which has a large improvement in the luminous performance and the service life span of the semiconductor chip.

[0079] Referring to FIGS. 1 to 9, the semiconductor chip further comprises a protective layer 90, wherein the protective layer 90 is stacked on the quantum well layer 30 to maintain crystal quality of the quantum well layer 30, for avoiding destruction of the composition and structure of the quantum well layer 30 during next growth process. Preferably, the protective layer 90 is a GaN cap layer. Preferably, the protective layer 90 has a thickness ranging from 30 nm to 100 nm (including 30 nm and 100 nm).

[0080] Referring to FIGS. 1 to 9, the semiconductor chip further comprises an electron blocking layer 100, wherein the electron blocking layer 100 is stacked on the protective layer 90, and the P-type gallium nitride layer 40 is stacked on the quantum well layer 30 in a manner that the P-type gallium nitride layer 40 is stacked on the electron blocking layer 100, the electron blocking layer 100 is stacked on the protective layer 90, and the protective layer 90 is stacked on the quantum well layer 30. The electron blocking layer 100 has a wider bandgap, which can reduce electron leakage, increase the radiation recombination rate, and enhance the luminous efficiency.

[0081] Preferably, the electron blocking layer 100 is a P-type AlGaN electron blocking layer. The electron blocking layer 100 has a doping concentration of 11010.sup.18 cm.sup.3. Preferably, the electron blocking layer 100 has a thickness ranging from 0.1 m to 0.5 m (including 0.1 m and 0.5 m).

[0082] In the following description, the substrate 10, the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the P-type gallium nitride layer 40, the N-type electrode 50, and the P-type electrode 60 and connections thereof are further described with the growth process of the semiconductor chip to illustrate features of the semiconductor chip of the present invention.

[0083] In particular, under conditions of a reaction growth pressure ranging from 100 torr to 500 torr (including 100 torr and 500 torr), the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the P-type gallium nitride layer 40, the N-type electrode 50, and the P-type electrode 60 are sequentially grown from the substrate 10.

[0084] More specifically, the growing steps of the semiconductor chip includes:

[0085] S1, growing the buffer layer 70 from the substrate 10; S2;

[0086] S2, growing the N-type gallium nitride layer 20 from the buffer layer 70;

[0087] S3, growing the current spreading layer 80 from the N-type gallium nitride layer 20;

[0088] S4, growing the quantum well layer 30 from the current spreading layer 80;

[0089] S5, growing the protective layer 90 from the quantum well layer 30;

[0090] S6, growing the electron blocking layer 100 from the protective layer 90;

[0091] S7, growing the P-type gallium nitride layer 40 from the electron blocking layer 100; and

[0092] S8, growing the N-type electrode 50 from the current spreading layer 80 and the P-type electrode 60 are grown from the P-type gallium nitride layer 40.

[0093] Next, each growth step of the above-described preferred embodiment of the semiconductor chip according to the present invention is described in detail as follows.

[0094] In step S1, the buffer layer 70 is grown from the substrate 10, as shown in FIG. 2. Specifically, firstly, the substrate 10 is placed in a metal-organic chemical vapor deposition device (MOCVD). Next, high purity hydrogen (H2) is introduced into the metal organic compound vapor phase epitaxy apparatus at a temperature of about 1100 C., wherein the last time of high purity hydrogen (H2) is in the range of 10 minutes to 15 minutes (including 10 minutes and 15 minutes). Thirdly, the Ga source and the N source are introduced into the metal-organic chemical vapor deposition device when the temperature is lowered to 900 C.1000 C. (including 900 C. and 1000 C.) to grow the buffer layer 70 on the substrate 10, so that the buffer layer 70 is stacked on the substrate 10.

[0095] Preferably, the buffer layer 70 is an undoped gallium nitride buffer layer. Preferably, the buffer layer 70 has a thickness ranging from 20 nm to 50 nm (including 20 nm and 50 nm).

[0096] It is worth to mention that the type of the substrate 10 is not limited in the semiconductor chip of the present invention. For example, the substrate 10 may be a sapphire substrate, an AlN substrate, a SiC substrate, and a Si substrate.

[0097] Next, in step S2, the N-type gallium nitride layer 20 is grown from the buffer layer 70, as shown in FIG. 3. Specifically, Ga source, nitrogen source, and silane (SiH4) are introduced into the metal-organic chemical vapor deposition device when the temperature of the chamber raised up to 1100 C.-1200 C. (including 1100 C. and 1200 C.) to grow silicon (Si)-doped N-type gallium nitride layer 20 from the buffer layer 70, so that the N-type gallium nitride layer 20 is stacked on the buffer layer 70, Ga source/nitrogen source (NH3) is an essential element for growth, and N2 is carrier gas., and silane (SiH4) is dopant source.

[0098] It would be understand by person skilled in the art that, since the buffer layer 70 is grown on the substrate 10 and the N-type gallium nitride layer 20 is grown on the buffer layer 70, the buffer layer 70 is maintained between the substrate 10 and the N-type gallium nitride layer 20. Therefore, the problem of lattice mismatch between the substrate 10 and the N-type gallium nitride layer 20 can be avoided, so that it is advantageous to ensure the stability and reliability of the semiconductor chip.

[0099] Preferably, the N-type gallium nitride layer 20 has a thickness ranging from 3 m to 6 m (including 3 m and 6 m). Preferably, the N-type gallium nitride layer 20 has a silicon doping concentration of 11010.sup.18 cm.sup.3.

[0100] Next, in the step S3, the current spreading layer 80 is grown from the N-type gallium nitride layer 20, as shown in FIG. 4. For example, in a preferred embodiment of the semiconductor chip of the present invention, after the N-type gallium nitride layer 20 is grown in the buffer layer 70, Ga source, nitrogen source, and silane (SiH4) are continuously introduced into the metal-organic chemical vapor deposition device to grow a silicon-doped NGaN layer from the N-type gallium nitride layer 20, and then Ga source and nitrogen source are introduced to grow the undoped UGaN layer on the NGaN layer, for cyclically growing the NGaN layer and the UGaN layer for 5 cycles to 30 cycles (including 5 cycles and 30 cycles), so as to form the current spreading layer 80. Accordingly, the current spreading layer 80 can allow a more even distribution of current.

[0101] Specifically, since the NGaN layer of the current spreading layer 80 is a silicon doped layer and the UGaN layer is an undoped layer, the NGaN layer and the UGaN layer 32 of the current spreading layer 80 have different resistances, so that the current spreading layer 80 can have a low resistance-high resistance-low resistance-high resistance . . . resistance state in the growth direction of the semiconductor chip. Accordingly, on the one hand, the current spreading layer 80 causes the longitudinal resistance of the semiconductor chip to be increased, to weaken the longitudinal current spreading capability of the semiconductor chip, and on the other hand, the current spreading layer 80 makes the horizontal current spreading capability of the semiconductor chip being effectively improved, to facilitate uniformly distribution of current and improve luminous efficiency of the semiconductor chip, that has a highly improvement in optical performance and service life span of the semiconductor chip. In addition, a thickness of the NGaN layer and a thickness of the UGaN layer of the current spreading layer 80 can affect the resistance of the NGaN layer and resistance of the UGaN layer. Thus, by adjusting the thickness of the NGaN layer and the thickness of the UGaN layer of the current spreading layer 80, current can be more uniformly distributed to improve the luminous efficiency of the semiconductor chip.

[0102] Next, in the step S4, the quantum well layer 30 is grown from the current spreading layer 80, as shown in FIG. 5. Specifically, firstly, the temperature of a cavity of the metal-organic chemical vapor deposition device is lowered to 800 C.-900 C. (including 800 C. and 900 C.), and In source, Ga source, nitrogen source, and silane (SiH4) are introduced into the cavity of the metal-organic chemical vapor deposition device for growing the quantum barrier from the current spreading layer 80, wherein the quantum barrier has a doping concentration of 1510.sup.18 cm.sup.3, and the quantum barrier is in a thickness range of 5 nm-15 nm (including 5 nm and 15 nm) of Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N (0<X1<1, 0<Y1<1) quantum barrier. Secondly, raising the pressure of the cavity of the metal-organic chemical vapor deposition device to grow the undoped quantum well from the quantum barrier, wherein the quantum well is in a thickness range of 2 nm to 5 nm (including 2 nm and 5 nm) of Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N (0<X2<1, 0<Y2<1) quantum wells. Growing the quantum barrier from the quantum well after lowering the pressure of the cavity of the metal-organic chemical vapor deposition device in the above manner, and after raising the pressure of the cavity of the metal-organic chemical vapor deposition device, the quantum well is grown from the quantum barrier. The growth times are 3 cycles to 20 cycles to form the quantum well layer 30.

[0103] In other words, in the semiconductor chip of the present invention, the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well. Accordingly, the atomic migration of the quantum barrier can be enhanced to promote the two-dimensional growth of the surface of the quantum barrier, for facilitating the improvement of the well-barrier interface crystal quality between the quantum well and the quantum barrier, to improve the luminous efficiency of the semiconductor chip. Moreover, the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well, so that the incorporation of the group III element can be promoted in the process of growing the quantum barrier, such as the In element. Thus, when the blue-green light of the semiconductor chip is grown, more quantum dots can be provided to enhance the luminous efficiency of the semiconductor chip.

[0104] For example, in the quantum well layer 30 of AlInGaN, the quantum well has the growth pressure of 200 torr-300 torr (including 200 torr and 300 torr), and the growth pressure of the quantum barrier is lower than the growth pressure of the quantum well. Of course, it should be understood by those skilled in the art that the growth pressure of the quantum barrier of the quantum well layer 30 is lower than the growth pressure of the quantum well by 5 torr-10 torr as an example for disclosure the content and scope of the semiconductor chip of the present invention not to be construed as limiting the description and scope of the present invention. For example, when selecting the growth pressure of the quantum well and the quantum barrier of the quantum well layer 30, a Transmission Electron Microscope (TEM)/X-ray Diffractometer (XRD) may be used to determine the crystal quality of a well-barrier interface of the quantum well and the quantum barrier or luminous efficiency of the semiconductor chip under the same conditions to select suitable growth pressures of the quantum well and the quantum barrier.

[0105] It is worth to mention that the structure and growth mode of the quantum well layer 30 of the semiconductor chip of the present invention is applicable to the semiconductor chip of the full color system. For example, the structure and growth mode of the quantum well layer 30 are suitable for InGaN-based blue-green light and AlGaN-based ultraviolet light.

[0106] Next, in the step S5, the protective layer 90 is grown from the quantum well layer 30, as shown in FIG. 6. Specifically, after the internal temperature range of the metal-organic chemical vapor deposition device is lowered to 700 C.-800 C. (including 700 C. and 800 C.), Ga source and nitrogen source are introduced into the metal-organic chemical vapor deposition device to grow the protective layer 90 on the quantum well layer 30 such that the protective layer 90 is stacked on the quantum well layer 30. That is, the protective layer 90 is the low temperature GaN cap layer stacked on the quantum well layer 30. Preferably, the protective layer 90 has a thickness ranging from 30 nm to 100 nm (including 30 nm and 100 nm). By growing the protective layer 90 to the quantum well layer 30, the crystal quality of the quantum well layer 30 can be maintained during next growth processes, for avoiding subsequent high temperature growth damaging the composition and/or structure of the quantum well layer 30.

[0107] Next, in step S6, the electron blocking layer 100 is grown from the protective layer 90, as shown in FIG. 7. Specifically, after the internal temperature of the metal organic compound vapor phase epitaxy apparatus is raised to 900 C.-1000 C (including 900 C. and 1000 C.), Al source, Ga source, nitrogen source, and Mg source are introduced to grow magnesium-doped the electron blocking layer 100 of AlGaN, wherein the doping concentration is 11010.sup.18 cm.sup.3, wherein the Al source, the Ga source, and the nitrogen source are growth sources, N2 is carrier gases, the Mg source is a doped source. Preferably, the electron blocking layer 100 has a thickness ranging from 0.1 m to 0.5 m (including 0.1 m and 0.5 m).

[0108] Next, in step S7, the P-type gallium nitride layer 40 is grown from the electron blocking layer 100, as shown in FIG. 8. Specifically, Ga source, nitrogen source, and Mg source are introduced into the metal-organic chemical vapor deposition device to grow the Mg-doped P-type gallium nitride layer 40 on the electron blocking layer 100, wherein Ga source and nitrogen source are growth sources, and Mg source is dopant source

[0109] Preferably, the P-type gallium nitride layer 50 has a thickness ranging from 100 nm to 200 nm (including 100 nm and 200 nm). Preferably, the P-type gallium nitride layer 50 has a doping concentration of 51010.sup.18 cm.sup.3.

[0110] In addition, annealing at a temperature ranging from 800 C. to 900 C. (including 800 C. and 900 C.) in a nitrogen (N2) atmosphere for 20 minutes to 30 minutes (including 20 minutes and 30 minutes) to complete the growth of the semiconductor chip. It is worth to mention that, before annealing, the growth step further comprises the step S8, growing the N-type electrode 50 from the current spreading layer 80 and growing the P-type electrode 60 from the P-type gallium nitride layer 40, as shown in FIG. 9.

[0111] According to another aspect of the present invention, the present invention further provides a manufacturing method of a semiconductor chip, wherein the manufacturing method comprises the steps of:

[0112] (a) stacking the N-type gallium nitride layer 20 on the substrate 10;

[0113] (b) cyclically growing the one or more quantum barriers and the one or more quantum wells from the N-type gallium nitride layer 20 to form the quantum well layer 30 on the N-type nitride gallium layer 20 by stacking the quantum barriers and the quantum wells on the N-type gallium nitride layer 20 in sequence successively, wherein the growth pressure of the quantum barrier and the growth pressure of the quantum well are different;

[0114] (c) stacking said P-type gallium nitride layer 40 on the quantum well layer 30; and

[0115] (d) electrically connecting the N-type electrode 50 to the N-type gallium nitride layer 20 and electrically connecting the P-type electrode 60 to the P-type gallium nitride layer 40 to produce the semiconductor chip.

[0116] Preferably, the cycle times for growing the quantum barrier and the quantum well are from 3 cycles to 20 cycles.

[0117] Preferably, the growth pressure of the quantum barrier is lower than the growth pressure of the quantum well.

[0118] In the step (b), the manufacturing method further comprises the steps of:

[0119] (b.1) maintaining the substrate 10 stacked with the N-type gallium nitride layer 20 in the metal-organic chemical vapor deposition device;

[0120] (b.2) introducing In source, Ga source, nitrogen source, and silane into the metal-organic chemical vapor deposition device to grow doped Al.sub.x1In.sub.y1Ga.sub.1-x1-y1N (0<X1<1, 0<Y1<1) quantum barrier to form the corresponding quantum barrier layered on the N-type gallium nitride layer 20;

[0121] (b.3) reducing the pressure of the metal-organic chemical vapor deposition device, and introducing In source, Ga source, and nitrogen source to the metal-organic chemical vapor deposition device to grow undoped Al.sub.x2In.sub.y2Ga.sub.1-x2-y2N (0<X2<1, 0<Y2<1) quantum well to form the corresponding quantum well stacked on the quantum barrier; and

[0122] (b.4) cycling the step (b.2) and the step (b.3) to stack the quantum well layer 30 on the N-type gallium nitride layer 20.

[0123] According to the present invention, it is appreciated that the stacking/stacked used in the present invention could be a direct stacking or an indirect stacking. For example, stacking the N-type gallium nitride layer 20 on the substrate 10 may include the meaning that the N-type gallium nitride layer 20 is indirectly stacked on the substrate 10, that is other layers may be disposed between the N-type gallium nitride layer 20 and the substrate 10. For example, the buffer layer 70 may be disposed between the N-type gallium nitride layer 20 and the substrate 10. Correspondingly, stacking the buffer layer 70 on the substrate 10 may also include the meaning that the buffer layer 70 is directly layered on the substrate 10, that is the buffer layer 70 is grown directly on the substrate 10.

[0124] It should be noted that the thicknesses of the substrate 10, the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the N-type electrode 50, and the P-type electrode 60 of the semiconductor chip as shown in the drawings of the present invention are merely for illustration purpose as example, but not intending to represent the actual real thicknesses of the substrate 10, the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the N-type electrode 50, and the P-type electrode 60. Moreover, person skilled in the art should realize that the real dimensional proportion of the substrate 10, the buffer layer 70, the N-type gallium nitride layer 20, the current spreading layer 80, the quantum well layer 30, the protective layer 90, the electron blocking layer 100, the N-type electrode 50, and the P-type electrode 60 are not exactly as shown in the drawings.

[0125] One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

[0126] It will thus be seen that the objects of the present invention have been fully and effectively accomplished. The embodiments have been shown and described for the purposes of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention comprises all modifications encompassed within the spirit and scope of the following claims.