DIFFERENTIAL TRANS-IMPEDANCE AMPLIFIER

Abstract

In conventional high data rate receivers, the transmitted optical signal has poor extinction ratio and translates into a small modulated current with a large DC current, which saturates the receiver TIA and amplifiers, and significantly degrades the gain and bandwidth performance. Consequently, cancelling PD DC current in high data rate receivers is desired for proper operation. Differential TIA schemes, i.e. providing separate AC-coupled and DC-coupled paths, in parallel, provide better linearity for large input currents and low gain settings. To AC couple the PD to the TIA using passive AC-coupling circuitry, an AC-coupling capacitor (C.sub.C) is positioned between the PD and the TIA to block the DC current, while passing the modulated AC current to the TIA. A DC cancellation circuit may be provided, without a capacitor, to maintain the receiver input bias while suppressing any DC component generated by the PD for the DC-coupled path.

Claims

1. An optical receiver comprising: a photodetector configured to generate a differential input current including a first input current component and a second input current component in response to an optical signal; a trans-impedance amplifier (TIA) comprising a first TIA section and a second TIA section, the first TIA section configured to convert the first input current component into a first input voltage component, and the second TIA section configured to convert the second input current component into a second input voltage component; a variable gain amplifier (VGA) configured to amplify the first input voltage component and the second input voltage component to a desired output voltage forming a first output voltage component and a second output voltage component; an AC coupler in an AC-coupled path for AC coupling the first TIA section to the photodetector; and a DC coupler in a DC-coupled path, absent a capacitor, for DC coupling the second TIA section to the photodetector.

2. The optical receiver according to claim 1, wherein the photodetector includes an anode and a cathode; wherein the cathode is AC coupled to the first TIA section; and wherein the anode is DC coupled to the second TIA section.

3. The optical receiver according to claim 1, wherein the AC coupler comprises a coupling capacitor.

4. The optical receiver according to claim 3, wherein the coupling capacitor has a capacitance of less than 10 pF.

5. The optical receiver according to claim 3, wherein the AC coupler further comprises a coupling resistor in parallel with the coupling capacitor.

6. The optical receiver according to claim 5, wherein the coupling resistor comprises a resistance of less than 10 k.

7. The optical receiver according to claim 5, wherein the AC coupler further comprises a bias voltage source connected to the coupling resistor for reverse biasing the photodetector.

8. The optical receiver according to claim 7, wherein the bias voltage source comprises a voltage of 2 to 6 volts.

9. The optical receiver according to claim 1, wherein the DC coupler comprises: a DC cancellation circuit (DCCC) for cancelling a DC component of the second input current components or the second input voltage component by comparing the second input current component or the second input voltage component to a reference current or a reference voltage generating a comparison, and sinking the DC component of the second input current component based on the comparison.

10. The optical receiver according to claim 9, wherein the photodetector includes an anode and a cathode; wherein the cathode is AC coupled to the first TIA section; wherein the anode is DC coupled to the second TIA section; and wherein an anode voltage of the anode is set based on the reference voltage.

11. The optical receiver according to claim 9, wherein the DC cancellation circuit comprises: a voltage comparator for comparing a sample of the second input current component or the second input voltage component to the reference voltage or current, generating the comparison; and a current sink for sinking the DC component of the second input current component based on the comparison.

12. The optical receiver according to claim 11, wherein the reference voltage is between 0.3V and 1.5V.

13. The optical receiver according to claim 11, further comprising a replica TIA configured to generated the reference voltage.

14. The optical receiver according to claim 11, further comprising a DCCC sensing point positioned before the TIA enabling the DC cancellation circuit to sample the second input current component.

15. The optical receiver according to claim 11, further comprising a DCCC sensing point positioned after the TIA enabling the DC cancellation circuit to sample the second input voltage component.

16. The optical receiver according to claim 1, wherein the first TIA section includes a first shunt feedback impedance comprising a first feedback resistor and a second feedback resistor in parallel, and a shunt feedback capacitor in series with the first feedback resistor; and wherein the second TIA section includes a second shunt feedback impedance comprising a third feedback resistor; wherein each of the first feedback resistor and the second feedback resistor comprise a resistance about twice a resistance of the third feedback resistor, whereby below a desired frequency an overall resistance of the first TIA section is twice that of the second TIA section to boost gain at frequencies below the desired frequency, and whereby above the desired frequency the overall resistance of the first TIA section is equal to the second TIA section.

17. The optical receiver according to claim 16, wherein the resistance of the third feedback resistor comprises between 500 and 1000.

18. The optical receiver according to claim 16, wherein the feedback capacitor comprises a capacitance of between 5 pF and 10 pF.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The invention will be described in greater detail with reference to the accompanying drawings which represent preferred embodiments thereof, wherein:

[0017] FIG. 1 is a schematic diagram of a conventional photodetector circuit;

[0018] FIG. 2 is a schematic diagram of a conventional differential photodetector circuit with AC coupling;

[0019] FIG. 3 is a schematic diagram of a differential photodetector circuit with a mixed coupling scheme in accordance with an exemplary embodiment of the present invention;

[0020] FIG. 4 is a schematic diagram of the differential photodetector circuit of FIG. 3, with a DC cancellation circuit;

[0021] FIG. 5A is a schematic diagram of a shunt feedback TIA for the DC coupled path; and

[0022] FIG. 5B is a schematic diagram of a shunt feedback TIA for the AC coupled path.

DETAILED DESCRIPTION

[0023] While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.

[0024] Compared to the above described single-ended schemes, a differential TIA scheme has advantages because the differential signal becomes 2 larger, while the RMS added random noise is only 2 larger, and therefore the differential TIA has increased SNR by only 2. Moreover, differential TIA schemes provide better linearity for large input currents and low gain settings due to better common mode rejection ratio (CMRR) by 2.sup.nd harmonics rejection. Improved linearity is critical in PAM4 or higher order modulation schemes.

[0025] With reference to FIG. 3, an optical receiver 20, in accordance with the present invention, comprises of a photodetector, e.g. photo diode (PD), 21 followed by a trans-impedance amplifier (TIA) 22 and main voltage amplifiers (MAs) 23. The PD 21 and the TIA 22 may be disposed on separate integrated circuit chips, e.g. photonic integrated circuit (PIC) 24 and an RF integrated circuit (RFIC) 25, respectively. The PD 21 receives a transmitted optical signal 26, and generates a differential current signal comprised of a first current component 27a and a second current component 27b, proportional to the received optical power of the transmitted optical signal 26. The trans-impedance amplifier (TIA) 22 may be comprised of a first TIA section 22a and a second TIA section 22b, each of the first and second TIA sections 22a and 22b are configured for converting one of the first and second current components 27a and 27b, respectively, of the differential current signal into a differential voltage signal comprising a first voltage component 28a and a second voltage components 28b. The MAs 23 may include one or more of a variable gain amplifier (VGA) 29 configured for amplifying the first and second components 27a and 27b of the voltage signal, a limiting amplifier 30 for attenuating the first and second components 27a and 27b of the voltage signal, and a driver stage 31 for driving subsequent stages, e.g. an ADC. The PD 21 may be provided on the separate photonic integrated circuit (PIC) 24 including one or more transducers, such as one or more photodetectors 21 or on the same IC 25 as the remainder of the optical receiver 20. The back end of the optical receiver 20 may be connected to an output load, e.g. a digital signal processor (DSP) 32 for converting the output of the optical receiver 20 into digital signals.

[0026] The PD 21 includes an anode 33 and a cathode 34, which are coupled to two different paths, i.e. an DC-coupled signal path and a AC-coupled signal path, respectively. To AC couple the PD 21 to the TIA 22 using passive AC-coupler circuitry, an AC-coupling capacitor (C.sub.C) 36 is positioned between the photodetector 21 and the TIA 22 to block the DC current, while passing the modulated AC current to the TIA 22. A biasing resistor (R.sub.C) 37 extending from the AC-coupled path to a biasing voltage source V.sub.PD is used to bias the voltage from the cathode 34 to be reverse biased, and provides an alternative path for the photo diode DC current I.sub.DC. The biasing resistor R.sub.C 37 with the AC-coupling capacitor C.sub.C 36 form a high pass filter section in the RF AC-coupled signal path, whereby the cutoff frequency (F.sub.C) is calculated as,

[00002]$\begin{array}{cc}{F}_C=\frac{1}{2.Math..Math..Math.R_C.Math.C_C}& \left(4\right)\end{array}$

[0027] However, the latest photodetectors require a TIA low cutoff frequency (F.sub.C) around 1 MHz, which requires either a large AC coupling capacitance C.sub.C or a huge biasing resistance R.sub.C. As an example, a coupling capacitor 36 with a coupling capacitance C.sub.C of 4 pF would require a biasing resistor 37 with a biasing resistance R.sub.C of at least 40 k to achieve cutoff frequency of 1 MHz, resulting in a photodiode biasing voltage of over 20V for 0.5 mA of input current, which is unacceptable. As stated above, this technique also suffers from two main drawbacks: 1) parasitic capacitance, and 2) photo diode biasing. For bulk silicon technologies, the bottom plate ground parasitic capacitance of the coupling capacitor 36 is around 10% of its value and degrades the bandwidth of the front-end of the TIA 22, which is defined by its input node capacitance. Thus, there is a maximum coupling capacitance C.sub.C for the coupling capacitor 36 that can be used without degrading the bandwidth of the TIA 22. Accordingly, a coupling capacitance C.sub.C of less than 10 pF, preferably less than 6 pF, and more preferably between 2 pF and 5 pF is preferred for the coupling capacitor 36 as an AC coupler for the AC-coupled path. A resistance of less than 10 k, preferably less than 6 k, and more preferably between 2 k and 5 k may be used as R.sub.C in the biasing resistor 37 in the AC coupler for the AC-couple path.

[0028] However, to further reduce and control the V.sub.BIAS, the anode voltage V.sub.B from the DC coupling path may be preset, as hereinafter described, whereby the biasing voltage across the photodetector 21 is defined by the following equation:

V.sub.BIAS=V.sub.PDV.sub.B(I.sub.DCR.sub.C),(5)

[0029] where V.sub.BIAS is the reverse biasing voltage across the PN junction of the photodetector 21, V.sub.PD is the photodiode bias voltage from a bias voltage source, I.sub.PD is the DC current (average current) through the photodetector 21 caused by the incoming light, and V.sub.B is the voltage from Anode 33 or the TIA input voltage, as will be discussed below with reference to FIG. 4. The photodiode bias voltage V.sub.PD may be between 2 volts and 6 volts, preferably about 4 volts. A high photo diode reverse biasing voltage V.sub.BIAS is required to obtain good photo diode responsivity and low PN junction capacitance. However, equation (5) shows that V.sub.BIAS depends on PD average current (I.sub.DC) and leads to different PD biasing for different received optical power. Furthermore, a large resistance R.sub.C value in the biasing resistor 37 impedes receiving high optical power levels as the DC current I.sub.DC will be large and the voltage drop across the biasing resistor 37 will be huge. As a numerical example, a DC current I.sub.DC of 10 A leads to a 10 V drop on a 1 M biasing resistance R.sub.C for the biasing resistor 37, which is not practical. Moreover, the situation in coherent optical receivers is much worse as the photodiode DC current I.sub.DC is approximately 1 mA and requires a biasing resistance R.sub.C of less than 1 k for less than a 1 V drop across the biasing resistor 37.

[0030] With reference to FIG. 4, a DC cancellation circuit 41 may be provided as a DC coupler, in the absence of a coupling capacitor, to maintain the receiver input bias while suppressing any DC component at the input generated by the PD 21 for the DC-coupled path, as disclosed in U.S. patent application Ser. No. 16/135,914, entitled Optical Receivers with DC Cancellation and Offset Cancellation, filed Sep. 19, 2018, which is incorporated herein by reference. The DC cancellation circuit 41 uses a closed loop 42 in which a sample voltage or current is compared to a reference voltage (or current) V.sub.REF. V.sub.REF may be the optimum input bias for the TIA 22, and therefore depends on the TIA circuit topology. Typically, V.sub.REF may be 0.3V to 1.5V, and ideally about 1V, but other TIA designs may utilize a V.sub.REF above or below these values. V.sub.REF is an on-chip (or off-chip) reference voltage that may be designed to be invariant, e.g. bandgap voltage, or have a temperature or process dependency. The closed loop 42 may be used to define the output or the input bias condition. The reference voltage V.sub.REF may be generated by a replica TIA with open input. The reference voltage (or current) V.sub.REF is selected to guarantee proper operation of the receiver 20. DC cancellation circuit (DCCC) sensing points for the DC cancellation circuit 41 may be positioned before the second TIA section 22b enabling the DC cancellation circuit 41 to sample the second current component 27b or after the second TIA section 22b enabling the DC cancellation circuit to sample the second voltage component 28b.

[0031] In the DC cancellation circuit 41, the reference voltage signal V.sub.REF is compared in a voltage comparator OA with one of the sensing input points, e.g. taken at the input or the output of the second TIA section 22b generating a comparison. The difference, i.e. the comparison, between the sensed point and the modified reference voltage signals V.sub.REF is used to control a first terminal, e.g. gate, of a first feedback transistors, e.g. N.sub.FET, to sink the input DC current of the second current component 27b (I.sub.IN_DC) of the DC-coupled path via the second and third terminals, e.g. drain and source, of the feedback transistor N.sub.FET, and set the DC input voltage (V.sub.B) V.sub.IN_DC for the second TIA section 22b to be about equal to V.sub.REF, e.g. 0.3 V to 1.5 V, preferably 0.6 V to 1.1 V.

[0032] Due to the limited time-constant from the biasing resistance R.sub.C of the biasing resistor 37 and the capacitance C.sub.C of the coupling capacitor 36 in the AC-coupled path, the low cut-off frequency (F.sub.C) may be higher than the link specification (1 MHz). However, a low frequency gain boosting of the impedance in the shunt-feedback of the first TIA section 22a in the AC-coupled path may resolve this problem. With reference to FIG. 5A, a first shunt feedback impedance 50a for the first TIA section 22a may be comprised of two, parallel shunt feedback resistors 51 in top and bottom paths, with a feedback capacitor 52 with capacitance C.sub.S in series with one of the shunt feedback resistors 51, e.g. in top path. With reference to FIG. 5B, a typical TIA section, e.g. the second TIA section 22b, includes a second shunt feedback impedance 50b, based on a single shunt feedback resistor 53 with resistance R.sub.S. Each of the parallel shunt feedback resistors 51 may comprise approximately twice the shunt feedback resistance 2R.sub.S of the feedback resistor 53 of the second shunt feedback impedance 50b in the second TIA section 22b in the DC-coupled path Whereby, below the RC cut-off frequency, the feedback capacitor 52 of the top path (F.sub.C=1/(2C.sub.S2R.sub.S)) is open, the TIA gain is twice the normal gain due to the doubling of the shunt-feedback resistance (2R.sub.S) of the bottom path. Whereby, above a desired threshold, e.g. the RC cut-off frequency F.sub.C, the feedback capacitor 52 is closed, the effective overall resistance is the same as the second TIA section 22b, i.e. two resistors in parallel: R.sub.S (R.sub.S+R.sub.s=1/R.sub.S), and the high frequency gain, e.g. above the cut-off frequency F.sub.C, is the same as in the second TIA section 22b. A shunt feedback resistance R.sub.S of between 500 and 1000 may be used, with a feedback capacitance C.sub.S of between 5 pF and 10 pF may be used; however, any suitable resistance and capacitance may be used.

[0033] A flatter AC response at low frequency improves the low frequency group-delay variation (GDV) significantly, and the improved GDV enables a reduction in BER.

[0034] The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.