FREQUENCY SYNTHESIS DEVICE WITH HIGH MULTIPLICATION RANK

Abstract

A frequency synthesis device with high multiplication rank, including a base frequency generator generating two first base signals of square shape of same frequency and opposite to each other, a first synthesis stage including two first switching power supply oscillators, of which the power supplies are respectively switched by the two first base signals, a second synthesis stage including a second switching power supply oscillator of which the supply is switched by a combination of the output signals of the two first oscillators, the output of the second switching power supply oscillator being filtered by a frequency discriminator circuit realized with an injection locked oscillator.

Claims

1-7. (canceled)

8. A frequency synthesis device comprising: a base frequency generator suited to generating a plurality K of first base signals, said first base signals being clock signals with non-overlapping phases, of same frequency f.sub.1; a first synthesis stage including a plurality K of first switching power supply oscillators of identical structure and of same natural frequency, f.sub.G.sup.1, the power supplies of these K first oscillators being respectively switched by said K base signals, the output signals of these K first oscillators being combined to supply a second base signal, of square shape and periodic, of frequency f.sub.2=Nf.sub.1 where N is an integer; a second synthesis stage including a second switching power supply oscillator of which the supply is switched by the second base signal, the output signal of this second oscillator being in the form of wave trains, the repetition frequency of these wave trains being equal to f.sub.2 and the frequency of these waves being equal to Mf.sub.2 where M is an integer, the second synthesis stage further including a frequency discriminator circuit adapted to filtering the output signal of the second oscillator to supply a sinusoidal signal at the frequency Mf.sub.2.

9. The frequency synthesis device according to claim 8, wherein the output signals of the K first oscillators are summed after having been respectively square shaped in K shaping circuits.

10. The frequency synthesis device according to claim 8, wherein the K first switching power supply oscillators are VCO type oscillators and that they are controlled by a same control voltage.

11. The frequency synthesis device according to claim 8, wherein the frequency discriminator circuit is an injection locked oscillator of which the resonance band includes the frequency Mf.sub.2.

12. The frequency synthesis device according to claim 8, wherein the duty cycles of the first base signals are all equal to 1/K.

13. The frequency synthesis device according to claim 8, wherein K=2, the two first base signals being opposite to each other.

14. The frequency synthesis device according to claim 8, wherein the base frequency generator comprises a voltage controlled oscillator, frequency locked and in phase with a PLL loop on a reference frequency supplied by a quartz resonator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other characteristics and advantages of the invention will become clear on reading a preferential embodiment of the invention, described with reference to the appended figures among which:

[0037] FIG. 1 schematically represents a frequency synthesis device known from the prior art;

[0038] FIG. 2 represents a time chart of signals present at different points of the synthesis device of FIG. 1;

[0039] FIG. 3 represents a frequency synthesis device with high multiplication order employing the cascading of several frequency synthesis stages;

[0040] FIG. 4 represents a time chart of signals present at different points of the frequency synthesis device of FIG. 3;

[0041] FIG. 5 schematically represents a frequency synthesis device with high multiplication order and with simplified structure;

[0042] FIG. 6 represents a time chart of signals present at different points of the frequency synthesis device with simplified structure of FIG. 5;

[0043] FIG. 7 represents the spectrum of the signal at the output of the second switching power supply oscillator of FIG. 5;

[0044] FIG. 8 schematically represents a frequency synthesis device with high multiplication order, according to a first embodiment of the invention;

[0045] FIG. 9 represents a time chart of signals present at different points of the frequency synthesis device of FIG. 8;

[0046] FIG. 10 represents the spectrum of the signal at the output of the second switching power supply oscillator of FIG. 8;

[0047] FIG. 11 schematically represents a frequency synthesis device with high multiplication order, according to a second embodiment of the invention.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0048] A frequency synthesis device with several synthesis stages according to the principle of FIG. 3 is again considered. A first basic idea of the invention is to do without the frequency recovery circuit to obtain a device with simplified structure.

[0049] FIG. 5 schematically represents such a frequency synthesis device with high multiplication order and with simplified structure.

[0050] This device, 500, includes a base frequency generator, 510, identical to the generator 310, a first stage, 520, comprising a first switching power supply oscillator, 521, a shaping circuit (square or pseudo-square), 525, and a second stage, 530, including a second switching power supply oscillator, 531, and a frequency recovery circuit, 532.

[0051] FIG. 6 represents a time chart of signals present at different points of the frequency synthesis device with simplified structure of FIG. 5.

[0052] The first line of the time chart corresponds to the signal s.sub.1 at the output of the base frequency generator, serving for the switching of the power supply of the first oscillator 521.

[0053] The second line corresponds to the signal s.sub.2 at the output of the shaping circuit 525, serving for the switching of the power supply of the second oscillator 531.

[0054] The third line corresponds to the signal s.sub.G.sup.2 at the output of the second switching power supply oscillator, 531.

[0055] The final line corresponds to the signal s.sub.out at the output of the frequency recovery circuit 532.

[0056] It is noted here that the signal s.sub.G.sup.2 is zero when the signal s.sub.1 is zero, this zero crossing occurring at the rhythm of the base frequency f.sub.1. In other words, the spectrum S.sub.G.sup.2 of s.sub.G.sup.2 comprises a large number of lines spaced apart by f.sub.1, as may furthermore be observed in FIG. 7.

[0057] In FIG. 7 are represented the different steps (A)-(G) making it possible to calculate the spectrum S.sub.G.sup.2, with, on the left, the representation of these steps in the temporal domain and, on the right, the corresponding representation in the frequency domain.

[0058] The signal s.sub.G.sup.2 may be expressed in the form:

[00004]$\begin{array}{cc}{S}_G^2\left(t\right)=\left(e^{j.Math..Math.2.Math..Math..Math.f_G^2.Math.t}.Math..Math.(.Math.\frac{t}{t_w^2})\right).Math.\left(.Math.\left(\frac{t}{T_1}\right).Math.\left(.Math.\left(\frac{t}{t_w^1}\right)\right).Math..Math.\left(\frac{t}{T_2}\right)\right)& \left(3\right)\end{array}$

where

[00005]$.Math.\left(\frac{t}{T}\right)$

represents the port function of width T,

[00006]$.Math.\left(\frac{t}{T}\right)=\underset{k=-}{\overset{+}{.Math.}}.Math.\left(t-\mathrm{kT}\right)$

is a Dirac comb of period T, t.sub.w.sup.1 is the width of the pulse in the base signal

[00007]$(t_w^1=\frac{T_1}{2}$

for a signal of duty cycle ), T.sub.1=1/f.sub.1, T.sub.2=1/f.sub.2, and f.sub.G.sup.2Mf.sub.2=NMf.sub.1.

[0059] The steps (A)-(G) of constructing the signal s.sub.G.sup.2 are represented in the left part of the figure, these steps corresponding to the operations appearing from right to left in the expression (3).

[0060] The spectrum S.sub.G.sup.2 is then expressed as follows:

[00008]$\begin{array}{cc}{S}_G^2\left(f\right)=\left(\sin .Math..Math.c\left(\frac{f-f_G^2}{2.Math.f_2}\right)\right).Math.\left(.Math.\left(\frac{f}{f_1}\right).Math.\left(\sin .Math..Math.c\left(\frac{f}{f_w^1}\right)\right).Math..Math.\left(\frac{f}{f_2}\right)\right)& \left(4\right)\end{array}$

with f.sub.w.sup.1=1/t.sub.w.sup.1 (2f.sub.1 if the duty cycle is ).

[0061] At line (G) may be noted the presence of a large number of spectral lines spaced apart by f.sub.1, coming from the repetition of the pattern PT indicated in FIG. 5. The selection of the line at the frequency NMf.sub.1 is very delicate and requires an injection locked oscillator with very high quality factor (ratio of the natural frequency of the oscillator over the resonance band width). Moreover, the fact of having available a very narrow resonance band considerably reduces the locking range of the oscillator ILO.

[0062] A second basic idea of the invention is to eliminate the comb of lines spaced apart by f.sub.1 in the spectrum S.sub.G.sup.2 using a plurality of base signals at the frequency f.sub.1 and with non-overlapping phases as described hereafter.

[0063] FIG. 8 schematically represents a frequency synthesis device with high multiplication order, according to a first embodiment of the invention.

[0064] The frequency synthesis device, 800, includes a base frequency generator, 810, generating two square clock signals at the frequency f.sub.1 and opposite to each other, s.sub.1 and s.sub.1. These two base signals come for example from complementary outputs Q and Q of a flip-flop D of which the input CK receives a clock signal at the frequency 2f.sub.1 supplied by a quartz resonator, 805. Alternatively, the signal s.sub.1 could be obtained from s.sub.1 by means of an inverter, 807, as represented, the signal s.sub.1 furthermore passing through a delay element, 806, in such a way that the signals at the output of 806 and 807 are temporally aligned. Obviously, it would be possible in the same way to use an oscillator VCO servo-controlled by means of a loop PLL on a sub-multiple frequency of f.sub.1 supplied by the quartz resonator to generate the base signals s.sub.1 and s.sub.1.

[0065] The base signals s.sub.1 and s.sub.1 respectively switch the power supply of two first switching power supply oscillators, 821.sup.1 and 821.sup.2. These two first oscillators are VCOs of identical structure controlled by the same control voltage, V.sub.ctrl.sup.1 and thus have the same natural oscillation frequency (that is to say in non-switched regime), f.sub.G.sup.1. The oscillators 821.sup.1 and 821.sup.2 consequently phase locks on the same harmonic at the frequency Nf.sub.1.

[0066] The signals at the output of the oscillators 821.sup.1 and 821.sup.2, noted respectively s.sub.G.sup.1,1 and s.sub.G.sup.1,2, are pulsed sinusoidal oscillations, a pulse of s.sub.G.sup.1,1 corresponding to a zero voltage interval in s.sub.G.sup.1,2 and vice versa.

[0067] The signals s.sub.G.sup.1,1 and s.sub.G.sup.1,2 are respectively square shaped in the shaping circuits 825.sup.1 and 825.sup.2. After shaping, these signals are summed by means of a port OR, 827, to supply a second base signal, s.sub.2. Unlike the signals s.sub.G.sup.1,1 and s.sub.G.sup.1,2, the signal s.sub.2=s.sub.G.sup.1,1+s.sub.G.sup.1,2 is not pulsed and its fundamental frequency is equal to Nf.sub.1.

[0068] This second base signal switches the power supply of a second switching power supply oscillator, 831. This oscillator is of VCO type and is controlled by a control voltage V.sub.crtl.sup.2. The natural oscillation frequency of the oscillator corresponding to this control voltage is noted f.sub.G.sup.2. The oscillator phase locks on a harmonic of f.sub.2=Nf.sub.1 at the frequency Mf.sub.2=MNf.sub.1, the control voltage V.sub.ctrl.sup.2 makes it possible to select the order M of the harmonic. The signal s.sub.G.sup.2 at the output of the oscillator 831 is in the form of wave trains repeating at the repetition frequency f.sub.2, the frequency of the oscillations within a wave train being equal to Mf.sub.2.

[0069] The signal s.sub.G.sup.2 is supplied to a frequency recovery (or discriminator) circuit, 832, realized in the form of an ILO oscillator as indicated previously. When the frequency Mf.sub.2 of the injected signal falls within the resonance frequency band of the ILO oscillator, the oscillator phase locks on the injection signal to supply a sinusoidal signal (non-pulsed) at the frequency Mf.sub.2, stable in frequency and in phase.

[0070] The frequency recovery circuit 832 does not need a quality factor as high as the frequency recovery circuit 532. Indeed, the spectrum S.sub.G.sup.2 of s.sub.G.sup.2 not having rays spaced apart by f.sub.1 but only f.sub.2=Nf.sub.1, the constraint on the resonance band width may be relaxed by a factor N.

[0071] In practice, the characteristic parameters of the ILO oscillator will be chosen in such a way that the natural frequency of the ILO oscillator is close to the target frequency and V.sub.ctrl.sup.1 and/or V.sub.ctrl.sup.2 will be varied in such a way that a ray is situated as close as possible to Mf.sub.2 to obtain the maximum output power.

[0072] Those skilled in the art will understand that the frequency synthesis device of FIG. 8 includes two synthesis stages, 820 and 830, only the second is equipped with a frequency discriminator circuit, which makes it possible to reduce the energy consumption of the device.

[0073] FIG. 9 represents a time chart of signals present at different points of the frequency synthesis device of FIG. 8.

[0074] The two first lines (A) and (B) of the time chart represent the base signals s.sub.1 and s.sub.1. It is here assumed that the duty cycles of these signals were equal to . In the general case, they may be equal to and 1 even if the value = is preferred.

[0075] The following two lines (C) and (D) of the time chart represent the signals s.sub.G.sup.1,1 and s.sub.G.sup.1,2 supplied by the two first switching power supply oscillators, after they have been shaped in the circuits 825.sup.1 and 825.sup.2. The line (E) represents for its part the second base signal s.sub.2.

[0076] The line (F) of the time chart represents the signal s.sub.G.sup.2 at the output of the third switching power supply oscillator.

[0077] Finally, the final line (G) represents the output signal, s.sub.out, supplied by the frequency recovery circuit.

[0078] FIG. 10 represents the spectrum of the signal at the output of the second switching power supply oscillator of FIG. 8.

[0079] The left part of the figure gives a temporal representation of the signals and the right part the corresponding frequency representation.

[0080] On account of the complementary of the signals s.sub.1 and s.sub.1, the switching signal s.sub.2 is not pulsed and the signal s.sub.G.sup.2(t) is expressed simply in the form:

[00009]$\begin{array}{cc}{s}_G^2\left(t\right)=e^{j.Math..Math.2.Math..Math..Math.f_G^2.Math.t}.Math..Math.(.Math.\frac{t}{t_w^2}).Math..Math.\left(\frac{t}{T_2}\right)& \left(5\right)\end{array}$

[0081] The spectrum of this signal is thus given by:

[00010]$\begin{array}{cc}{S}_G^2\left(f\right)=\left(\sin .Math..Math.c\left(\frac{f-f_G^2}{2.Math.f_2}\right)\right).Math..Math.\left(\frac{f}{f_2}\right)& \left(6\right)\end{array}$

[0082] It may be noted that the rays at intervals of f.sub.1 have been eliminated and that it is consequently much easier to produce the frequency discriminator circuit 832 to select the target frequency.

[0083] FIG. 11 schematically represents a frequency synthesis device with high multiplication order, according to a second embodiment of the invention.

[0084] This second embodiment may be considered as a generalisation of the first in so far as it uses as base signals frequency time clocks f.sub.1 with non-overlapping phases, noted s.sub.1.sup.i, i=1, . . . , K.

[0085] Signals with non-overlapping phases designate square signals of same frequency, s.sup.i, i=1, . . . , K, being able conventionally to take the logic values 0 or 1, such that:

[00011]$\begin{array}{cc}{s}^i*s^j=0,ij.Math..Math.\mathrm{and}.Math..Math.\underset{i=1}{\overset{K}{.Math.}}.Math.s^i=1& \left(7\right)\end{array}$

where * signifies the logic multiplication (AND) and the sum is a logic sum (OR).

[0086] In this embodiment, the base frequency generator, 1110, generates a plurality K of first base signals s.sub.1.sup.i, i=1, . . . , K of frequency f.sub.1 and with non-overlapping phases. The duty cycles .sub.i of these first base signals may be distinct but bear out the relationship

[00012]$\underset{i=1}{\overset{K}{.Math.}}.Math.{}_i=1.$

Preferably however, the duty cycles .sub.i will all be chosen equal to 1/K. The whole number K will advantageously be chosen equal to a power of 2 for reasons of ease of implementation.

[0087] The first base signals s.sub.1.sup.i, i=1, . . . , K switch respectively the power supply of K switching power supply oscillators, 1121.sup.1, . . . , 1121.sup.K.

[0088] These K oscillators are VCOs of identical structure controlled by a same control voltage, V.sub.ctrl.sup.1, and thus have the same natural oscillation frequency f.sub.G.sup.1. They phase lock on the same harmonic at the frequency Nf.sub.1.

[0089] Each of the signals at the output of the oscillators 1121.sup.1, . . . , 1121.sup.K noted s.sub.G.sup.1,i, i=1, . . . , K, has pulsed sinusoidal oscillations, each pulse of s.sub.G.sup.1,i corresponding to a zero voltage interval in the signals s.sub.G.sup.1,j, ji.

[0090] The signals s.sub.G.sup.1,i, i=1, . . . , K are respectively square shaped in the shaping circuits 1125.sup.1, . . . , 1125.sup.K. After shaping, these signals are summed by means of a port OR, 827, to supply a second base signal, s.sub.2. Unlike the signals s.sub.G.sup.1,j, i=1, . . . , K, the signal

[00013]$s_2=\underset{i=1}{\overset{K}{.Math.}}.Math.s_G^{1,i}$

is not pulsed and its fundamental frequency is equal to Nf.sub.1.

[0091] The second base signal s.sub.2 switches the power supply of the (K+1).sup.th switching power supply oscillator, 1131, this oscillator phase locks on a harmonic of f.sub.2=Nf.sub.1 at the frequency Mf.sub.2=MNf.sub.1 as in the first embodiment. The signal s.sub.G.sup.2 at the output of the oscillator is supplied to the frequency recovery circuit, 1132, realized in the form of an ILO oscillator, to supply a non-pulsed sinusoidal signal, s.sub.out, at the frequency Mf.sub.2, stable in frequency and in phase.

[0092] The frequency synthesis device of FIG. 11 includes two synthesis stages, 1120 and 1130, only the second is equipped with a frequency discriminator circuit to supply the target frequency.