POWER CONVERTER WITH ASYMMETRIC SWITCH LEVELS

Abstract

Described embodiments include a circuit for limiting power converter output ripple. A first transistor has a first current terminal receiving an input voltage, and a second current terminal coupled to a first capacitor. A second transistor has a third current terminal coupled to the first capacitor, and a fourth current terminal is coupled to a second capacitor. A third transistor has a fifth current terminal coupled to the second capacitor, and a sixth terminal coupled to a filter input. A fourth transistor has a seventh current terminal coupled to the second current terminal, and an eighth current terminal coupled to the sixth current terminal. A fifth transistor has a ninth current terminal coupled to the fourth current terminal, and a tenth current terminal coupled to the sixth current terminal.

Claims

1. An integrated circuit for limiting power converter output ripple, the integrated circuit comprising: a first transistor having first and second current terminals, the first current terminal coupled to an input voltage terminal, the second current terminal coupled to a first capacitive terminal; a second transistor having third and fourth current terminals, the third current terminal coupled to a second capacitive terminal, and the fourth current terminal coupled to a third capacitive terminal; a third transistor having fifth and sixth current terminals, the fifth current terminal coupled to a fourth capacitive terminal, and the sixth terminal coupled to a filter input terminal; a fourth transistor having seventh and eighth current terminals, the seventh current terminal coupled to the second current terminal, and the eighth current terminal coupled to the filter input terminal; and a fifth transistor having ninth and tenth current terminals, the ninth current terminal coupled to the fourth current terminal, and the tenth current terminal coupled to the filter input terminal.

2. The integrated circuit of claim 1, further comprising: a sixth transistor having eleventh and twelfth current terminals, the eleventh current terminal coupled to the third current terminal, and the twelfth current terminal coupled to a ground terminal; and a seventh transistor having thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the fifth current terminal, and the fourteenth current terminal coupled to the ground terminal.

3. The integrated circuit of claim 1, wherein an output voltage terminal is adapted to be coupled to a first terminal of an inductor, and the filter input terminal is adapted to be coupled to a second terminal of the inductor.

4. The integrated circuit of claim 2, wherein the integrated circuit is configured to operate on a cycle having first, second, third and fourth sequential operating stages that recur.

5. The integrated circuit of claim 4, wherein the first, second and third transistors are configured to turn on, and the fourth, fifth, sixth and seventh transistors are configured to turn off during the first operating stage if a voltage at the input voltage terminal is at least three times a voltage at the output voltage terminal.

6. The integrated circuit of claim 5, wherein the third and seventh transistors are configured to turn on, and the first, second, fourth, fifth and sixth transistors are configured to turn off during the second operating stage.

7. The integrated circuit of claim 6, wherein the fourth, fifth, sixth and seventh transistors are configured to turn on, and the first, second and third transistors are configured to turn off during the third operating stage.

8. The integrated circuit of claim 7, wherein the third and seventh transistors are configured to turn on, and the first, second, fourth, fifth and sixth transistors are configured to turn off during the fourth operating stage.

9. The integrated circuit of claim 1, in which the first, second, third, fourth, fifth, sixth and seventh transistors are FETs.

10. The integrated circuit of claim 4, wherein, responsive to a voltage at the input voltage terminal being less than three times a voltage at the output voltage terminal: the first, second and third transistors are configured to turn on, and the fourth, fifth, sixth and seventh transistors are configured to turn off during the first operating stage; the first and fourth transistors are configured to turn on, and the second, third, fifth, sixth and seventh transistors are configured to turn off during the second operating stage; the fourth, fifth, sixth and seventh transistors are configured to turn on, and the first, second and third transistors are configured to turn off during the third operating stage; and the first and fourth transistors are configured to turn on, and the second, third, fifth, sixth and seventh transistors are configured to turn off during the fourth operating stage.

11. A circuit for limiting power converter output ripple, comprising: a first capacitor having first and second capacitor terminals; a second capacitor having third and fourth capacitor terminals; a first transistor having first and second current terminals, the first current terminal coupled to an input voltage terminal, the second current terminal coupled to the first capacitor terminal; a second transistor having third and fourth current terminals, the third current terminal coupled to a second capacitor terminal, and the fourth current terminal coupled to the third capacitor terminal; a third transistor having fifth and sixth current terminals, the fifth current terminal coupled to the fourth capacitor terminal, and the sixth current terminal coupled to an input of a filter; a fourth transistor having seventh and eighth current terminals, the seventh current terminal coupled to the second current terminal, and the eighth current terminal coupled to the sixth current terminal; and a fifth transistor having ninth and tenth current terminals, the ninth current terminal coupled to the fourth current terminal, and the tenth current terminal coupled to the sixth current terminal.

12. The integrated circuit of claim 11, further comprising: a sixth transistor having eleventh and twelfth current terminals, the eleventh current terminal coupled to the third current terminal, and the twelfth current terminal coupled to a ground terminal; and a seventh transistor having thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the fifth current terminal, and the fourteenth current terminal coupled to the ground terminal.

13. The integrated circuit of claim 11, wherein the filter includes: an inductor having first and second inductor terminals, the first inductor terminal coupled to the eighth current terminal, and the second inductor current terminal coupled to an output voltage terminal; and a third capacitor coupled between the output voltage terminal and the ground terminal.

14. The integrated circuit of claim 12, wherein the integrated circuit is configured to operate on a cycle having first, second, third and fourth sequential operating stages that recur.

15. The integrated circuit of claim 14, wherein the first, second and third transistors are configured to turn on, and the fourth, fifth, sixth and seventh transistors are configured to turn off during the first operating stage responsive to a voltage at the input voltage terminal being at least three times a voltage at the output voltage terminal.

16. The integrated circuit of claim 15, wherein the third and seventh transistors are configured to turn on, and the first, second, fourth, fifth and sixth transistors are configured to turn off during the second operating stage.

17. The integrated circuit of claim 16, wherein the fourth, fifth, sixth and seventh transistors are configured to turn on, and the first, second and third transistors are configured to turn off during the third operating stage.

18. The integrated circuit of claim 17, wherein the third and seventh transistors are configured to turn on, and the first, second, fourth, fifth and sixth transistors are configured to turn off during the fourth operating stage.

19. The integrated circuit of claim 11, in which the first, second, third, fourth, fifth, sixth and seventh transistors are FETs.

20. The integrated circuit of claim 14, wherein responsive to a voltage at the input voltage terminal being less than three times a voltage at the output voltage terminal: the first, second and third transistors are configured to turn on, and the fourth, fifth, sixth and seventh transistors are configured to turn off during the first operating stage; the first and fourth transistors are configured to turn on, and the second, third, fifth, sixth and seventh transistors are configured to turn off during the second operating stage; the fourth, fifth, sixth and seventh transistors are configured to turn on, and the first, second and third transistors are configured to turn off during the third operating stage; and the first and fourth transistors are configured to turn on, and the second, third, fifth, sixth and seventh transistors are configured to turn off during the fourth operating stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows a block diagram for an example mobile phone battery charger system including a power converter.

[0011] FIG. 2 shows a schematic diagram for a buck power converter having two switching voltage levels.

[0012] FIG. 3 shows a schematic diagram for a symmetric three-level buck power converter.

[0013] FIG. 4 shows a schematic diagram for an asymmetric three-level buck power converter.

DETAILED DESCRIPTION

[0014] In this description, the same reference numbers depict the same or similar (by function and/or structure) features. The drawings are not necessarily drawn to scale.

[0015] Buck power converters have an input voltage that is higher than the regulated output voltage. The conversion ratio of a power converter is the ratio of the input voltage to the output voltage. Numerous applications today call for a buck power converter having a conversion ratio of three or greater. An example of an application requiring a high conversion ratio is a mobile phone battery charger.

[0016] FIG. 1. shows a block diagram for an example mobile phone battery charger system 100 that includes a power converter. Mobile phone battery charging system 100 has two switchable sources for input power, USB connector 102 and wireless receiver 104. In at least one case, USB connector 102 is connected to a USB cable that delivers power derived from an AC power source through a power conversion adapter. Alternatively, wireless receiver 104 may deliver power from a charging mat or a similar wireless power source.

[0017] Power converter 108 includes the following terminals: VBUS 110, GND 112, V.sub.OUT 114, and BAT 116. Power is supplied from USB connector 102 or wireless receiver 104 to VBUS 110 at a voltage V.sub.IN. A system ground reference can be connected to GND 112. A battery 118 can be connected to the BAT terminal 116. Power converter 108 has output V.sub.OUT 114 which can be coupled to power input terminals of other devices in the system, providing a regulated voltage source.

[0018] FIG. 2 shows a schematic diagram for a buck converter 200 having two switching voltage levels. Transistor Q.sub.1 is coupled between an input voltage terminal at a voltage V.sub.IN and a switching node 210, which is at a voltage V.sub.SW. Transistor Q.sub.2 is coupled between the switching node 210 and ground. An output terminal V.sub.OUT has a load impedance Z.sub.L.

[0019] The control terminal of Q.sub.1 is coupled to a controller that provides control signal CNTL1. The control terminal of Q.sub.2 is coupled to the controller and receives control signal CNTL2. Signals CNTL1 and CNTL2 turn transistors Q.sub.1 and Q.sub.2 on and off, modulating the on times of Q.sub.1 and Q.sub.2 to maintain a desired regulated output voltage at V.sub.OUT while ensuring that Q.sub.1 and Q.sub.2 are never on at the same time.

[0020] An inductor L.sub.O is coupled between the switching node 210 and output terminal V.sub.OUT. Capacitor C.sub.O is connected in parallel with load impedance Z.sub.L and is coupled to inductor L.sub.O. Capacitor C.sub.O and inductor L.sub.O provide filtering for the output voltage V.sub.OUT, filtering ripple present on the signal V.sub.SW. The inductance value of inductor L.sub.O is chosen to be proportional to the magnitude of the ripple on the signal V.sub.SW. A larger ripple voltage on V.sub.SW requires a larger inductor to absorb the ripple.

[0021] Turning on Q.sub.1 while Q.sub.2 is turned off makes V.sub.SW equal to V.sub.IN minus the drain-to-source voltage drop across Q.sub.1. Turning off Q.sub.1 and turning Q.sub.2 on makes V.sub.SW equal to ground plus the drain-to-source voltage drop across Q.sub.2. Hence, the voltage at switching node 210, V.sub.SW, switches approximately between V.sub.IN and ground. Because the magnitude of the ripple voltage on V.sub.OUT is proportional to the magnitude of the voltage swing at V.sub.SW, reducing this voltage swing reduces the magnitude of the ripple voltage present on V.sub.SW.

[0022] FIG. 3 shows a schematic diagram for a symmetric three-level buck converter 300. The symmetric three-level buck converter switches the voltage V.sub.SW at the switch node 310 between three voltage levels: V.sub.in, V.sub.in/2, and ground. The symmetric three-level buck converter 300 produces a ripple that is one-quarter the ripple produced by a two-level buck converter. This reduction in ripple is due to reducing the voltage swing at the switch node 310.

[0023] Transistor Q.sub.1 is coupled between an input voltage terminal having a voltage V.sub.IN and transistor Q.sub.3. Transistor Q.sub.1 is coupled to transistor Q.sub.3 at node 306, which is at a voltage V.sub.TOP. Transistor Q.sub.2 is coupled between ground and transistor Q.sub.4. Transistor Q.sub.4 is coupled to transistor Q.sub.3 at switching node 310, which is at a voltage V.sub.SW. Transistor Q.sub.2 is coupled between the switching node 210 and ground. Transistor Q.sub.4 is coupled to transistor Q.sub.2 at node 314, which is at a voltage V.sub.BOT. A capacitor C.sub.FLY is coupled between node 306 and node 314. The voltage across capacitor C.sub.FLY is equal to V.sub.TOP minus V.sub.BOT. An output voltage terminal V.sub.OUT has a load impedance Z.sub.L.

[0024] The control terminal of Q.sub.1 is coupled to a controller that provides control signal CNTL1. The control terminal of Q.sub.2 is coupled to the controller and receives control signal CNTL2. The control terminal of Q.sub.3 is coupled to the controller and receives control signal CNTL3. The control terminal of Q.sub.4 is coupled to the controller and receives control signal CNTL4. Signals CNTL1, CNTL2, CNTL3 and CNTL4 turn transistors Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4, respectively, on and off, modulating the transistor on times to maintain a desired regulated output voltage at V.sub.OUT while ensuring that V.sub.IN and ground are never shorted.

[0025] An inductor L.sub.O is coupled between the switching node 310 and output terminal V.sub.OUT. Capacitor C.sub.O is connected in parallel with load impedance Z.sub.L, and is coupled between inductor L.sub.O and ground. Capacitor C.sub.O and inductor L.sub.O provide filtering to the output voltage V.sub.OUT, filtering the ripple present on V.sub.SW. The inductance value of inductor L.sub.O is chosen to be proportional to the magnitude of the ripple on the signal V.sub.SW. A larger ripple voltage on V.sub.SW requires a larger inductor to absorb the ripple.

[0026] Turning on Q.sub.1 and Q.sub.3 with Q.sub.2 and Q.sub.4 turned off makes V.sub.SW approximately equal to V.sub.IN/2 minus the drain-to-source voltage drops across Q.sub.1 and Q.sub.3. Capacitor C.sub.FLY holds the voltage at nodes 306 and 314 at three-quarters V.sub.IN and at one-quarter V.sub.IN, respectively. Turning off Q.sub.1 and Q.sub.3 and turning on Q.sub.2 and Q.sub.4 makes V.sub.SW equal to ground plus the drain-to-source voltage drops across Q.sub.2 and Q.sub.4. Hence, the voltage at switching node 310, V.sub.SW, switches approximately between V.sub.IN/2 and ground. Reducing the voltage swing at V.sub.SW by half reduces the magnitude of the ripple voltage on V.sub.OUT to one-quarter of the ripple magnitude from the two-level buck converter. Further reduction in the ripple voltage on V.sub.OUT can be achieved in cases where the input voltage is three or more times greater than the output voltage.

[0027] FIG. 4 shows a schematic diagram for an asymmetric three-level buck converter 400. The asymmetric three-level buck converter switches the voltage V.sub.SW at the switch node 410 between three voltage levels: V.sub.in, V.sub.in/3, and ground. The asymmetric three-level buck converter 400 produces a ripple voltage on V.sub.SW that is lower than the ripple voltage produced by a two-level buck converter or a symmetric three-level buck converter. This reduction in the ripple is due to reducing the voltage swing at the switch node 410 to a lower voltage than the switch node voltage swing with either the two-level buck converter or the symmetric three-level buck converter. A lower voltage swing at the switch node produces lower ripple on the switching voltage signal V.sub.SW.

[0028] Transistor Q.sub.1 is coupled between an input voltage terminal having a voltage V.sub.IN and a first terminal of a capacitor C.sub.FLY1. Transistor Q.sub.3 is coupled between a second terminal of capacitor C.sub.FLY1 and ground. Transistor Q.sub.4 is coupled between the second terminal of capacitor C.sub.FLY1 and a first terminal of capacitor C.sub.FLY2. Transistor Q.sub.6 is coupled between a second terminal of capacitor C.sub.FLY2 and ground. Q7 is coupled between the second terminal of capacitor C.sub.FLY2 and switching node 410, which is at a voltage V.sub.SW. Transistor Q.sub.5 is coupled between the first terminal of capacitor C.sub.FLY2 and switching node 410. Transistor Q.sub.2 is coupled between the first terminal of capacitor C.sub.FLY1 and switching node 410. An output terminal V.sub.OUT has a load impedance Z.sub.L. Capacitors C.sub.FLY1 and C.sub.FLY2 can be external to the device, or may be integrated into the same package as transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6, and Q.sub.7.

[0029] The control terminal of Q.sub.1 is coupled to a controller providing control signal CNTL1. The control terminal of Q.sub.2 is coupled to the controller and receives control signal CNTL2. The control terminal of Q.sub.3 is coupled to the controller and receives control signal CNTL3. The control terminal of Q.sub.4 is coupled to the controller and receives control signal CNTL4. The control terminal of Q.sub.5 is coupled to a controller providing control signal CNTL5. The control terminal of Q.sub.6 is coupled to the controller and receives control signal CNTL6. The control terminal of Q.sub.7 is coupled to the controller and receives control signal CNTL7. Signals CNTL1, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6 and CNTL7 turn transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6, and Q.sub.7, respectively, on and off, modulating the on times of transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6, and Q.sub.7 to maintain a desired regulated output voltage at V.sub.OUT while ensuring that V.sub.IN and ground are never shorted. Transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6, and Q.sub.7 can be field effect transistors (FETs) or can be bipolar junction transistors (BJTs).

[0030] An inductor L.sub.O is coupled between the switching node 410 and output terminal V.sub.OUT. Capacitor C.sub.O is connected in parallel with load impedance Z.sub.L, and is coupled between inductor L.sub.O and ground. Capacitor C.sub.O and inductor L.sub.O provide filtering to the output voltage V.sub.OUT, filtering ripple present on V.sub.SW. The inductance value of inductor L.sub.O is chosen to be proportional to the magnitude of the ripple on the signal V.sub.SW. A larger ripple voltage on V.sub.SW requires a larger inductor to absorb the ripple.

[0031] Asymmetric three-level buck converter 400 operates in a continuously recurring cycle having four segments. Asymmetric three-level buck converter 400 operates to maintain charge balance on capacitors C.sub.FLY1 and C.sub.FLY2, and produce the desired regulated output voltage at V.sub.OUT. The voltage V.sub.SW at switch node 410 switches between V.sub.IN/3 and ground.

[0032] In the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, transistors Q.sub.1, Q.sub.4 and Q.sub.7 are turned on while transistors Q.sub.2, Q.sub.3, Q.sub.5 and Q.sub.6 are off during the first segment of the cycle. V.sub.IN is connected to V.sub.OUT through capacitors C.sub.FLY1 and C.sub.FLY2 during the first segment of the cycle. The voltage drop across each of capacitors C.sub.FLY1 and C.sub.FLY2 is V.sub.IN/3. Therefore, the voltage V.sub.SW at the switching node 410 is V.sub.IN/3. The voltage at V.sub.C2TOP is 2/3 V.sub.IN and the voltage V.sub.C1TOP is at V.sub.IN. The voltage V.sub.SW is greater than V.sub.OUT, so the inductor current I.sub.L is charging up during the first segment of the cycle. Capacitors C.sub.FLY1 and C.sub.FLY2 are also being charged during the first segment of the cycle.

[0033] During the second segment of the cycle, in the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, transistors Q.sub.6 and Q.sub.7 are turned on while transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 and Q.sub.5 are turned off. The voltage V.sub.SW at switch node 410 is held at approximately ground through transistors Q.sub.7 and Q.sub.6. During the second segment, the inductor current I.sub.L is discharging through the load Z.sub.L and the charges on capacitors C.sub.FLY1 and C.sub.FLY2 remain as they were at the end of the first segment.

[0034] During the third segment of the cycle, in the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, transistors Q.sub.2, Q.sub.3, Q.sub.5 and Q.sub.6 are turned on while transistors Q.sub.1, Q.sub.4 and Q.sub.7 are turned off. The voltage V.sub.SW at the switching node 410 is at V.sub.IN/3. During the third segment, capacitors C.sub.FLY1 and C.sub.FLY2 are discharged to keep the capacitor charge balanced, allowing the voltage V.sub.SW at the switching node 410 to remain at V.sub.IN/3. During the third segment, capacitors C.sub.FLY1 and C.sub.FLY2 are connected in parallel through transistor combinations Q.sub.2-Q.sub.3 and Q.sub.5-Q.sub.6. Capacitors C.sub.FLY1 and C.sub.FLY2 act as a power supply supplying current to the circuit during the third segment. The inductor current I.sub.L charges up and capacitors C.sub.FLY1 and C.sub.FLY2 slowly discharge during the third segment of the cycle.

[0035] The fourth segment of the cycle is similar to the second segment of the cycle. During the fourth segment of the cycle, in the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, transistors Q.sub.6 and Q.sub.7 are turned on while transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 and Q.sub.5 are turned off. The voltage V.sub.SW at switch node 410 is brought back to approximately ground through transistors Q.sub.7 and Q.sub.6. During the fourth segment, the inductor current I.sub.L discharges through the load impedance Z.sub.L and the charges on capacitors C.sub.FLY1 and C.sub.FLY2 remains as they were at the end of the third segment. Following the fourth segment of the cycle, the cycle goes back to the first segment and the cycle continues repeating.

[0036] In the case where the voltage at V.sub.IN is less than three times the voltage at V.sub.OUT, the circuit operation of the first and third segments of the cycle are the same as the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, but the second and fourth segments of the cycle operates differently. When the voltage at V.sub.IN is less than three time the voltage at V.sub.OUT, transistors Q.sub.1, Q.sub.4 and Q.sub.7 are turned on while transistors Q.sub.2, Q.sub.3, Q.sub.5 and Q.sub.6 are turned off. V.sub.IN is connected to V.sub.OUT through capacitors C.sub.FLY1 and C.sub.FLY2 and the voltage drop across each of C.sub.FLY1 and C.sub.FLY2 is V.sub.IN/3. Therefore, the voltage V.sub.SW at the switching node 410 is V.sub.IN/3. The voltage at V.sub.C2TOP is at 2/3 V.sub.IN and V.sub.C1TOp is at V.sub.IN. The voltage V.sub.SW is lower than V.sub.OUT, so the inductor current I.sub.L is negative as inductor L.sub.O charges up during the first segment of the cycle. Capacitors C.sub.FLY1 and C.sub.FLY2 are also being charged during this segment of the cycle.

[0037] During the second segment of the cycle, in the case where the voltage at V.sub.IN is less than three times the voltage at V.sub.OUT, transistors Q.sub.1 and Q.sub.2 are turned on while transistors Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6 and Q.sub.7 are turned off. The voltage V.sub.SW at switch node 410 is held at approximately V.sub.IN through transistors Q.sub.1 and Q.sub.2. During the second segment, the inductor current I.sub.L is charging, and the charges on capacitors C.sub.FLY1 and C.sub.FLY2 remain as they were at the end of the first segment.

[0038] During the third segment of the cycle, in the case where the voltage at V.sub.IN is more than three times the voltage at V.sub.OUT, transistors Q.sub.2, Q.sub.3, Q.sub.5 and Q.sub.6 are turned on while transistors Q.sub.1, Q.sub.4 and Q.sub.7 are turned off. The voltage V.sub.SW at the switching node 410 is at V.sub.IN/3. During the third segment, capacitors C.sub.FLY1 and C.sub.FLY2 are discharged to keep the capacitor charges balanced, allowing the voltage V.sub.SW at the switching node 410 to remain at V.sub.IN/3. Capacitors C.sub.FLY1 and C.sub.FLY2 are connected in parallel through transistors Q.sub.2-Q.sub.3 and Q.sub.5-Q.sub.6. Capacitors C.sub.FLY1 and C.sub.FLY2 act as a power supply to the circuit during the third segment. The inductor L.sub.O discharges because V.sub.OUT is at a higher voltage than the switch node voltage V.sub.SW. The inductor current decreases and capacitors C.sub.FLY1 and C.sub.FLY2 discharge during the third segment. The charge that was stored in capacitors C.sub.FLY1 and C.sub.FLY2 during segment 1 is discharged in segment 3 of the cycle.

[0039] The fourth segment of the cycle is similar to the second segment. During the fourth segment of the cycle, in the case where the voltage at V.sub.IN is less than three times the voltage at V.sub.OUT, transistors Q.sub.1 and Q.sub.2 are turned on while transistors Q.sub.3, Q.sub.4, Q.sub.5, Q.sub.6 and Q.sub.7 are turned off. The voltage V.sub.SW at switch node 410 is held at approximately V.sub.IN through transistors Q.sub.1 and Q.sub.2. During the fourth segment, the inductor current I.sub.L is charged, and the charges on capacitors C.sub.FLY1 and C.sub.FLY2 remain as they were at the end of the third segment. Following the fourth segment of the cycle, the cycle goes back to the first segment and the cycle continues repeating.

[0040] Asymmetric three-level buck converter 400 is optimized for use in high input voltage, low output voltage applications. However, the design is still useful for other power converter applications, albeit possibly with reduced benefits.

[0041] Additional ripple reduction may be obtained by adding additional switching voltage levels, but with compromised performance in other parameters. For example, the asymmetric three-level buck converter provides approximately the same ripple reduction as a four-level buck converter. However, the asymmetric three-level buck converter 400 has only two transistors in series between V.sub.IN and V.sub.OUT, while the four-level buck converter has three transistors in series which current must pass through between V.sub.IN and V.sub.OUT. Therefore, the asymmetric three-level buck converter has less DC resistance than the four-level buck converter due to having fewer drain-to-source resistances in series with the filter inductance. The higher series resistance of the four-level converter means the four-level converter has a higher power loss, and thus a lower power efficiency, than the asymmetric three-level buck converter.

[0042] A benefit of the asymmetric three-level converter over a two-level converter, or even a symmetric three-level converter, is that a smaller inductor is needed to achieve the same ripple reduction because the voltage swing levels at the switching node are smaller with the asymmetric three-level converter. Therefore, the ripple that is generated by the switching is smaller with the asymmetric three-level converter. The filter inductor L.sub.O is sized proportional to the ripple, so a smaller inductor is needed with the asymmetric three-level converter. If the inductance is reduced, the DC resistance of the inductor is reduced, thereby decreasing the power loss in the inductor.

[0043] As used herein, “terminal”, “node”, “interconnection”, “lead” and “pin” are used interchangeably. Unless specifically stated to the contrary, these terms generally mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device, or other electronics or semiconductor component.

[0044] In this description, “ground” includes a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description.

[0045] In this description, even if operations are described in a particular order, some operations may be optional, and the operations are not necessarily required to be performed in that particular order to achieve desirable results. In some examples, multitasking and parallel processing may be advantageous. Moreover, a separation of various system components in the embodiments described above does not necessarily require such separation in all embodiments.

[0046] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.