MULTIPLE-ROW DISPLAY DRIVING TO MITIGATE TOUCH SENSOR SUBSYSTEM INTERACTION

Abstract

Systems and methods for programming an electronic display in a double-row manner are provided. A system may include processing circuitry that generates image data and an electronic display that programs multiple rows of display pixels with different pixel data of the image data at the same time. This may allow double-row interlaced driving to reduce or eliminate image artifacts due to intra-frame pauses.

Claims

1. An electronic display comprising: a column of display pixels; and data lines comprising a first data line coupled to a first set of display pixels of the column of display pixels and a second data line coupled to a second set of display pixels of the column of display pixels to enable two display pixels, one from the first set of display pixels and one from the second set of display pixels, to be programmed at a same time.

2. The electronic display of claim 1, comprising: first and second column drivers configured to drive first image data over the first data line; and third and fourth column drivers configured to drive second image data over the second data line.

3. The electronic display of claim 2, wherein the first and third column drivers are disposed on one end of the column of display pixels and the second and fourth column drivers are disposed on another end of the column of display pixels.

4. The electronic display of claim 1, comprising a display driver configured to program the column of display pixels in a progressive manner two display pixels at a time.

5. The electronic display of claim 1, comprising a display driver configured to program the column of display pixels in an interlaced manner two display pixels at a time.

6. The electronic display of claim 5, wherein the two display pixels are adjacent to one another.

7. The electronic display of claim 6, wherein the display driver is configured to take an intra-frame pause after programming a first half of the column of display pixels.

8. An electronic device comprising: processing circuitry configured to generate image data; and an electronic display configured to program multiple rows of display pixels with different pixel data of the image data at a same time.

9. The electronic device of claim 8, wherein the processing circuitry is configured to generate the image data one half-frame at a time.

10. The electronic device of claim 9, wherein the processing circuitry is configured to generate the image data for rows [odd*2, odd*21] at one time and for rows [even*2, even*21] at another time.

11. The electronic device of claim 8, wherein the electronic display is configured to program two rows of display pixels at the same time.

12. The electronic device of claim 8, wherein the electronic display comprises a frame buffer configured to store half of an image frame of the image data to be displayed on the electronic display.

13. The electronic display of claim 12, wherein the electronic display is configured to: receive a frame of the image data from the processing circuitry; as the pixel data of the frame of the image data is received, program a first half of the display pixels with a first half of the frame of the image data and store a second half of the frame of the image data in the frame buffer; and program a second half of the display pixels with the second half of the frame of the image data from the frame buffer.

14. The electronic device of claim 8, wherein the electronic display is configured to program the multiple rows of the display pixels in a double-row interlaced manner.

15. The electronic device of claim 8, wherein the electronic display is configured to program the multiple rows of the display pixels in a double-row progressive manner.

16. The electronic device of claim 15, wherein the electronic display is configured to perform an intra-frame pause after programming half of the display pixels in the double-row progressive manner.

17. A controller for an electronic display, comprising: a buffer configured to receive image data for an image frame processed by a pipeline, wherein the pipeline is configured to provide the image data to the electronic display, where in the electronic display comprises a plurality of rows of display pixels configured to receive the image data from the buffer; and display driver circuitry configured to: enable each pair of a first set of one or more pairs of rows in a first group of rows to receive respective portions of image data from the buffer during a respective period in a first time duration, wherein each pair of the first set of one or more pairs of rows comprises a respective set of two adjacent rows that are configured to be simultaneously enabled; and enable each pair of a second set of one or more pairs of rows in a second group of rows to receive respective portions of image data from the buffer during a respective period in a second time duration, wherein each pair of the second set of one or more pairs of rows comprises a respective set of two adjacent rows that are configured to be simultaneously enabled.

18. The controller of claim 17, wherein the buffer is configured to store no more than half of the image data for the image frame.

19. The controller of claim 17, wherein the buffer is configured to be selectively disabled.

20. The controller of claim 17, wherein the display driver circuitry is configured to perform an intra-frame pause between the first time duration and the second time duration.

21. The controller of claim 20, wherein the display driver circuitry is configured to perform the intra-frame pause when display pixel programming has occurred in rows at a location at an end of the electronic display or within two rows of an end of the electronic display.

22. The controller of claim 17, wherein each column of display pixels of the electronic display comprises two data lines configured to receive a respective portion of image data from the buffer.

23. The controller of claim 22, wherein the two data lines in each column of display pixels is configured to receive the respective portion of image data from the buffer for respective display pixels on different rows.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings described below.

[0014] FIG. 1 is a schematic block diagram of an electronic device, in accordance with an embodiment;

[0015] FIG. 2 is a front view of a mobile phone representing an example of the electronic device of FIG. 1, in accordance with an embodiment;

[0016] FIG. 3 is a front view of a tablet device representing an example of the electronic device of FIG. 1, in accordance with an embodiment;

[0017] FIG. 4 is a front view of a notebook computer representing an example of the electronic device of FIG. 1, in accordance with an embodiment;

[0018] FIG. 5 are front and side views of a watch representing an example of the electronic device of FIG. 1, in accordance with an embodiment;

[0019] FIG. 6 is a block diagram of an electronic display of the electronic device, in accordance with an embodiment;

[0020] FIG. 7 illustrates example timing diagrams for image frames, in accordance with an embodiment;

[0021] FIG. 8 illustrates example timing diagrams for double data-line driving, in accordance with an embodiment;

[0022] FIG. 9 is a diagram showing an embodiment of a portion of the electronic display with a dual-data-line display panel and double row interlaced driving, in accordance with an embodiment;

[0023] FIG. 10 illustrates a timing diagram showing an embodiment of a portion of the electronic display with a dual-data-line display panel and double row interlaced driving, in accordance with an embodiment;

[0024] FIG. 11 illustrates a schematic view of an embodiment of a display panel with double data-line per column of sub-pixels and top and bottom driving, in accordance with an embodiment;

[0025] FIG. 12 is a block diagram for a system working with interlaced display and progressive display, in accordance with an embodiment;

[0026] FIG. 13 is a plot showing one embodiment of a time latency for the system of FIG. 12, in accordance with an embodiment; and

[0027] FIG. 14 is a plot showing another embodiment of a time latency for the system of FIG. 12, in accordance with an embodiment.

DETAILED DESCRIPTION

[0028] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0029] When introducing elements of various embodiments of the present disclosure, the articles a, an, and the are intended to mean that there are one or more of the elements. The terms including and having are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to some embodiments, embodiments, one embodiment, or an embodiment of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A based on B is intended to mean that A is at least partially based on B. Moreover, the term or is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A or B is intended to mean A, B, or both A and B.

[0030] This disclosure relates to electronic displays that drive multiple rows of pixels of the electronic displays in an interlaced pattern to adjust the locations of the pauses for touch sensing to an end of the display panel. Because the pauses to allow the touch sensor system to operate take place where the last pixels to be driven are at the end of the screen, image artifacts due to pausing row driving somewhere in the middle of the electronic display may be avoided, while also avoiding interference between the display driving and the operation of the touch sensor system.

[0031] With the preceding in mind and to help illustrate, an electronic device 10 including an electronic display 12 is shown in FIG. 1. As is described in more detail below, the electronic device 10 may be any suitable electronic device, such as a computer, a mobile phone, a portable media device, a tablet, a television, a virtual-reality headset, a wearable device such as a watch, a vehicle dashboard, or the like. Thus, it should be noted that FIG. 1 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in an electronic device 10.

[0032] The electronic device 10 includes the electronic display 12, one or more input devices 14, one or more input/output (I/O) ports 16, a processor core complex 18 having one or more processor(s) or processor cores, local memory 20, a main memory storage device 22, a network interface 24, and a power source 26 (e.g., power supply). The various components described in FIG. 1 may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing executable instructions), or a combination of both hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components. For example, the local memory 20 and the main memory storage device 22 may be included in a single component.

[0033] The processor core complex 18 is operably coupled with local memory 20 and the main memory storage device 22. Thus, the processor core complex 18 may execute instructions stored in local memory 20 or the main memory storage device 22 to perform operations, such as generating or transmitting image data to display on the electronic display 12. As such, the processor core complex 18 may include one or more general purpose microprocessors, one or more application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), or any combination thereof.

[0034] In addition to program instructions, the local memory 20 or the main memory storage device 22 may store data to be processed by the processor core complex 18. Thus, the local memory 20 and/or the main memory storage device 22 may include one or more tangible, non-transitory, computer-readable media. For example, the local memory 20 may include random access memory (RAM) and the main memory storage device 22 may include read-only memory (ROM), rewritable non-volatile memory such as flash memory, hard drives, optical discs, or the like.

[0035] The network interface 24 may communicate data with another electronic device or a network. For example, the network interface 24 (e.g., a radio frequency system) may enable the electronic device 10 to communicatively couple to a personal area network (PAN), such as a Bluetooth network, a local area network (LAN), such as an 802.11x Wi-Fi network, or a wide area network (WAN), such as a 4G, Long-Term Evolution (LTE), or 5G cellular network. The power source 26 may provide electrical power to one or more components in the electronic device 10, such as the processor core complex 18 or the electronic display 12. Thus, the power source 26 may include any suitable source of energy, such as a rechargeable lithium polymer (Li-poly) battery or an alternating current (AC) power converter. The I/O ports 16 may enable the electronic device 10 to interface with other electronic devices. For example, when a portable storage device is connected, the I/O port 16 may enable the processor core complex 18 to communicate data with the portable storage device.

[0036] The input devices 14 may enable user interaction with the electronic device 10, for example, by receiving user inputs via a button, a keyboard, a mouse, a trackpad, a touch sensing, or the like. The input device 14 may include touch-sensing components (e.g., touch control circuitry, touch sensing circuitry) in the electronic display 12. The touch sensing components may receive user inputs by detecting occurrence or position of an object touching the surface of the electronic display 12.

[0037] In addition to enabling user inputs, the electronic display 12 may be a display panel with one or more display pixels. For example, the electronic display 12 may include a self-emissive pixel array having an array of one or more of self-emissive pixels. The electronic display 12 may include any suitable circuitry (e.g., display driver circuitry) to drive the self-emissive pixels, including for example row driver and/or column drivers (e.g., display drivers). Each of the self-emissive pixels may include any suitable light emitting element, such as a LED or a micro-LED, one example of which is an OLED. However, any other suitable type of pixel, including non-self-emissive pixels (e.g., liquid crystal as used in liquid crystal displays (LCDs), digital micromirror devices (DMD) used in DMD displays) may also be used. The electronic display 12 may control light emission from the display pixels to present visual representations of information, such as a graphical user interface (GUI) of an operating system, an application interface, a still image, or video content, by displaying frames of image data. To display images, the electronic display 12 may include display pixels implemented on the display panel. The display pixels may represent sub-pixels that each control a luminance value of one color component (e.g., red, green, or blue for an RGB pixel arrangement or red, green, blue, or white for an RGBW arrangement).

[0038] The electronic display 12 may display an image by controlling pulse emission (e.g., light emission) from its display pixels based on pixel or image data associated with corresponding image pixels (e.g., points) in the image. In some embodiments, pixel or image data may be generated by an image source (e.g., image data, digital code), such as the processor core complex 18, a graphics processing unit (GPU), or an image sensor. Additionally, in some embodiments, image data may be received from another electronic device 10, for example, via the network interface 24 and/or an I/O port 16. Similarly, the electronic display 12 may display an image frame of content based on pixel or image data generated by the processor core complex 18, or the electronic display 12 may display frames based on pixel or image data received via the network interface 24, an input device, or an I/O port 16.

[0039] The electronic device 10 may be any suitable electronic device. To help illustrate, an example of the electronic device 10, a handheld device 10A, is shown in FIG. 2. The handheld device 10A may be a portable phone, a media player, a personal data organizer, a handheld game platform, or the like. For illustrative purposes, the handheld device 10A may be a smart phone, such as any IPHONE model available from Apple Inc.

[0040] The handheld device 10A includes an enclosure 30 (e.g., housing). The enclosure 30 may protect interior components from physical damage or shield them from electromagnetic interference, such as by surrounding the electronic display 12. The electronic display 12 may display a graphical user interface (GUI) 32 having an array of icons. When an icon 34 is selected either by an input device 14 or a touch-sensing component of the electronic display 12, an application program may launch.

[0041] The input devices 14 may be accessed through openings in the enclosure 30. The input devices 14 may enable a user to interact with the handheld device 10A. For example, the input devices 14 may enable the user to activate or deactivate the handheld device 10A, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate a voice-recognition feature, provide volume control, or toggle between vibrate and ring modes.

[0042] Another example of a suitable electronic device 10, specifically a tablet device is shown in FIG. 3. The tablet device 10B may be any IPAD model available from Apple Inc. A further example of a suitable electronic device 10, specifically a computer is shown in FIG. 4. For illustrative purposes, the computer 10C may be any MACBOOK or IMAC model available from Apple Inc. Another example of a suitable electronic device 10, specifically a watch 10D, is shown in FIG. 5. For illustrative purposes, the watch 10D may be any APPLE WATCH model available from Apple Inc. As depicted, the tablet device 10B, the computer 10C, and the watch 10D each also includes an electronic display 12, input devices 14, I/O ports 16, and an enclosure 30. The electronic display 12 may display a GUI 32. Here, the GUI 32 shows a visualization of a clock. When the visualization is selected either by the input device 14 or a touch-sensing component of the electronic display 12, an application program may launch, such as to transition the GUI 32 to presenting the icons 34 discussed in FIGS. 2 and 3.

[0043] As shown in FIG. 6, the electronic display 12 may receive image data 48 for display on the electronic display 12. The electronic display 12 includes display driver circuitry that includes scan driver circuitry 50 and data driver circuitry 52 that can program the image data 48 onto display pixels 54. The display pixels 54 may each contain one or more self-emissive elements, such as a light-emitting diodes (LEDs) (e.g., organic light emitting diodes (OLEDs) or micro-LEDs (LEDs)). Different display pixels 54 may emit different colors (e.g., red, green, blue (RGB)). For example, some of the display pixels 54 may emit red light, some may emit green light, and some may emit blue light. Thus, the display pixels 54 may be driven to emit light at different brightness levels to cause a user viewing the electronic display 12 to perceive an image formed from different colors of light. The display pixels 54 may also correspond to hue and/or luminance levels of a color to be emitted and/or to alternative color combinations, such as combinations that use cyan, magenta, and yellow (CMY), or others.

[0044] The scan driver 50 may provide scan signals (e.g., pixel reset, data enable, on-bias stress) on scan lines 56 to control the display pixels 54 by row. For example, the scan driver 50 may cause a row of the display pixels 54 to become enabled to receive a portion of the image data 48 from data lines 58 from the data driver 52. In this way, an image frame of image data 48 may be programmed onto the display pixels 54 row by row. Other examples of the electronic display 12 may program the display pixels 54 in groups other than by row.

[0045] FIG. 7 illustrates a first timing diagram 60 for an image frame 62. The first timing diagram 60 for the image frame 62 includes an active frame 64 and a blanking frame 66. During the active frame 64, image data may be written to pixels of the electronic display 12. The blanking frame 66 may represent a vertical blanking (VBLANK) period during which no data is written to nor displayed by the pixels of the electronic display 12. In some embodiments, the image frame 62 may have a duration of about 8.3 milliseconds (ms), and the vertical blanking may have a duration about 500 microseconds (s).

[0046] A second timing diagram 68 for the image frame 62 includes the active frame 64 and the blanking frame 66. However, the active frame 64 is divided into a first portion and a second portion 72 by an intra-frame pause (IFP) 74. As discussed above, writing image data to the pixels of the electronic display 12 may stop during the intra-frame pause 74. During this time, for example, the electronic display 12 may check for a touch input. In some embodiments, a length (e.g., duration) of the intra-frame pause 74 may be about 500 microseconds (s).

[0047] As mentioned above, the present disclosure relates to adjusting the occurrence locations of the pauses, including the intra-frame pause (IFP) 74 and the vertical blanking (VBLANK) period 66, to be at or near an end of the electronic display 12 to reduce an occurrence of visual artifacts on the electronic display 12 and improve touch detection sensitivity of the electronic display 12.

[0048] FIG. 8 illustrates a timing diagram 80 showing an embodiment of a portion of the electronic display 12 with dual-data-line display panel and double row driving. In FIG. 8, two data lines 58A and 58B are connected to each display pixel 54. For instance, rows 1 and 2 may be enabled, during which period each of the two data lines 58A and 58B may be operated by a respective column driver integrated circuit (CDIC) 82 at a first end of the electronic display 12 or/and a respective column driver integrated circuit (CDIC) 84 at a second end of the electronic display 12; then rows 3 and 4 may be enabled, and so forth (e.g., rows with number n and n+1, n=1,2,3 . . . ). The line-time for each data line 58 may be extended by driving multiple rows (e.g., two rows) of pixels of the electronic display simultaneously and having more than one data lines (e.g., double data-line) per column of sub-pixels. For example, in the embodiment described above, using double data-line may extend the line time for each data line to double the length. There may be a time offset between operations of two adjacent data lines for the image data 48 to be programmed into a respective display pixel 54 on the two enabled rows. For example, when rows #N and #N+1 are enabled, the display pixel 54 on the row #N may receive a portion of the image data 48 from data line 58A from the data driver 52, and the display pixel 54 on the row #N+1 may receive a portion of the image data 48 from data line 58B from the data driver 52. Then when rows #N+2 and #N+3 are enabled, the display pixel 54 on the row #N+2 may receive a portion of the image data 48 from data line 58A from the data driver 52, and the display pixel 54 on the row #N+3 may receive a portion of the image data 48 from data line 58B from the data driver 52. Consequently, in the illustrated embodiment, each data line may effectively have double the length of line time since each column of display pixels 54 can receive image data on two display pixels 54 of different rows via different data lines. It should be noted that, in certain embodiment, more than two data lines may be operated at a time, and/or more than two rows may be driven at a time to extend the line time for each data line. In some examples, there may be three data lines 58 per column of display pixels 54, allowing three display pixels 54 to be driven at the same time. In other examples, there may be four data lines 58 per column of display pixels 54, allowing four display pixels 54 to be driven at the same time.

[0049] FIG. 9 illustrates a diagram 90 showing an embodiment of a portion of the electronic display 12 with dual-data-line display panel and double row interlaced driving. In the diagram 90, two data lines 58A and 58B are connected to each display pixel 54, and double row interlaced driving is used. For example, during the first portion 70 of the active frame 64, rows 1 and 2 may be enabled, during which period each of the two data lines 58A and 58B may be operated as described above in FIG. 8; then rows 5 and 6 may be enabled, and so forth (e.g., rows with number 2h and 2h1, his an odd number, h=1,3,5 . . . ), until half of the rows of pixels have been driven. The last two rows to have been driven in the first portion 70 may be at or near an end 92 of the electronic display 12. At this point, pixel driving may pause to allow the touch sensor system to perform touch sensing at the halfway, i.e., the intra-frame pause (IFP) 74. After the intra-frame pause (IFP) 74, the second portion 72 of the active frame 64 starts, and other rows of pixels may be driven multiple rows at a time until the blanking frame 66 occurs, e.g., rows 3 and 4 may be enabled and then rows 7 and 8, etc. (e.g., rows with number 2m and 2m1, m is an even number, m=2,4,6 . . . ). In some embodiments, the image frame 62 may have a duration of about 8.3 milliseconds (ms), the intra-frame pause (IFP) 74 may have a duration about 0.5 milliseconds (ms), the vertical blanking (VBLANK) 66 may have a duration about 0.5 milliseconds (ms), and the active frame 64 may have a duration about 7.3 milliseconds (ms). The line-time for each data line may be extended by driving multiple rows (e.g., two rows) of pixels of the electronic display and having more than one data lines (e.g., double data-line) per column of sub-pixels. For example, in the embodiment described above, using a double data-line arrangement may extend the line time for each data line to double the length of the display without extending the time involved in refreshing the display. There may be a time offset between operations of the two data lines of the double data-line sub-pixel for the image data 48 to be programmed into the corresponding display pixel 54, as described in FIG. 8. It should be noted that, in certain embodiments, more than two data lines may be operated at a time, and/or more than two rows may be driven at a time in an interlaced pattern to extend the line time for each data line.

[0050] FIG. 10 illustrates a timing diagram 100 showing an embodiment of a portion of the electronic display 12 with dual-data-line display panel and double row interlaced driving. In FIG. 10, two data lines 58A and 58B are connected to each display pixel 54. For instance, during the first portion 70 of the active frame 64, rows 1 and 2 may be enabled, during which period each of the two data lines 58A and 58B may be operated as described above in FIG. 8; then rows 5 and 6 may be enabled, and so forth (e.g., rows with number 2h and 2h1, his an odd number, h=1,3,5 . . . ), until half of the rows of pixels have been driven. The last two rows to have been driven in the first portion 70 may be at or near an end 92 of the electronic display 12. At this point, pixel driving may pause to allow the touch sensor system to perform touch sensing at the halfway, i.e., the intra-frame pause (IFP) 74. After the intra-frame pause (IFP) 74, the second portion 72 of the active frame 64 starts, and other rows of pixels may be driven multiple rows at a time until the blanking frame 66 occurs, e.g., rows 3 and 4 may be enabled and then rows 7 and 8, etc. (e.g., rows with number 2m and 2m1, m is an even number, m=2,4,6 . . . ).

[0051] FIG. 11 illustrates a schematic view of an embodiment of a display panel 110 with double data-line per column of sub-pixels and top and bottom driving for large displays. One or more power sources 26 (with power management integrated circuit, PMIC) may be used at different locations of the display panel 110 to generate gamma reference voltages. The processor core complex 18 (Soc) may control the TCON 112 (timing controller board), which may control the operations of the column driver integrated circuits (CDIC) 82 and 84 for multiple data line (e.g., double data-line) driving and/or multiple data line interlaced driving described above.

[0052] FIG. 12 illustrates a block diagram for a system 120, in which the interlaced display in the present disclosure is configured to work compatibly with the image processing pipeline designed for progressive display (PIPELINE) 122 by using a half-a-frame buffer (F/B) 124. In displays using progressive driving, a few tens of row latency may be used between the portion of image data 48 prepared by the PIPELINE 122 and the portion of image data 48 under scanning on the electronic display 12. However, for interlaced driving, rows are not driven successively, accordingly, more latency time needed to use the interlaced driving with the PIPELINE 122. For example, during the first portion of the active frame 64, only half of rows (e.g., odd rows) prepared by the PIPELINE 122 may be usable for the interlaced display since the other half of the rows (e.g., even rows) may be used in the second portion 72 of the active frame 64. The half-a-frame buffer 124 may store half of a frame of image data 48 processed by the PIPELINE 122 to be used for interlaced driving so that the time latency is sufficient for the interlaced driving. As illustrated in FIG. 12, the half-a-frame buffer 124 is selected when interlaced display is used for the display 12, and the half-a-frame buffer 124 may be bypassed or disabled (e.g., turned off or disconnected) when progressive display is used for the display 12. Accordingly, the system 120 may be used for both interlaced display and progressive display.

[0053] FIG. 13 illustrates a plot 130 showing one embodiment of a time latency for the system 120 when interlaced display (single row interlaced driving is illustrated in FIG. 13) is used with the PIPELINE 122. In the illustrated embodiment, an image frame 132 displaying on the display 12 has a duration of 8.3 milliseconds (ms) with 3000 rows by way of example (i.e., row #0001 to row #3000). There may be more or fewer rows in other embodiments. A curve 134 shows the rows of the image data 48 of the image frame 132 prepared by the PIPELINE 122 with respect to time with a starting time at tp1. The half-a-frame buffer 124 may store at least half of the 3000 rows of the image data 48 of the frame 132 prepared by the PIPELINE 122, which may provide at least 4.15 ms latency for the interlaced display. Accordingly, the half-a-frame buffer 124 stores sufficient rows of image data 48 of the frame 132 prepared by the PIPELINE 122 for the interlaced display.

[0054] In FIG. 13, a curve 136 shows the scanning of the odd rows of the image data 48 of the image frame 132, and a curve 138 shows the scanning of the even rows of the image data 48 of the image frame 132 (IFP and VBLANK not illustrated in the curves 136 and 138 in FIG. 13). In FIG. 13, the odd rows of the image frame 132 are driven first, then the even rows of the image frame 132 are driven. In FIG. 13, when the scanning of the odd rows (i.e., curve 136) starts at t0, which has a time latency of at least 4.15 ms with respect to the starting time tp1 of the curve 134 (i.e., t0tp1>4.15 ms), the PIPELINE 122 may have at least half of the 3000 rows of the image frame 132 prepared. During the scanning of the odd rows, the PIPELINE 122 continues preparing the rest rows of the image data 48 of the image frame 132, and for a row 140 with row number N (N is an odd number in the illustrated example), the PIPELINE 122 prepares the row 140 at a time t1, which is before a scanning time t2 of the row 140 on the curve 136. In the illustrated embodiment, the PIPELINE 122 is configured to finish preparing the rest rows of the image data 48 of the image frame 132 during the scanning of the odd rows, i.e., curve 136, and the PIPELINE 122 is configured to have a row prepared before the moment it needs to be scanned on the curve 136. For example, when the curve 136 is scanning row #2997, the PIPELINE 122 may be preparing row #2999, and when the curve 136 is scanning row #2999, the PIPELINE 122 may be preparing row #3000. Consequently, when the curve 136 finishes scanning at time t3, the PIPELINE 122 has all the 3000 rows of the image frame 132 prepared, and the curve 138 may use the even rows of the prepared 3000 rows of the image frame 132 for interlaced scanning starting at time t3. It should be noted that, although single row interlaced driving is illustrated in FIG. 13, the system 120 may be used for multiple rows driving (e.g., two rows driving).

[0055] FIG. 14 illustrates a timing plot 150 showing another embodiment of a time latency for the system 120 when interlaced display is used with the PIPELINE 122. In FIG. 14, when it is used in the interlaced display, the PIPELINE 122 (in both Soc 18 and Tcon 112) may run two times faster than its operating speed in the progressive display.

[0056] In, FIG. 14, a curve 152 shows the rows of the image data 48 of the image frame 132 prepared by the PIPELINE 122 with respect to time with a starting time at tp2. A time latency 154 is used for the interlaced display. A curve 156 shows the scanning of the odd rows of the image data 48 of the image frame 132, and a curve 158 shows the scanning of the even rows of the image data 48 of the image frame 132 (IFP and VBLANK not illustrated in the curves 156 and 158 in FIG. 14, and single row driving is used in FIG. 14). In FIG. 14, the odd rows of the image frame 132 are driven first, then the even rows of the image frame 132 are driven. In FIG. 14, when the scanning of the odd rows (i.e., curve 156) starts at t5, the PIPELINE 122 may have several rows of the image frame 132 prepared within the latency time 154. During the scanning of the odd rows, the PIPELINE 122 continues preparing the rest rows of the image data 48 of the image frame 132, and for the row 140 with row number N (N is an odd number in the illustrated example), the PIPELINE 122 prepares the row 140 at time t6, which is before the scanning time t7 of the row 140 on the curve 156. In the illustrated embodiment, the PIPELINE 122 is configured to run two times faster than its operating speed in the progressive display and finish preparing the rest rows of the image data 48 of the image frame 132 during the scanning of the odd rows, i.e., curve 156. The PIPELINE 122 is configured to have a row prepared before the moment it needs to be scanned on the curve 156. For example, when the curve 156 is scanning row #2997, the PIPELINE 122 may be preparing row #2999, and when the curve 136 is scanning row #2999, the PIPELINE 122 may be preparing row #3000. Consequently, when the curve 156 finishes scanning at time t8, the PIPELINE 122 has all the 3000 rows of the image frame 132 prepared, and the curve 158 may use the even rows of the prepared 3000 rows of the image frame 132 for interlaced scanning starting at t8.

[0057] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0058] The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as means for [perform]ing [a function] . . . or step for [perform]ing [a function] . . . , it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).

[0059] It is well understood that the use of personally identifiable information should follow privacy policies and practices that are generally recognized as meeting or exceeding industry or governmental requirements for maintaining the privacy of users. In particular, personally identifiable information data should be managed and handled so as to minimize risks of unintentional or unauthorized access or use, and the nature of authorized use should be clearly indicated to users.