Load Switch Apparatus and Control Method

Abstract

An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

Claims

1. An apparatus comprising: a transistor coupled to a load through an output terminal of a load switch integrated circuit (IC); and a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

2. The apparatus of claim 1, wherein: the transistor is a n-type metal-oxide-semiconductor field-effect transistor (MOSFET); and the gate drive circuit comprises an auxiliary switch and a driver, and wherein: a drain of the auxiliary switch is connected to the gate of the transistor; a source of the auxiliary switch is connected to ground; and an output of the driver is connected to a gate of the auxiliary switch, and wherein a bias voltage of the driver is reduced in a controllable manner such that a turn-off process of the transistor is adjustable through configuring a turn-on impedance of the auxiliary switch.

3. The apparatus of claim 1, wherein: the gate drive circuit comprises a first diode-connected n-type transistor, a second diode-connected n-type transistor, a first switch and a first current source, and wherein: the first diode-connected n-type transistor, the second diode-connected n-type transistor and the first switch are connected in series between the gate of the transistor and the output terminal of the load switch IC; and the first current source is connected between the gate of the transistor and ground.

4. The apparatus of claim 3, wherein: during the short circuit event, the first switch is configured to be turned on to clamp a gate-to-source voltage of the transistor at a predetermined voltage; and after the gate-to-source voltage of the transistor has been clamped at the predetermined voltage, the first current source is configured to discharge the gate of the transistor in a controllable manner from the predetermined voltage to zero.

5. The apparatus of claim 1, wherein: the gate drive circuit comprises a first diode-connected p-type transistor, a second diode-connected p-type transistor, a second switch and a second current source, and wherein: the second switch, the first diode-connected p-type transistor and the second diode-connected p-type transistor and are connected in series between the gate of the transistor and the output terminal of the load switch IC; and the second current source is connected between the gate of the transistor and ground.

6. The apparatus of claim 5, wherein: during the short circuit event, the second switch is configured to be turned on to clamp a gate-to-source voltage of the transistor at a predetermined voltage; and after the gate-to-source voltage of the transistor has been clamped at the predetermined voltage, the second current source is configured to discharge the gate of the transistor in a controllable manner from the predetermined voltage to zero.

7. The apparatus of claim 1, wherein: the gate drive circuit comprises a first diode, a second diode, a third switch and a third current source, and wherein: the third switch, the first diode and the second diode are connected in series between the gate of the transistor and the output terminal of the load switch IC; and the third current source is connected between the gate of the transistor and ground.

8. The apparatus of claim 7, wherein: during the short circuit event, the third switch is configured to be turned on to clamp a gate-to-source voltage of the transistor at a predetermined voltage; and after the gate-to-source voltage of the transistor has been clamped at the predetermined voltage, the third current source is configured to discharge the gate of the transistor in a controllable manner from the predetermined voltage to zero.

9. The apparatus of claim 1, wherein: the gate drive circuit comprises a diode-connected auxiliary transistor, a resistor and a fourth switch, and wherein: the resistor, the diode-connected auxiliary transistor and the fourth switch are connected in series between the gate of the transistor and ground.

10. The apparatus of claim 9, wherein: during the short circuit event, the fourth switch is configured to be turned on; and the diode-connected auxiliary transistor and the resistor are configured to discharge the gate of the transistor in a controllable manner to zero.

11. A method comprising: configuring a transistor as a load switch, wherein a first drain/source terminal of the transistor is coupled to a power source through an input terminal of a load switch IC, and a second drain/source terminal of the transistor is coupled to a load through an output terminal of the load switch IC; and during a short circuit event, gradually reducing a gate voltage of the transistor so as to minimize a negative voltage occurring at the output terminal of the load switch IC.

12. The method of claim 11, further comprising: turning off the transistor in a controllable manner through varying a turn-on impedance of an auxiliary switch coupled between a gate of the transistor and ground, wherein the auxiliary switch is driven by a driver, and wherein: a drain of the auxiliary switch is connected to the gate of the transistor; a source of the auxiliary switch is connected to ground; and an output of the driver is connected to a gate of the auxiliary switch, and wherein a bias voltage of the driver is reduced in a controllable manner to turn off the transistor.

13. The method of claim 11, further comprising: during the short circuit event, clamping the gate voltage of the transistor at a predetermined voltage; and after the gate voltage of the transistor has been clamped at the predetermined voltage, discharging the gate voltage of the transistor to zero in a controllable manner using a current source.

14. The method of claim 13, wherein: the predetermined voltage is equal to two times a threshold voltage of the transistor.

15. The method of claim 13, wherein: the predetermined voltage is equal to two times a voltage drop across a diode.

16. The method of claim 15, wherein: a first diode-connected transistor, a second diode-connected transistor and a switch are used to generate the predetermined voltage, and wherein: the first diode-connected transistor, the second diode-connected transistor and the switch are connected in series between a gate of the transistor and the output terminal of the load switch IC.

17. A method comprising: providing a gate drive circuit to control a gate of a load switch coupled between a power source and a load; during a short circuit event, clamping a gate voltage of the load switch at a voltage level approximately equal to two times a voltage drop across a diode; and after the gate voltage of the load switch has been clamped, discharging the gate voltage of the load switch to zero in a controllable manner using a current source.

18. The method of claim 17, wherein the gate drive circuit comprises a first diode-connected transistor, a second diode-connected transistor, a switch and the current source, and wherein: the switch, the first diode-connected transistor and the second diode-connected transistor and are connected in series between the gate of the load switch and a source of the load switch; and the current source is connected between the gate of the load switch and ground.

19. The method of claim 18, wherein: during the short circuit event, the switch is turned on, and the first diode-connected transistor and the second diode-connected transistor provide a clamping voltage applied to the gate of the load switch to limit a current flowing through the load switch.

20. The method of claim 19, wherein: the current source is configured to discharge the gate voltage of the load switch from the clamping voltage to zero in the controllable manner such that a negative voltage occurring at the source of the load switch is minimized.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0020] FIG. 1 illustrates a schematic diagram of a system including a load switch IC;

[0021] FIG. 2 illustrates various waveforms associated with the load switch IC shown in FIG. 1;

[0022] FIG. 3 illustrates a block diagram of a system including a load switch IC in accordance with various embodiments of the present disclosure;

[0023] FIG. 4 illustrates a schematic diagram of a first implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0024] FIG. 5 illustrates a schematic diagram of a second implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0025] FIG. 6 illustrates a schematic diagram of a third implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0026] FIG. 7 illustrates a schematic diagram of a fourth implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0027] FIG. 8 illustrates a schematic diagram of a fifth implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure;

[0028] FIG. 9 illustrates various waveforms associated with the load switch and the gate drive circuit shown in FIG. 3 in accordance with various embodiments of the present disclosure; and

[0029] FIG. 10 illustrates a flow chart of a method for controlling the load switch shown in FIG. 3 in accordance with various embodiments of the present disclosure.

[0030] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0031] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

[0032] The present disclosure will be described with respect to preferred embodiments in a specific context, namely a gate drive circuit and control method for a load switch IC. The invention may also be applied, however, to a variety of integrated circuits. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

[0033] FIG. 3 illustrates a block diagram of a system including a load switch IC in accordance with various embodiments of the present disclosure. The load switch IC is coupled between a power source 301 and a load 303. The input terminal of the load switch IC is coupled to the power source 301. The output terminal is coupled to the load 303. In order to have a steady input voltage, an input capacitor is coupled between the input terminal of the load switch IC and ground. Likewise, in order to have a steady output voltage, an output capacitor is coupled between the output terminal of the load switch IC and ground.

[0034] In some embodiments, the load switch IC comprises a transistor configured as a load switch. In some embodiments, the transistor is an n-type MOSFET. The drain of the n-type MOSFET is coupled to the input terminal of the load switch IC. The source of the n-type MOSFET is coupled to the output terminal of the load switch IC. The gate of the n-type MOSFET is controlled by a gate drive circuit.

[0035] The gate drive circuit is configured to turn off the load switch in response to an abnormal event occurring inside and outside the load switch IC. In particular, the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the load switch is gradually reduced. As a result of reducing the voltage on the gate gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized. The detailed structure and operating principle of the gate drive circuit will be described below with respect to FIGS. 3-8.

[0036] In some embodiments, the load switch may be implemented as any other suitable semiconductor devices such as bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, insulated gate bipolar transistor (IGBT) devices, gallium nitride (GaN) based power devices and/or the like.

[0037] FIG. 4 illustrates a schematic diagram of a first implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure. The load switch IC comprises a transistor M0. Transistor M0 is an n-type MOSFET. As shown in FIG. 4, M0 is coupled between an input terminal V.sub.IN and an output terminal V.sub.OUT.

[0038] The gate drive circuit comprises an auxiliary switch M1 and a driver DI1. As shown in FIG. 4, a drain of the auxiliary switch M1 is connected to the gate of the transistor M0. A source of the auxiliary switch is connected to ground. The output of the driver DI1 is connected to a gate of the auxiliary switch M1.

[0039] In a short circuit event, the control signal OCPB is configured to turn on the auxiliary switch M1 through the driver DI1. The turned on M1 is able to turn off M0 to protect the load switch IC during the short circuit event. In the process of turning on M1, a bias voltage VDD of the driver is adjusted so as to change the turn-on impedance of the auxiliary switch M1. The turn-on impedance of the auxiliary switch M1 is adjusted such that the turn-off process of M0 has several different turn-off speeds in response to different turn-off stages of M0. The different turn-off speeds help to control the current downward slope of I.sub.LOAD. A slow downward slope of I.sub.LOAD helps to minimize the negative voltage occurring at the output terminal of the load switch IC.

[0040] FIG. 5 illustrates a schematic diagram of a second implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure. The load switch IC comprises a transistor MH1. Transistor MH1 is an n-type MOSFET. As shown in FIG. 5, MH1 is coupled between an input terminal V.sub.IN and an output terminal V.sub.OUT.

[0041] The gate drive circuit comprises a first diode-connected n-type transistor MN1, a second diode-connected n-type transistor MN2, a first switch S1 and a first current source I1. The first diode-connected n-type transistor MN1, the second diode-connected n-type transistor MN2 and the first switch S1 are connected in series between the gate of the transistor MH1 and the output terminal of the load switch IC. The first current source is connected between the gate of the transistor MH1 and ground.

[0042] During the short circuit event, the first switch S1 is configured to be turned on to clamp a gate-to-source voltage of the transistor MH1 at a predetermined voltage. After the gate-to-source voltage of the transistor MH1 has been clamped at the predetermined voltage, the first current source I1 is configured to discharge the gate of the transistor MH1 in a controllable manner from the predetermined voltage to zero. In some embodiments, the predetermined voltage is equal to two times a voltage drop across a diode. In alternative embodiments, the predetermined voltage is equal to two times a threshold voltage of the transistor.

[0043] In the short circuit event, a voltage on the gate of the transistor MH1 is gradually reduced. As a result of reducing the voltage on the gate gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

[0044] FIG. 6 illustrates a schematic diagram of a third implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure. The structure and operating principle of the gate drive circuit shown in FIG. 6 is similar to that shown in FIG. 5 except that the diode-connected transistors MP1 and MP2 are p-type transistors, and hence are not discussed herein again to avoid repetition.

[0045] FIG. 7 illustrates a schematic diagram of a fourth implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure. The structure of the gate drive circuit shown in FIG. 7 is similar to that shown in FIG. 5 except that the diode-connected transistors are replaced by didoes D1 and D2. The operating principle of the gate drive circuit is similar to that of the gate drive circuit discussed above with respect to FIG. 5, and hence is not discussed herein again to avoid repetition.

[0046] FIG. 8 illustrates a schematic diagram of a fifth implementation of the load switch IC shown in FIG. 3 in accordance with various embodiments of the present disclosure. The load switch IC comprises a transistor M0. Transistor M0 is an n-type MOSFET. As shown in FIG. 8, M0 is coupled between an input terminal V.sub.IN and an output terminal V.sub.OUT.

[0047] The gate drive circuit comprises a diode-connected auxiliary transistor M1, a resistor RO and a fourth switch S4. The resistor, the diode-connected auxiliary transistor M1 and the fourth switch S4 are connected in series between the gate of the transistor M0 and ground.

[0048] During the short circuit event, the fourth switch S4 is configured to be turned on. The diode-connected auxiliary transistor M1 and the resistor RO are configured to discharge the gate of the transistor M0 in a controllable manner to zero.

[0049] In the short circuit event, the voltage on the gate of the transistor M0 is gradually reduced to zero. As a result of reducing the voltage on the gate gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.

[0050] In FIGS. 5-8, in response to a short circuit, the operation of the gate drive circuit can be divided into two stages. In a first stage, the switches S1 (FIG. 5), S2 (FIG. 6), S3 (FIG. 7) and S4 (FIG. 8) are turned on. The gate-to-source voltage of the transistor inside the load switch IC is clamped to a predetermined voltage. In some embodiments, the predetermined voltage is equal to two times a threshold voltage of the transistor. In alternative embodiments, the predetermined voltage is equal to two times a voltage drop across a diode. After the gate-to-source voltage of the transistor has been clamped to the predetermined voltage, the current flowing through the transistor is limited by the clamped gate-to-source voltage of the transistor. In a second stage, after the gate-to-source voltage of the transistor has been clamped to the predetermined voltage, a small current source (e.g., I1 shown in FIG. 5) is employed to discharge the gate voltage gradually to zero. The transistor of the load switch IC is fully turned off accordingly.

[0051] In the first stage described above, the gate-to-source voltage of the transistor is quickly clamped to the predetermined voltage so as to limit the current flowing through the load switch IC under the short circuit. In the second stage described above, the gate-to-source voltage of the transistor is gradually reduced from the predetermined voltage to zero. Such a gradually reduced gate-to-source voltage helps to achieve a slow downward slope of the current flowing through the parasitic inductor, thereby minimizing the negative voltage on the output terminal of the load switch IC.

[0052] FIG. 9 illustrates various waveforms associated with the load switch and the gate drive circuit shown in FIG. 3 in accordance with various embodiments of the present disclosure. The horizontal axis of FIG. 9 represents intervals of time. There are six rows. The first row represents the voltage (V.sub.LOAD) across the two terminals of the load RL. The second row represents the voltage (V.sub.OUT) at the output terminal of the load switch IC. The third row represents the current (I.sub.OUT) flowing through the transistor of the load switch IC. The fourth row represents the current (I.sub.COUT) flowing through the output capacitor of the load switch IC. The fifth row represents the current (I.sub.LOUT) flowing through the parasitic inductor coupled between the output terminal of the load switch IC and the load RL. The sixth row represents the current (I.sub.BD) flowing through the ESD diode of the load switch IC.

[0053] In operation, when a short circuit occurs at t1, the voltage (V.sub.LOAD) across the two terminals of the load RL drops quickly to zero as shown in FIG. 9. In response to this short circuit, the current (I.sub.OUT) flowing through the transistor of the load switch IC and the current (I.sub.LOAD) flowing through the parasitic inductor increases in a linear manner from t1 to t2. During the same time period, the gate drive circuit is configured to gradually reduce a gate voltage of the transistor of the load switch IC. In particular, the gate voltage of the transistor is clamped to a voltage level approximately equal to a predetermined voltage (e.g., two times a voltage drop across a diode).

[0054] As shown in FIG. 9, from t2 to t3, the current (I.sub.OUT) flowing through the transistor of the load switch IC is clamped to a predetermined current value (ICLMP). After the current (I.sub.OUT) flowing through the transistor of the load switch IC has been clamped to ICLMP, the current (I.sub.COUT) flowing through the output capacitor starts to increase to meet the current demand of the load (I.sub.LOAD).

[0055] After t2, the gate voltage of the transistor of the load switch IC is gradually discharged to zero. The current (I.sub.COUT) flowing through the output capacitor discharges the energy stored in the output capacitor. At the same time, the current (I.sub.OUT) flowing through the transistor of the load switch IC stays at ICLMP from t2 to t3 and starts to decrease from t3. The reduced I.sub.OUT indicates less energy is provided for the output capacitor. In other words, the output capacitor cannot be replenished. As shown in FIG. 9, the voltage (V.sub.OUT) at the output terminal of the load switch decreases from t2.

[0056] At t4, both the current (I.sub.LOAD) flowing through the parasitic inductor and the current (I.sub.COUT) flowing through the output capacitor reach their respective peak values.

[0057] After t4, the voltage (V.sub.OUT) at the output terminal of the load switch keeps decreasing and starts to have a negative value as shown in FIG. 9. After t4, both the current (I.sub.LOAD) flowing through the parasitic inductor and the current (I.sub.COUT) flowing through the output capacitor start to decrease as shown in FIG. 9. At t5, the voltage (V.sub.OUT) at the output terminal of the load switch IC reaches its negative peak value. The current (I.sub.COUT) flowing through the output capacitor is approximately equal to zero.

[0058] As shown in FIG. 9, prior to t5, the current (I.sub.BD) flowing through the ESD diode starts to increase and falls back to zero at t5. After t5, the current (I.sub.COUT) flowing through the output capacitor has a negative value as shown in FIG. 9. After a resonant process between the parasitic inductor and the output capacitor, the current (I.sub.COUT) flowing through the output capacitor falls back to zero. Likewise, during the resonant process, the voltage (V.sub.OUT) at the output terminal of the load switch IC changes from its negative peak back to zero.

[0059] In comparison with FIG. 2, the current (I.sub.OUT) flowing through the transistor of the load switch has a slow downward slope. As shown in FIG. 9, at t4, when the current (I.sub.LOAD) flowing through the parasitic inductor reaches its peak value, the majority of I.sub.LOAD is provided by I.sub.OUT. As such, the downward slope of I.sub.LOAD is determined by the downward slope of I.sub.OUT. Since I.sub.OUT has a slow downward slope, the voltage difference across the parasitic inductor is reduced accordingly. After the voltage difference across the parasitic inductor has been reduced, the current (I.sub.BD) flowing through the ESD diode is reduced too. In addition, the negative voltage on the output terminal of the load switch IC is minimized.

[0060] FIG. 10 illustrates a flow chart of a method for controlling the load switch shown in FIG. 3 in accordance with various embodiments of the present disclosure. This flowchart shown in FIG. 10 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in FIG. 10 may be added, removed, replaced, rearranged and repeated.

[0061] A load switch IC comprises a transistor coupled between a power source and a load. The transistor is an n-type MOSFET. The load switch IC further comprises a gate drive circuit configured to control the operation of the transistor.

[0062] At step 1002, the transistor is configured as a load switch. A first drain/source terminal of the transistor is coupled to the power source through an input terminal of the load switch IC. A second drain/source terminal of the transistor is coupled to the load through an output terminal of the load switch IC.

[0063] At step 1004, during a short circuit event, the gate drive circuit is configured to gradually reduce the gate voltage of the transistor so as to minimize a negative voltage occurring at the output terminal of the load switch IC.

[0064] Although embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

[0065] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.