SYSTEM FOR THERAPEUTIC TREATMENTS WITH ELECTROMAGNETIC WAVES
20230226367 · 2023-07-20
Inventors
Cpc classification
G16H20/30
PHYSICS
A61N2005/0626
HUMAN NECESSITIES
A61N1/40
HUMAN NECESSITIES
International classification
Abstract
A system for therapeutic treatments with electromagnetic waves is described. The system comprises an antenna and an apparatus configured to generate a supply current for the antenna in order to generate the electromagnetic waves. The apparatus comprises a digital processing circuit configured to generate a first PWM signal, a switching stage configured to generate an amplified PWM signal, an analog low-pass or band-pass filter configured to generate the supply current by filtering the amplified PWM signal, and a current sensor configured to provide a digital sample indicative of the amplitude of the supply current.
Specifically, the digital processing circuit generates a sequence of first digital values of a periodic base pulse. Moreover, the digital processing circuit generates a second PWM signal having a packet switch-on period and a packet switch-off period, generates a third PWM signal having a train switch-on period and a train switch-off period, and generates an enable signal as a function of the second PWM signal and the third PWM signal. The digital processing circuit generates then a second digital value, wherein the second digital value is set to the first digital value when the enable signal has a first logic level and to zero when the enable signal has a second logic level.
In particular, the digital processing circuit generates the first PWM signal as a function of a third digital value indicative of the duty cycle of the first PWM signal, and varies the third digital value via a discrete proportional-integral regulation configured to regulate the difference between the second digital value and the digital sample to zero.
Claims
1. A system for therapeutic treatments with electromagnetic waves, comprising an antenna and an apparatus configured to generate a supply current for said antenna in order to generate said electromagnetic wave, wherein said apparatus comprises: a digital processing circuit configured to generate a first PWM signal having a given duty cycle, wherein said first PWM signal is set, for each switching cycle, to high for a switch-on period and to low for a switch-off period; a switching stage configured to generate an amplified PWM signal by amplifying said first PWM signal; an analog low-pass or band-pass filter configured to generate said supply current by filtering said amplified PWM signal; a current sensor configured to provide a digital sample indicative of the amplitude of said supply current; wherein said digital processing circuit is configured to: generate a sequence of first digital values of a periodic base pulse having a given frequency; generate a second PWM signal, wherein said second PWM signal is set, for each switching cycle, to a respective first logic level for a packet switch-on period and to a respective second logic level for a packet switch-off period; generate a third PWM signal, wherein said third PWM signal is set, for each switching cycle, to a respective first logic level for a train switch-on period and to a respective second logic level for a train switch-off period; generate an enable signal, wherein said enable signal is set to a respective first logic level when said second PWM signal has the respective first logic level and said third PWM signal has the respective first logic level, and to a respective second logic level when said second PWM signal has the respective second logic level or said third PWM signal has the respective second logic level; generate a second digital value, wherein the second digital value is set to the first digital value when said enable signal has the respective first logic level and to zero when said enable signal has the respective second logic level; generate said first PWM signal as a function of a third digital value indicative of said given duty cycle; vary said third digital value via a discrete proportional integral regulation configured to regulate the difference between said second digital value and said digital sample to zero.
2. The system for therapeutic treatments according to claim 1, wherein said digital processing circuit is implemented with an FPGA or an ASIC comprising: a digital signal generator configured to generate said sequence of first digital values; a first digital PWM generator circuit configured to generate said first PWM signal as a function of said third digital value indicative of said given duty cycle; a second digital PWM generator circuit configured to generate said second PWM signal; a third digital PWM generator circuit configured to generate said third PWM signal; a first logic gate configured to generate said enable signal as a function of said second PWM signal and said third PWM signal; a second logic circuit configured to generate said second digital value as a function of said first digital value and said enable signal; a discrete proportional integral regulator circuit configured to vary said third digital value as a function of said second digital value and said digital sample.
3. The system for therapeutic treatments according to claim 2, wherein said digital signal generator is configured to generate periodic base pulses having a saw-tooth profile, and wherein said digital signal generator comprises a counter configured to: in response to a clock signal having a given frequency, increase said first digital values by an increment value; and reset said first digital values when said first digital values reaches a given maximum value.
4. The system for therapeutic treatments according to claim 3, wherein said digital signal generator comprises an increment control circuit configured to generate said increment value as a function of: data identifying said frequency or said clock signal; data identifying said frequency of said periodic base pulses; said maximum value.
5. The system for therapeutic treatments according to claim 2, wherein said digital signal generator comprises: a look-up table comprising a plurality of elements corresponding to a given number of samples of a standard waveform of said base pulses with a given standard frequency, wherein each element has stored the amplitude of a respective sample of said standard waveform of said base pulses, wherein said look-up table receives at input a count value selecting a given sample, and wherein said first digital value is determined as a function of the amplitude of the respective selected sample; a counter configured to, in response to a clock signal, increase said count value by an increment value, whereby said counter represents a phase accumulator; and an increment control circuit configured to generate said increment value as a function of data identifying said standard frequency and data identifying said frequency of said periodic base pulses.
6. The system for therapeutic treatments according to claim 4, wherein said increment control circuit is configured to calculate an internal increment value, said internal increment value having an integer part having a number of bits corresponding to the number of bits of said increment value, and a fractional part, and wherein said increment control circuit is configured to vary said increment value, such that said increment value has an average value corresponding to said internal increment value.
7. The system for therapeutic treatments according to claim 1, wherein said digital processing circuit comprises a third digital PWM generator circuit configured to generate a polarity signal, and wherein said switching stage comprises: a first half-bride comprising a first and a second electronic switch, wherein the intermediate node between said first and said second electronic switch is a first switching node; a second half-bride comprising a third and a fourth electronic switch, wherein the intermediate node between said third and said fourth electronic switch is a second switching node, wherein said amplified PWM signal corresponds to the voltage between said first switching node and said second switching node; a driver circuit configured to generate drive signals for said first, second, third and fourth electronic switch as a function of said first PWM signal and said polarity signal.
8. The system for therapeutic treatments according to claim 1, wherein said digital processing circuit comprises: a first communication interface for exchanging data with a further digital processing unit; and a control circuit configured to receive via said first communication interface data identifying a treatment program to be executed and, as a function of said data identifying a treatment program to be executed determine: said frequency of said periodic base pulse, said packet switch-on period and said packet switch-off period, and said train switch-on period and said train switch-off period.
9. The system for therapeutic treatments according to claim 8, wherein said digital processing circuit and said further digital processing unit are configured to execute at least one of the following treatment programs: program 1: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 206.80 ms (corresponding to the time of 44 base pulses), the pause between the packets is T.sub.pac_off=140.00 ms, the time T.sub.tr_on is set to 1387.20 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1450 ms; program 2: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 146.88 ms (corresponding to the time of 34 base pulses), the pause between the packets is T.sub.pac_off=105.00 ms, the time T.sub.tr_on is set to 1007.52 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1100 ms; program 3: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 94.00 ms (corresponding to the time of 20 base pulses), the pause between the packets is T.sub.pac_off=55.00 ms, the time T.sub.tr_on is set to 596.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=600 ms; program 4: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 77.76 ms (corresponding to the time of 18 base pulses), the pause between the packets is T.sub.pac_off=37.00 ms, the time T.sub.tr_on is set to 459.04 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=480 ms; program 5: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 75.20 ms (corresponding to the time of 16 base pulses), the pause between the packets is reduced to T.sub.pac_off=21 ms, the time T.sub.tr_on is set to 384.80 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=370 ms; program 6: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 60.48 ms (corresponding to the time of 14 base pulses), the pause between the packets is T.sub.pac_off=16.00 ms, the time T.sub.tr_on is set to 305.92 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=350 ms; program 7: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 56.40 ms (corresponding to the time of 12 base pulses), the pause between the packets is T.sub.pac_off=6.60 ms, the time T.sub.tr_on is set to 252.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=220 ms; program 8: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 43.20 ms (corresponding to the time of 10 base pulses), the pause between the packets is T.sub.pac_off=2.44 ms, the time T.sub.tr_on is set to 183.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=176 ms; and program 9: saw-tooth base pulse with frequency f.sub.imp=189.75 Hz, where the duration of the base pulse is T.sub.imp=5.27 ms, the time T.sub.pac_on is set to 26.35 ms (corresponding to the time of 5 base pulses), the pause between the packets is set to T.sub.pac_off=16.85 ms, the time T.sub.tr_on is set to 1728.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1600 ms.
10. The system for therapeutic treatments according to claim 8, wherein said data identifying a treatment program to be executed comprise a program number or the respective timing data.
11. The system for therapeutic treatments according to claim 8, wherein said further digital processing unit is configured to: receive data identifying a treatment application; determine a sequence of a plurality of treatment programs as a function of said data identifying a treatment application; starting execution of a first treatment program of said sequence of treatment programs by sending data identifying said first treatment program to said digital processing unit; waiting that a given treatment program duration has elapsed; and selecting the next treatment program of said sequence of treatment programs and starting execution of said next treatment program of said sequence of treatment programs by sending data identifying said next treatment program to said digital processing unit.
12. The system for therapeutic treatments according to claim 11, wherein said further digital processing unit is configured to receive said data identifying a treatment application via at least one of: a user interface, and a communication interface configured to exchange data with a processing system.
13. The system for therapeutic treatments according to claim 8, wherein said digital processing unit is an FPGA programmable via respective program data stored to a first non-volatile memory and/or said further digital processing unit is a microprocessor programmable via a respective firmware stored to a second non-volatile memory, and wherein said further digital processing unit is configured to receive at least one or: new program data for said digital processing unit and store said new program data to said first non-volatile memory; and a new firmware for said further digital processing unit and store said new firmware to said second non-volatile memory.
14. The system for therapeutic treatments according to claim 1, wherein said digital processing circuit comprises a pulse generator configured to generate a pulsed signal configured to be applied to an acoustic, light and/or vibration transducers, wherein said pulse generator is configured to set said pulsed signal to high when said second digital value is greater than a threshold, and to low when said second digital value is equal to or smaller than said threshold, whereby said pulsed signal has a square waveform synchronized with said supply current according to said given frequency of said periodic base pulse, the switching cycle of said second PWM signal and the switching cycle of said third PWM signal.
15. The system for therapeutic treatments according to claim 1, wherein said apparatus is configured to support a total and/or a local operating mode, wherein: in said total operating mode, a first antenna is connected to said apparatus, said first antenna being a planar antenna having a length between 120 cm and 250 cm, preferably between 150 cm and 200 cm, and a width between 40 cm and 120 cm, preferably between 60 cm and 90 cm; and in said local operating mode, a second antenna is connected to the apparatus, said second antenna being a planar antenna having a length between 20 cm and 120 cm, preferably, between 20 cm and 60 cm, and a width between 20 cm and 60 cm, or an anatomically modeled antenna.
16. The system for therapeutic treatments according to claim 9, wherein said sequence of a plurality of treatment comprises at least one of: e.g. for treating multiple sclerosis, a total treatment application consisting in a sequence of treatment programs 1, 3 and 6 and/or a local treatment application consisting in a sequence of treatment programs 3 and 6; e.g. for treating Parkinson's disease, a total treatment application consisting in a sequence of treatment programs 3, 6 and 3 and/or a first local treatment consisting in a sequence of treatment programs 3 and 6 and/or a second local treatment application consisting in a sequence of treatment programs 8 and 8; e.g. for treating Alzheimer's disease or senile dementia, a total treatment application consisting in a sequence of treatment programs 3, 6 and 9 and/or a local treatment application consisting in a sequence of treatment programs 3 and 6; e.g. for treating postictal states, a total treatment application consisting in a sequence of treatment programs 3, 3 and 6 and/or a local treatment application consisting in a sequence of treatment programs 6 and 6; e.g. for treating fibromyalgia or chronic fatigue syndrome, a total treatment application consisting in a sequence of treatment programs 3, 6 and 9 and/or a local treatment application consisting in a sequence of treatment programs 6 and 8; and e.g. for treating the Psycho-Neuro-Endocrine-Immunology (P.N.E.I) system, a total treatment application consisting in a sequence of treatment programs 9, 6 and 9 and/or a local treatment application consisting in a sequence of treatment programs 3 and 6.
Description
BRIEF DESCRIPTION OF THE ANNEXED DRAWINGS
[0051] The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:
[0052] The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which:
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DETAILED DESCRIPTION OF EMBODIMENTS
[0068] In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.
[0069] Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
[0070] The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.
[0071] In
[0072] As explained in the foregoing, various embodiments of the present description relate to a system for therapeutic treatments with electromagnetic waves. As described in the foregoing, when using programs 1 or 3 of the apparatus of document WO 2012/172504 A1 for the treatment of the central and/or peripheral nervous system, e.g. for treating chronic neuroinflammation and/or neurodegenerative diseases such as Alzheimer's disease, multiple sclerosis or Parkinson's disease, only minor improvements could be shown.
[0073] Generally, the inventor has observed that this problem could have various reasons, such as incorrect frequencies of the programs, or that a single program is insufficient for the treatment of a particular decease. In this respect, the inventor of the present application has observed, that the combination of programs 1, 3 and 6 seems to be most suitable for the treatment of the central and/or peripheral nervous system, e.g. for the treatment of the above mentioned diseases, insofar as an improvement of the result of the treatment could be observed. However, a rather surprising improvement could be observed when slightly adapting the embodiment shown in FIG. 5 of document WO 2012/172504 A1, and which is reproduced herein as
[0074] Specifically, according to document WO 2012/172504 A1, the signal S comprises a plurality of base pulses I grouped in pulse packets P and in pulse trains Tr, wherein each pulse packet P consists of a series of base pulses I followed by a first pause T.sub.pac_off, and wherein each pulse train Tr consists of a series of pulse packets P followed by a second pause T.sub.tr_off. For example, each base pulse I may have a saw-tooth, square-wave, or sinusoidal waveform; or each base pulse I may comprise a series of curved profiles in such a way that in a pulse time interval T.sub.imp_on the waveform is increasing and comprises a plurality of cusps 2 and 4.
[0075] In the embodiment considered, the control circuit 22 comprises a waveform generator 226 configured to generate different waveforms (see for example
[0076] As described in the foregoing, document WO 2012/172504 A1 generates a signal having trains Tr of identical packets P, each comprising a given number n.sub.imp of base pulses I. This is also shown in
[0077] Accordingly, by using a waveform generator 226, such a sequence of trains Tr of packets P may e obtained by: [0078] activating the waveform generator 226 at the beginning of a packet P and deactivating the waveform generator 226 at the end of the interval T.sub.pac_on, or, e.g. in case a PWM modulation of the base pulse I is performed, activating the waveform generator 226 at the beginning of each interval T.sub.imp and deactivating the waveform generator 226 at the end of the interval T.sub.imp_on; or [0079] by using switch-off durations T.sub.pac_off and T.sub.tr_off, which are multiples of the time T.sub.imp of the base pulse I, whereby the start of a packet intrinsically corresponds to the start of a base pulse I.
[0080] Generally, the second option may be rather unfeasible, because the switch-off durations T.sub.pac_off and T.sub.tr_off are not necessarily multiples of the time T.sub.imp. Accordingly, in the embodiment of document WO 2012/172504 A1, the control circuit 22 uses the first option, wherein the processing unit 220 is configured to activate and deactivate the signal provided by the waveform generator 226 according to the data identifying durations T.sub.pac_on, T.sub.pac_off, T.sub.tr_on and T.sub.tr_off, and possibly also of the durations T.sub.imp_on and T.sub.imp_off (as stored to the memory 222). However, the inventor has observed that the result of the treatment improves significantly for the low frequency programs 1 to 4 when the waveform generator 226 is not activated at the beginning of each packet P, or even each interval T.sub.imp, but the waveform generator 226 is maintained running and provides at output continuous base pulses I, with a given frequency f.sub.imp/a given period T.sub.imp. As mentioned before, while the frequency f.sub.imp/period T.sub.imp is usually constant for a given treatment program 1 to 9, the frequency f.sub.imp/period T.sub.imp may still be settable, e.g. for the frequencies 213 Hz and 231 Hz mentioned before.
[0081] As mentioned before, for the specific programs 1 to 9 mentioned before, the period T.sub.pac of a packet P does not correspond to a multiple of the period T.sub.imp of the base pulse I. Accordingly, as also shown in
[0082] As mentioned before, such a broadening of the spectrum would be undesirable according to document WO 2012/172504 A1, which provides an arrangement configured to generate clearly defined series of frequencies only within certain ranges, while avoiding a wider frequency ranges, which according to document WO 2012/172504 A1 would provide only a low probability of inducing the effect of therapeutic resonance. In this respect, document EP 3160582 A1 already mentioned that the dynamic variation of the harmonics could be useful, e.g. in order to prevent the phenomenon of cell adaptation, with reduction of the sensitivity to the stimulation induced and of the consequent responses. Accordingly, the inventor performed further experiments, in particular: [0083] varying the frequency f.sub.imp of the base pulse, and the switch-off durations T.sub.pac_off and T.sub.tr_off of the packets in the apparatus of document WO 2012/172504 A1 according to a random dithering operation; and [0084] varying the frequencies of the sinusoidal signals of the apparatus of document EP 3160582 A1 according to a random dithering operation.
[0085] However, surprisingly the above described shifting operation by activating/deactivating a continuously running base pulse I obtained the best results. A possible explanation may reside in the fact that a dithering operation results in a random and rather chaotic variation of the frequencies of the electromagnetic wave. Conversely, the shift operation maintains the frequency of the trains, but additional and variable low power harmonics of the truncated first and last packet P, and similarly the first and last base pulses are added. Moreover, the shifting operation is not casual, but essentially results in a repetitive and cyclic pattern, which seems to be useful for the resonance effects.
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[0087] Generally, the filter stage 28 may also be external with respect to the apparatus 20a and, e.g., incorporated in the antenna/diffuser 30. Generally, the filter stage 28 may also comprise the capacitance and inductance of the antenna 30. Accordingly, the terminals 202a and 202b may be connected to the output of the filter stage 28 (when the filter stage 28 is incorporated in the apparatus 20a) or to the output of the power stage 24a (when the filter stage 28 is external with respect to the apparatus 20a).
[0088] Accordingly, the apparatus 20a may also comprise a power supply 26a configured to receive an input voltage Vin and generate the supply voltage Vdd (and possible further supply voltages) for the control circuit 22a and the supply voltage Vcc for the power stage 24a. Generally, the power supply 26a may be any AC/DC or DC/DC power supply adapted to generate a plurality of supply voltages (e.g. from the mains and/or a battery integrated in the apparatus 20a). For example, in various embodiments, the power supply 26a may comprise an electronic converter, such as a flyback, forward or half-bridge converter, comprising a transformer with a plurality of secondary windings, each secondary winding providing a respective supply voltage. Alternatively may be used a cascade of voltage regulators, wherein a first voltage regulator generates the supply voltage Vcc from the input voltage Vin and a second voltage regulator generates the voltage Vdd from the voltage Vcc. Generally, as mentioned before the power supply 26a may be also at least in part external with respect to the apparatus 20a. For example, an external AC/DC electronic converter may generate a DC voltage Vin from the mains, and one or more internal DC/DC voltage regulators may generate the voltages Vcc and Vdd. Generally, the mentioned DC/DC voltage regulators may be e.g. switched mode electronic converters (e.g. in order to reduce power losses) or linear regulators (e.g. in order to reduce the electromagnetic interference).
[0089] In various embodiments, the apparatus 20a may also comprise a user interface 50, e.g. for receiving an input from a user and/or for providing status information to the user. For example, the user interface 50 may be used to select a treatment program corresponding to one of the programs 1 to 9 (or a subset thereof) or a treatment application corresponding to a predetermined sequence of programs 1 to 9, e.g. programs 1, 3 and 6. Conversely, the status information shown to the user may include one or more of the following information: whether a treatment program is running, which treatment program has been selected. the time remaining of the treatment program, and/or diagnostic information, e.g. indicating that no antenna 30 has been connected to the terminals 202a and 202b. Accordingly, the user interface 50 may include buttons, a keyboard, luminous indicators (such as LEDs), a display, a touch screen, etc.
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[0091] The first digital processing circuit 220a is connected to a non-volatile memory 222a. For example, the non-volatile 222a may correspond to the program memory of the microprocessor 220a, such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a FLASH memory, i.e. the memory having stored the firmware/software executed by the microprocessor 220a. Specifically, in various embodiments, the non volatile memory 222a is used to store the timing data of the signal S to be generated, such as data identifying the frequency f.sub.imp of the base pulse I, optionally the type of the base pulse if different waveforms are supported, such as saw-tooth and profile with cusps, data identifying the durations T.sub.pac_on and T.sub.pac_off of a package P, and data identifying the durations T.sub.tr_on and T.sub.tr_off of a train Tr. As mentioned before, in various embodiments, the duration T.sub.pac_on corresponds to a multiple of the period T.sub.imp=1/f.sub.imp and the duration T.sub.tr o.sub.n corresponds to a multiple of the period T.sub.pac=T.sub.pac_on+T.sub.pac_off.
[0092] In various embodiments, the control circuit 224 may also comprise a communication interface 224a for connection to an external processing system 10, such as a PC, a tablet, a smartphone or a remote server, e.g. a web-server. For example, the communication interface 224a may comprise at least one of: [0093] a reader device for a portable memory support; [0094] a communication interface for a wired communication with the processing system 10, such as a serial communication interface, e.g. a RS-232 or USB (Universal Serial Bus) communication interface, or an Ethernet network adapter; [0095] a short-range wireless communication interface, such as a NFC (Near Field Communication) or Bluetooth® communication interface; [0096] a Wi-Fi communication interface according to the IEEE 802.11 standard; and [0097] a mobile communication interface, such as a GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System) modem, HSPA (High-Speed Packet Access), or LTE (Long Term Evolution) modem.
[0098] Accordingly, the communication with the processing system 10 may be indirectly via a portable memory support, directly via a wired or wireless communication, via a LAN (Local-Area Network) or even via a WAN (Wide-Area Network), such as Internet. Generally, the communication interface and/or the memory 222a may also be integrated in a microcontroller comprising the microprocessor 220a. In the embodiment considered, the communication interface 224a may be used to communicate with the processing circuit 220a, e.g. in order to control the operation of the apparatus 20a. For example, the processing circuit 220a may be configured to implement one or more of the above functions described with respect to the user interface 50 by exchanging commands and/or status information with the processing system 10. For example, in this way, a smartphone or tablet may be used to control and/or monitor the operation of the apparatus 20a, e.g. via a Bluetooth® or Wi-Fi communication. In various embodiments, the processing circuit 220a may also be configured to receive new timing data of the signal S from the processing system 10 and store these data to the memory 222a. Similarly, in various embodiments, the communication interface 224a and the processing system 220a may also be configured to receive a new firmware for the processing unit 220a from the processing system 10 and store the new firmware to the memory 222a.
[0099] In various embodiments, the control circuit 22a comprises also a second digital processing circuit 220b, preferably a digital hardware circuit, such as an ASIC (Application-specific integrated circuit) or an FPGA (Field Programmable Gated Array). Accordingly, the control circuit 22a may also comprise a second non-volatile memory 222b having stored the firmware/program data for the second digital processing circuit 220b. In various embodiments, the communication interface 224a and the processing system 220a may thus also be configured to receive a new firmware for the processing circuit 220b from the processing system 10 and store the new firmware to the memory 222b.
[0100] Generally, the operation of the various circuits of the processing circuit 220b may also be implemented via software modules implementing the same function. For example, in this way, the operation of the processing circuit 220a and 220b may also be implemented in a single processing circuit, such as a DSP (Digital Signal Processor). However, as will be described in the following, several parallel processing operations are implemented within the processing circuit 220b, which would require a rather fast microprocessor in order to implement the same operations via software instructions. The inventor has observed that, also taking into account a typical production volume of the apparatus 20a, the most cost efficient solution is a microprocessor 220a configured to manage the user interface and the optional communication interface 224a, and a FPGA 220b for managing the generation of the signal S.
[0101] Specifically, in the embodiment considered, the second digital processing circuit 220b essentially implements a custom programmable signal generator, wherein the operation of the second digital processing circuit 220b is controlled by the first processing circuit 220a.
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[0103] For example, in various embodiments, a slight modification of program 5 has been performed: [0104] new program 5: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 75.20 ms (corresponding to the time of 16 base pulses), the pause between the packets is reduced to T.sub.pac_off=21 ms, the time T.sub.tr_on is set to 384.80 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=370 ms;
[0105] Conversely, program 9 of document WO 2012/172504 A1 uses a base pulse with cusps and provides the broadest frequency spectrum with the highest number of harmonics. Generating such a profile with cusps may be rather complex with a digital circuit. Accordingly, in various embodiments, a similar broad frequency spectrum has been obtained by using the following timing data for a modified program 9: [0106] new program 9: saw-tooth base pulse with frequency f.sub.imp=189.75 Hz, where the duration of the base pulse is T.sub.imp=5.27 ms, the time T.sub.pac_on is set to 26.35 ms (corresponding to the time of 5 base pulses), the pause between the packets is set to T.sub.pac_off=16.85 ms, the time T.sub.tr_on is set to 1728.00 ms (corresponding to the time of 40 packets) and the pause between the trains is T.sub.tr_off=1600 ms.
[0107] Thus, in various embodiments, the other programs 1-4 and 6-8 may have the following characteristics: [0108] program 1: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 206.80 ms (corresponding to the time of 44 base pulses), the pause between the packets is T.sub.pac_off=140.00 ms, the time T.sub.tr_on is set to 1387.20 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1.sup.450 ms; [0109] program 2: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 146.88 ms (corresponding to the time of 34 base pulses), the pause between the packets is T.sub.pac_off=105.00 ms, the time T.sub.tr_on is set to 1007.52 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1100 ms; [0110] program 3: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 94.00 ms (corresponding to the time of 20 base pulses), the pause between the packets is T.sub.pac_off=55.00 ms, the time T.sub.tr_on is set to 596.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=600 ms; [0111] program 4: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 77.76 ms (corresponding to the time of 18 base pulses), the pause between the packets is T.sub.pac_off=37.00 ms, the time T.sub.tr_on is set to 459.04 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=480 ms; [0112] program 6: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 60.48 ms (corresponding to the time of 14 base pulses), the pause between the packets is T.sub.pac_off=16.00 ms, the time T.sub.tr_on is set to 305.92 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=350 ms; [0113] program 7: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 56.40 ms (corresponding to the time of 12 base pulses), the pause between the packets is T.sub.pac_off=6.60 ms, the time T.sub.tr_on is set to 252.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=220 ms; [0114] program 8: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 43.20 ms (corresponding to the time of 10 base pulses), the pause between the packets is T.sub.pac_off=2.44 ms, the time T.sub.tr_on is set to 183.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=176 ms.
[0115] For example, the timing in [ms] of the above programs may be summarized according to the following table:
TABLE-US-00002 # T.sub.imp n.sub.imp T.sub.pac_on T.sub.pac_off T.sub.pac n.sub.pac T.sub.tr_on T.sub.tr_off T.sub.tr 1 4.70 44 206.80 140.00 346.80 4 1387.20 1450 2837.20 2 4.32 34 146.88 105.00 251.88 4 1007.52 1100 2107.52 3 4.70 20 94.00 55.00 149.00 4 596.00 600 1196.00 4 4.32 18 77.76 37.00 114.76 4 459.04 480 939.04 5 4.70 16 75.20 21.00 96.20 4 384.80 370 754.80 6 4.32 14 60.48 16.00 76.48 4 305.92 350 655.92 7 4.70 12 56.40 6.60 63.00 4 252.00 220 472.00 8 4.32 10 43.20 2.55 45.75 4 183.00 176 359.00 9 5.27 5 26.35 16.85 43.20 40 1728.00 1600 3328.00
[0116] As described in the foregoing, in various embodiments, a PWM modulation may also be applied to each base pulse. For example, in various embodiments, a PWM modulation with a duty cycle of 50% is used, i.e. T.sub.imp_on=T.sub.imp_off=T.sub.imp/2.
[0117] As mentioned before, the apparatus 20a may support only a single treatment application or support plural treatment applications. For example, in various embodiments, the apparatus 20a is configured to support at least the following treatment applications: [0118] a first treatment application executing only program 1; [0119] a second treatment application executing only program 3; [0120] a third treatment application executing only program 6; [0121] a fourth treatment application executing the sequence of programs 1, 3 and 6, wherein any order may be used, but preferably the order 1, 3 and 6 is used.
[0122] Specifically, in various embodiments, the apparatus 20a is configured to support a total and/or a local operating mode. Specifically, in the total operating mode, a large planar antenna 30 is connected to the apparatus 20a, thereby permitting a global/total stimulation of the body of the target (human). For example, in this case, the antenna 30 may be a planar pad or mat having a length between 120 cm and 250 cm, preferably between 150 cm and 200 cm, and a width between 40 cm and 120 cm, preferably between 60 cm and 90 cm. Conversely, in the local operating mode, a smaller antenna 30 is connected to the apparatus 20a, thereby permitting a local stimulation of only a part of the body of the target (human). For example, in this case, the antenna 30 may be a planar pad or mat having a length between 20 cm and 120 cm, preferably, between 20 cm and 60 cm, and a width between 20 cm and 60 cm, or an anatomically modeled antenna, e.g. having a shape being complementary to the area to be treated. Generally, the apparatus 20a may support only a single operating mode (total or local), or both operating modes. In the latter case, the apparatus 20a may comprise (in line with the description of
[0123] For example, in various embodiments, the apparatus 20a is configured to support one or more of the following global and/or local treatment applications: [0124] e.g. for treating osteoarticular and musculoskeletal pathologies, a total and/or a local (trauma area) treatment application executing both the sequence of programs 6 and 8; [0125] e.g. for treating vascular pathologies, a total and/or a local (trauma area) treatment application executing both the sequence of programs 6 and 5; [0126] e.g. for treating ulcers or a ischemic diabetic foot, a total and/or a local (ulcer area or foot) treatment application executing both the sequence of programs 6 and 8; and [0127] e.g. for treating a neuropathic diabetic foot, a total treatment application executing the sequence of programs 3, 6 and 8 and/or a local (foot) treatment application executing the sequence of programs 6 and 8.
[0128] As mentioned before, while also showing improvements for the programs 6 to 8 (and permitting a simplification of the implementation of the program 9), the apparatus 20a has been developed mainly in order to improve the programs 1 to 4. Accordingly, in addition to or as alternative to the above treatment applications, in various embodiments, the apparatus 20a is configured to support one or more of the following global and/or a local treatment applications: [0129] e.g. for treating multiple sclerosis, a total treatment application executing the sequence of programs 1, 3 and 6 and/or a local (head) treatment application executing the sequence of programs 3 and 6; [0130] e.g. for treating Parkinson's disease, a total treatment application executing the sequence of programs 3, 6 and 3 and/or a first local (head) treatment application executing the sequence of programs 3 and 6 and/or a second local (abdomen) treatment application executing the sequence of programs 8 and 8; [0131] e.g. for treating Alzheimer's disease or senile dementia, a total treatment application executing the sequence of programs 3, 6 and 9 and/or a local (head) treatment application executing the sequence of programs 3 and 6; [0132] e.g. for treating postictal states, a total treatment application executing the sequence of programs 3, 3 and 6 and/or a local (head) treatment application executing the sequence of programs 6 and 6; [0133] e.g. for treating fibromyalgia or chronic fatigue syndrome, a total treatment application executing the sequence of programs 3, 6 and 9 and/or a local (pain area) treatment application executing the sequence of programs 6 and 8; and [0134] e.g. for treating the Psycho-Neuro-Endocrine-Immunology (P.N.E.I.) system, a total treatment application executing the sequence of programs 9, 6 and 9 and/or a local (head) treatment application executing the sequence of programs 3 and 6.
[0135] Accordingly, usually a sequence of treatment programs has to be executed, wherein each treatment program may has associated respective timing data. Specifically, after a start step 1000, the first digital processing circuit 220a determines at a step 1002 the treatment program to be executed. As mentioned before, the treatment program may also correspond to the first treatment program of a treatment application. For example, the sequence of treatment program to be executed for a given treatment application may be stored in a Look-Up Table. In various embodiments, the first digital processing circuit 220a sends at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b including data identifying the treatment program to be executed. For example, in various embodiment, the data identifying the treatment program to be executed may comprise timing data of the signal S. Accordingly, in this case, the first digital processing circuit 220a may read the timing data from the memory 222a and send at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b, wherein the one or more control commands CTRL comprise the timing data of the signal S to be generated, such as: [0136] data identifying the frequency f.sub.imp of the base pulse I; [0137] optionally data identifying the duty cycle of the base pulse I; [0138] optionally the type of the base pulse if different waveforms are supported, such as saw-tooth and profile with cusps; [0139] data identifying the durations T.sub.pac_on and T.sub.pac_off of a package P; [0140] data identifying the durations T.sub.tr_on and T.sub.tr_off of a train Tr; [0141] optionally data identifying the inversion period of the signal S.
[0142] Generally, these data may correspond to the data stored to the memory 222a or may be determined as a function of the timing data stored to the memory 222a. Additionally or alternatively, the timing data of one or more treatment programs may also be stored directly in the second digital processing circuit 220b or in the memory 222b and read by the second digital processing circuit 220b. For example, in this way, a first set of standard programs, e.g. programs 1, 3 and 6, may already be pre-configured within the second digital processing circuit 220b, and one or more additional programs may be configured by storing the respective timing data to the memory 222a. Accordingly, in this case, the first digital processing circuit 220a may send at the step 1002 one or more control commands CTRL to the second digital processing circuit 220b, wherein the one or more control commands comprise a program number to be executed. Generally, the program number does not necessarily correspond to the above mentioned treatment program numbers, but e.g. program 1 could correspond to treatment program 1, program 2 could correspond to treatment program 3, program 3 could correspond to treatment program 6.
[0143] At a step 1004, the first digital processing circuit 220a sends a control command CTRL to the second digital processing circuit 220b requesting that the generation of the signal S should be started with the characteristics communicated at the step 1002. Generally, the steps 1002 and 1004 may also be combined, because the data identifying the treatment program to be executed (step 1002) may also be included in the instruction requesting the generation of the signal S. Accordingly, in response to the start instruction, the second digital processing circuit 220b generates the signal S as will be described in greater detail in the following. In various embodiments, once having sent the start command (step 1004), the first digital processing circuit 220a proceeds then to a step 1006. The step 1006, essentially corresponds to a wait step. For example, during the step 1006, the first digital processing circuit 220a may monitor the operation of the second digital processing circuit 220b, e.g. by sending one or more control commands CTRL to the second digital processing circuit 220b requesting status data, or the second digital processing circuit 220b may send autonomously status data to the first digital processing circuit 220a.
[0144] In the embodiment considered, the first digital processing circuit 220a then verifies at a step 1008 whether the treatment time of the current treatment program has elapsed. For example, in various embodiments, the first digital processing circuit 220a monitors the treatment time and determines whether a predetermined treatment time associated with the current treatment program has been reached, such as 480 s. Additionally or alternatively, the second digital processing circuit 220b may monitor the treatment time and determine whether a predetermined treatment time associated with the current treatment program has been reached. In this case, the second digital processing circuit 220b may include in the status information (sent at the step 1006 to the first digital processing circuit 220a) data indicating whether the treatment program is running or whether the treatment time has elapsed. In case the first digital processing circuit 220a determines that the treatment time of the current treatment program has not elapsed (output “N” of the verification step 1008), the first digital processing circuit 220a returns to the step 1006. Conversely, in case the first digital processing circuit 220a determines that the treatment time of the current treatment program has elapsed (output “Y” of the verification step 1008), the first digital processing circuit 220a proceeds to a step 1010.
[0145] Specifically, in various embodiments, the first digital processing circuit 220a verifies at a step 1010 whether the current treatment program was the last treatment program to be executed. As mentioned before, a single treatment program or a sequence of treatment programs may be executed. In case the first digital processing circuit 220a determines that the current treatment program was not the last treatment program to be executed (output “N” of the verification step 1010), the first digital processing circuit 220a returns to the step 1002, where the next treatment program of a sequence of treatment programs is selected and the above procedure is repeated for the next treatment program. Conversely, in case the first digital processing circuit 220a determines that the current treatment program was the last treatment program to be executed (output “Y” of the verification step 1010), e.g. because only a single program has to be executed or because the treatment program was the last of a sequence of treatment programs, the procedure terminates at a stop step 1012. Generally, as described in the foregoing, the digital processing circuit 220a may also provide status data of the execution of the treatment application to the processing system 10.
[0146] Accordingly, in various embodiments, the second digital processing circuit 220b may be configured to support at least one of: [0147] a generic operation mode, in which the second digital processing circuit 220b is configured to generate the signal S as a function of timing data received from the digital processing circuit 220a; and/or [0148] one or more specific operation modes, in which the second digital processing circuit 220b is configured to generate the signal S as a function of timing data determined as a function of a program number received from the digital processing circuit 220a.
[0149] As described in the foregoing (see also
[0150] For example, in
[0151] In the embodiment considered, the power stage 24a comprises thus also a driver circuit 242 configured to generate drive signals DRV1 and DRV2 for the electronic switches SW1 and SW2, respectively, wherein the drive signals DRV1 and DRV2 are generated as a function of the drive signal DRV. Generally, in such an arrangement, only one of the electronic switches of the half bridge is closed. For example, in various embodiments, the logic level of the drive signal DRV1 may correspond to the logic level of the drive signal DRV, and the logic level of the drive signal DRV2 may correspond to the inverted version of the logic level of the drive signal DRV.
[0152] Conversely,
[0155] Such delays may be useful in order to avoid that the switches of a half-bridge are closed contemporaneously. However, such delays TD1 and TD2 are usually small and thus will be neglected in the following.
[0156] Conversely, in
[0161] Accordingly, the arrangement of
[0162] Specifically, in the embodiment considered, the driver circuit 242 is configured to determine rising and falling edges in the polarity signal POL and the drive signal DRV, and: [0163] in response to detecting a first type of edge (e.g. a rising edge) in the polarity signal POL, set the drive signal DRV3 to low (immediately) and the drive signal DRV4 to high (immediately or possibly after a delay), and: [0164] in response to detecting a rising edge in the signal DRV, set the signal DRV1 to high (immediately or possibly after a delay) and set the signal DRV2 to low (immediately), whereby the voltage V.sub.240 between the terminals 240a and 240b corresponds to Vcc, and [0165] in response to detecting a falling edge in the signal DRV, set the signal DRV1 to low (immediately) and set the signal DRV2 to high (immediately or possibly after a delay), whereby the voltage V.sub.240 between the terminals 240a and 240b corresponds to zero; and [0166] in response to detecting a second type of edge (e.g. a falling edge) in the polarity signal POL, set the drive signal DRV3 to high (immediately or possibly after a delay) and the drive signal DRV4 to low (immediately), and: [0167] in response to detecting a rising edge in the signal DRV, set the signal DRV2 to high (immediately or possibly after a delay) and set the signal DRV1 to low (immediately), whereby the voltage V.sub.240 between the terminals 240a and 240b corresponds to −Vcc, and [0168] in response to detecting a falling edge in the signal DRV, set the signal DRV2 to low (immediately) and set the signal DRV1 to high (immediately or possibly after a delay), whereby the voltage V.sub.240 between the terminals 240a and 240b corresponds to zero.
[0169] Accordingly, in various embodiments, the second digital processing circuit 220b is configured to generate the drive signal DRV for the power stage 24a, wherein the drive signal DRV corresponds to a PWM signal, and optionally the polarity signal POL. Generally, the information of the polarity signal POL may also be transmitted via the drive signal DRV, e.g. by switching the drive signal DRV between three levels (“+1”, “0”, “−1”).
[0170] For example,
[0171] Accordingly, the voltage applied to the antenna 30 (approximately) corresponds to the average voltage between the terminals 240a and 240b (e.g., between Vcc and ground, or between Vcc and −Vcc). However, indeed the signal S should correspond to the current i.sub.out provided via the terminals 202a and 202b to the antenna 30. For this reason, in various embodiments, the apparatus 20a comprises a current sensor 228 configured to generate a signal CS indicative of (and preferably proportional to) the current i.sub.out. For example, in various embodiments, the current sensor 228 is connected (e.g. directly) in series with the terminals 202a and 202b. However, the current sensor 228 may also be connected (e.g. directly) in series with the output terminals 240a and 240b of the power stage 24a, because the current provided by the power/switching stage 24a may also be used to estimate the current i.sub.out. For example, the current sensor 228 may be a shunt resistor R.sub.S, e.g. a shunt resistor R.sub.S connected in series with the terminals 202a and 202b, wherein the voltage at the resistor R.sub.S is proportional to the current i.sub.out provided via the terminals 202a and 202b.
[0172] In this case, the second digital processing circuit 220b may be configured to vary the PWM drive signal DRV as a function of the signal CS in order to regulate the requested profile of the current i.sub.out, i.e. of the signal S. Specifically, for this purpose, the control circuit 22a may comprise an analog-to-digital converter (A/D) 228b, such as a sigma-delta converter, which is configured to provide digital samples CS.sub.D of the signal CS.
[0173] Generally, e.g. in case the signal CS is not directly proportional to the current flowing through the antenna 30 (e.g. because the sensor 228 is connected to the output terminals of the power stage 24a), a low-pass filter 228a may be connected between the current sensor 228 and the A/D 228b, i.e. the A/D 228b may receive a low-pass filtered version CS' of the signal CS. Additionally or alternatively, the block 228a may comprise a rectifier circuit, i.e. the A/D 228b may receive a rectified version CS' of the signal CS. For example, this may be useful in case the polarity of the voltage between the terminals 240a and 240b may be inverted (see the description of
[0174] Accordingly, in various embodiments, the second digital processing circuit 220b is configured to obtain digital samples CS.sub.D indicative of (and preferably proportional to) the (e.g. absolute value of the) current flowing through the antenna 30. As mentioned before, the second digital processing circuit 220b may be configured to vary the PWM drive signal DRV as a function of the samples CS.sub.D. However, the samples CS.sub.D may also be used for other purposes. For example, the first or the second digital processing circuit 220a/220b may use the samples in order to determine whether the antenna 30 is disconnected, e.g. because the values CS.sub.D are below a given minimum threshold, or damaged, e.g. because the values CS.sub.D are above a given maximum threshold.
[0175]
[0176] Accordingly, in the embodiment considered, the second digital processing circuit 220b comprises a digital hardware circuit 2240 configured to generate the sequence of values S.sub.D as a function of the timing data of the treatment program to be executed.
[0177] For example, in the embodiment considered, the second digital processing circuit 220b comprises a communication interface 2220 for exchanging data with the first digital processing unit 220a, in particular the previous mentioned control commands CTRL. Specifically, in various embodiments, the control commands CTRL comprise data identifying the treatment program to be executed, such as a program number or the respective timing data. For example, in various embodiments, the communication interface 2220 may be an Universal Asynchronous Receiver/Transmitter (UART), Inter-Integrated Circuit (I.sup.2C) or Serial Peripheral Interface (SPI) communication interface.
[0178] In various embodiments, a circuit 2222 is thus configured to determine the timing data of the treatment program to be executed as a function of the data identifying the treatment program to be executed, e.g. by extracting the timing data from the control command(s) CTRL, or extracting the program number from the control command(s) CTRL and determining the timing data as a function of the program number. Generally, in the latter case, the timing data associated with a given the program number may be fixed or programmable, e.g. by storing respective timing data to the memory 222b.
[0179] In various embodiments, the circuit 2222 is configured to provide the following data to the digital hardware circuit 2240: [0180] data identifying the frequency f.sub.imp of the base pulse I; [0181] optionally data identifying the duty cycle of the base pulse I; [0182] optionally the type P.sub.imp of the base pulse if different waveforms are supported, such as saw-tooth and profile with cusps; [0183] data identifying the durations T.sub.pac_on and T.sub.pac_off of a package P; [0184] data identifying the durations T.sub.tr_on and T.sub.tr_off of a train Tr; [0185] optionally data identifying the inversion period of the signal S.
[0186]
[0187] Specifically, in the embodiment considered, the digital hardware circuit 2240 comprises: [0188] a digital base pulse generator 2224 configured to generate a sequence of (continuous) digital samples S.sub.imp of the base pulse I as a function of the data identifying the frequency f.sub.imp of the base pulse I and optionally the type P.sub.imp of the base pulse; and [0189] an enable circuit 2226 configured to generate an enable signal EN as a function of the data identifying the durations T.sub.pac_on and T.sub.pac_off of a package P and data identifying the durations T.sub.tr_on and T.sub.tr_off of a train Tr.
[0190] For example, the digital samples S.sub.imp may have 8, 16, 24 or 32 bit.
[0191] In various embodiments, the digital hardware circuit 2240 comprises also logic gates 2234, such as a multiplexer or AND gates, configured to generate the values S.sub.D by: [0192] when the enable signal EN has a first logic level (e.g. high), setting the value S.sub.D to the value S.sub.imp; and [0193] when the enable signal EN has a second logic level (e.g. low), setting the value S.sub.D to a predetermined value (e.g. zero) indicating that the output of the power stage 24a should be set to zero volt (see also the description of
[0194] Accordingly, in the embodiment considered, the signal S.sub.D (having usually the same number of bits as the signal S.sub.imp) at the output of the logic gates 2234 corresponds to the signal S described with respect to
[0195] For example, in various embodiments, the enable circuit 2226 comprises: [0196] a first digital PWM generator circuit configured to generate a first PWM signal PWM.sub.P, wherein, during each switching cycle with period T.sub.pac, the signal PWM.sub.P is set to high for the time T.sub.pac_on and low for the time T.sub.pac_off; [0197] a second digital PWM generator circuit configured to generate a second PWM signal PWM.sub.Tr, wherein, during each switching cycle with period T.sub.tr, the signal PWM.sub.Tr is set to high for the time T.sub.tr_on and low for the time T.sub.tr_off; and [0198] a logic gate 2232, such as an AND gate, configured to generate the enable signal EN by combining the signals PWM.sub.P and PWM.sub.Tr.
[0199] For example, this is also shown in
[0200] For example, the PWM signal generator circuits 2228 and 2230 may be implemented with one or more digital counters. For example, a PWM signal generator may be implemented by increasing a count value in response to a clock signal, wherein: [0201] the output of the PWM signal generator circuit is set to high when the count value is between 0 and a first value proportional to the time T.sub.pac_on (or T.sub.tr_on); [0202] the output of the PWM signal generator circuit is set to low when the count value is greater than the first value; and [0203] the count value is reset to 0 when the count value reaches a second value proportional to the time T.sub.pac (or T.sub.tr).
[0204] For example, the inventor has observed that with a clock frequency of 48 Mhz, the PWM signal generators 2228 and 2230 may be implemented with counters having 24 bits.
[0205] The base pulse generator circuit 2224 may have different implementation forms, which essentially depend on the fact whether the frequency f.sub.imp may be variable and whether a single or plural base pulse types are required. For example, in various embodiments, the second digital processing circuit 220b should be able to generate (at least) the programs 1, 3 and 6, i.e.: [0206] program 1: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 206.80 ms (corresponding to the time of 44 base pulses), the pause between the packets is T.sub.pac_off=140.00 ms, the time T.sub.tr_on is set to 1387.20 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=1450 ms; and [0207] program 3: saw-tooth base pulse with frequency f.sub.imp=212.76 Hz, where the duration of the base pulse is T.sub.imp=4.70 ms, the time T.sub.pac_on is set to 94.00 ms (corresponding to the time of 20 base pulses), the pause between the packets is T.sub.pac_off=55.00 ms, the time T.sub.tr_on is set to 596.00 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=600 ms; [0208] program 6: saw-tooth base pulse with frequency f.sub.imp=231.48 Hz, where the duration of the base pulse is T.sub.imp=4.32 ms, the time T.sub.pac_on is set to 60.48 ms (corresponding to the time of 14 base pulses), the pause between the packets is T.sub.pac_off=16.00 ms, the time T.sub.tr_on is set to 305.92 ms (corresponding to the time of 4 packets) and the pause between the trains is T.sub.tr_off=350 ms;
[0209] Accordingly, these three programs use a saw-tooth base pulse, but two different frequencies f.sub.imp may be used. As mentioned before, also the modified program 9 may use a saw-tooth base pulse, but with a further frequency.
[0210]
[0213] Accordingly, a circuit 2262 may determine the number n.sub.CLK required to obtain a requested frequency f.sub.imp. For example, when receiving at input data identifying the requested frequency, the circuit 2262 may calculate n.sub.CLK=f.sub.CLK/f.sub.imp. However, the circuit 2262 may also receive directly the number n.sub.CLK, i.e. the data identifying the frequency f.sub.imp of the base pulse I may correspond to the number n.sub.CLK. Next, the circuit 2262 may calculate the increment value INC as a function of maximum value S.sub.Dmax and the number n.sub.CLK, i.e. INC=S.sub.Dmax/n.sub.CLK.
[0214] Generally, e.g. based on the resolution of the counter 2260, the calculated number n.sub.CLK and/or the increment value INC will not necessarily be an integer number. For example, assuming a clock frequency f.sub.CLK=48 Mhz, and a requested frequency f.sub.imp=212.76, n.sub.CLK would correspond to approximately 225,606.32 clock cycles. Moreover, assuming a counter with 24 bit, wherein the maximum value S.sub.Dmax is set to 16,777,215, the “optimal” increment value INC would be approximately 74.365. For example, when the counter uses the increment value INC=74 indeed 226,720 clock cycles would be required to reach the maximum value S.sub.Dmax, thereby resulting in a frequency of 211.715 Hz, and when the counter uses the increment value INC=75 indeed 223,697 clock cycles would be required to reach the maximum value S.sub.Dmax, thereby resulting in a frequency of 214.576 Hz.
[0215] Accordingly, in various embodiments, the circuit 2262 is configured to vary the increment value INC provided to the counter 2260, preferably for each clock cycle, such that the average value of the increment value INC corresponds the optimal increment value INC (with fraction). For example, for this purpose, the circuit 2262 may manage internally an increment value INC′ having a resolution being greater than the resolution of the increment value INC provided to the counter 2260, wherein the value INC′ is calculated according to the previous method by considering a given number of the most significant bits as integer part, wherein the given number corresponds to the number of bits of the signal INC, and the remaining least significant bits are considered as fraction part, e.g. the 16 least significant bits. Accordingly, the increment value INC may be varied such that the increment value INC corresponds in average to the value INC′.
[0216] In various embodiments, e.g. in order to permit a programmability of the base pulse profile or to support also other base pulse types, the base pulse generator circuit 2224 may also be based on a digital signal generator circuit using Direct Digital Synthesis (DDS).
[0217] Thus, also in this case the optimal increment value INC may not be an integer value. Accordingly, also in this case, the circuit 2258 may manage internally an increment value INC′ having a resolution being greater than the resolution of the increment value INC provided to the counter 2260, wherein the value INC′ is calculated according to the previous method by considering a given number of the most significant bits as integer part, wherein the given number corresponds to the number of bits of the signal INC, and the remaining least significant bits are considered as fraction part, e.g. the 16 least significant bits. Accordingly, the increment value INC may be varied, preferably for each clock cycle, such that the increment value INC corresponds in average to the value INC′. For example, assuming a clock frequency of f.sub.CLK=48 Mhz and standard waveforms being stored for base pulse profiles having f.sub.s=10 Hz, the LUT would comprise 4,800,000 samples. Generally, instead of storing all these samples, the circuit 2224 may operate with a down-scaled version of the clock signal CLK, i.e. the circuit 2224 may operate with a frequency f′.sub.CLK, e.g. corresponding to f.sub.CLK/4, f.sub.CLK/8, f.sub.CLK/16, f.sub.CLK/24 or f.sub.CLK/32, etc. For example, in various embodiments, the frequency f′.sub.CLK is between 100 kHz and 2 MHz. For example, in the following will be assumed that the frequency f′.sub.CLK corresponds to 375,000 Hz (f.sub.CLK/128), i.e. for f.sub.s=10 Hz, the LUT would comprise 37,500 samples. Accordingly, in order to generate a base pulse with f.sub.imp=212.76, the internal increment value INC′ may comprise the bits of the signal INC for the integer part and e.g. 10 bits for the fraction part. Accordingly, the internal increment value INC′ would correspond to 21.276, e.g. binary encoded as “10101.0100011010”, which approximately corresponds to 21.27539. Thus, the circuit 2258 may set the increment value INC either to 21 (“10101”) or 22 (“10110”), such that the average value of the increment value INC corresponds to the value INC′. For example, in the embodiment considered, the fractional part “0.0100011010” corresponds to “0100011010”/“10000000000”=282/1024. Accordingly, the circuit 2258 may be configured to apply 282 times the value 22 and 1024−282=742 times the value 21, which would result in an average increment value of (282×22+742×21)/1024=21.27539.
[0218] The inventor has observed that this averaging operation implemented by the circuits 2258 and 2262 may introduces a further small dithering operation of the harmonics of the base pulse I, which seems to be useful in order to improve the result of the low frequency treatment programs. Thus, in various embodiments, a first dithering operation may be performed directly during the generation of the base pulse values S.sub.imp by the averaging operation of the increment value INC provided to the signal generator 2250 or 2260. A second dithering operation (which indeed is not casual due to the shifting effect) is then performed by enabling and disabling the base pulse values S.sub.imp according to the timing of the packet P and the train Tr.
[0219] As describe in the foregoing, a PWM modulation may also be applied to the base pulse I. For example, in the embodiment shown in
[0220] The inventor has observed that the disclosed digital solution provides surprisingly better treatment results than a complete analog implementation of the block 2240, or a mixed digital/analog solution comprising an analog waveform generator (implementing the operation of the block 2224) and a digital circuit (implementing the operation of the clock 226) configured to selectively connected the output of the analog waveform generator to a power amplifier. Presumably, this results from the fact that the described digital implementation of the circuit 2224 permits to control more precisely the frequency of the base pulses. In fact, the described solutions permit to obtain a precise clock frequency, being not correlated with the frequency of the packets and trains, which ensures that the harmonics do not overlap. Moreover, the additional dithering operation of the averaging operation permits to slightly broaden the harmonics of the base pulses.
[0221] A further possible reason may reside in the additional control of the current flowing through the antenna 30. Specifically, as described in the foregoing, the values S.sub.D represent the requested values of the current i.sub.out to be provided to the antenna 30. Specifically, as shown in
E(k)=S.sub.D(k)−CS.sub.D(k) [0223] calculate, e.g. via an accumulator, an integral value EI(k) indicative of the integral of the error values E(k), e.g.:
EI(k)=EI(k−1)+E(k), with EI(0)=0; [0224] calculate the output D(k) as a function of the proportional component E(k) and the integral component EI(k) by using respective coefficients Kp and Ki, i.e.:
D=Kp×E(k)+Ki×EI(k)
[0225] In the embodiment considered, the value D is provided to a digital PWM generator circuit 2238 configured to generate the drive signal DRV as a function of the signal D. For example, also the PWM signal generator 2238 may be implemented with one or more digital counters. For example, the PWM signal generator 2238 may be implemented by increasing a count value in response to the clock signal CLK, wherein: [0226] the signal DRV at the output of the PWM signal generator 2238 is set to high when the count value is between 0 and a first value proportional to (and preferably corresponding to) the value D; [0227] the output of the PWM signal generator is set to low when the count value is greater than the first value; and [0228] the count value is reset to 0 when the count value reaches a given maximum value.
[0229] For example, in various embodiments, the counter 2238 has the same number of bits as the signal S.sub.D, e.g. 8 bits, which e.g. permits to obtain a PWM signal DRV with a switching frequency of 48 MHz/256=187,500 Hz.
[0230] Thus, in various embodiments, the digital PI regulator 2236, the digital PWM signal generator 2238, the power/switching stage 24a, the filter 28, the current sensor 228 and the A/D 228b (and possibly the filter 228a) implement a regulated current generator, configured to regulate the output current i.sub.out provided via the terminals 202a and 202b to the requested value S.sub.D. For example, the embodiment shown in
[0231] However, the implementation of the digital PI regulator 2236 and the digital PWM signal generator 2238 within the second digital processing circuit 220b has several advantages compared to the use of a separate regulated current generator. For example, the solution is more cost efficient, because instead of using a digital-to analog (D/A) converter for the signal S.sub.D and a separate regulated current generator, only an A/D converter 228b is required and the control operation of the regulated current generator (usually implemented in a dedicated current control IC) may be implemented by digital processing within the second processing circuit 220b. Moreover, due to the implementation within a FPGA or ASIC, a faster regulation of the current i.sub.out is possible, thereby permitting that the current i.sub.out follows precisely the profile of the values S.sub.D. In fact, such control ICs for regulated current generators usually are for constant current applications, such as for powering LEDs, and thus do not provide a sufficient bandwidth in order to follow a constantly varying profile of current pulses. Moreover, also the inversion of the polarity may be implemented easier. In fact, as described in the foregoing, the power/switching stage (while amplifying the PWM signal DRV) may also invert the polarity of the voltage between the terminals 240a and 240b as a function of a polarity signal POL.
[0232] For example, as shown in
[0233] Finally, as shown in
[0237] For example, in this way may be generated one or more further signals, synchronized with the signal applied to the antenna 30. For example, the further signal may be at least one of: [0238] as shown in
[0241] Accordingly, in various embodiments, the further signal(s) use the same signal profile S.sub.D (frequencies of base pulses, packets and trains) generated for the antenna(s) 30 (total and/or local applicators). The further signal(s) are supplied in a synchronous mode, e.g. to drive a headphone, LED glasses and piezoelectric Transducers. Accordingly, these one or more additional stimuli may be perceived by receptors of the patient, thereby stimulating given areas in the brain of the patient associated with the respective receptors, such as acoustic receptors (audio), visual receptors (light), and/or proprioceptive and/or nociceptive receptors (vibration).
[0242] Specifically, e.g. because the transducers are not fast enough or similarly because human eyes would be unable to perceive the variation of saw-tooth base pulses having a frequency around of 200 Hz, in various embodiments, one or more further signals may be generated by filtering the samples S.sub.D. For example, in various embodiments, a binarized version of the samples S.sub.D is used. For example, as described in the foregoing, in various embodiments, the base pulses I uses a PWM modulation, e.g. of 50%. Accordingly, in this case, the digital PWM signal generator 2236b may be configured to generate the PWM signal PWM.sub.A by setting the signal PWM.sub.A to high when the value S.sub.D is greater than a first threshold, e.g. zero, and to low when the value S.sub.D is smaller or equal to the first threshold, e.g. zero. For example, this simplifies also the generation of further signal, because the low-pass filter 28b may be omitted. Moreover, for the above mentioned transducers, the value of the polarity signal POL is not relevant.
[0243] Accordingly, in various embodiments, one or more further signals (such as the audio signal and the signal used to drive one or more LEDs, and optionally the signal used to drive a vibration transducers) have a square waveform, but follow the timing of the base pulses (T.sub.imp, T.sub.imp_on, T.sub.pac, T.sub.tr). For example, test have demonstrated that, while a human brain is typically able to elaborate images with up to 30 fps, indeed a human eye is able to perceive frequencies up to (approximately) 250 Hz.
[0244] Accordingly, various embodiments relate to a system for therapeutic treatments with electromagnetic waves. The system comprises an antenna 30 and an apparatus 20a configured to generate a supply current i.sub.out for the antenna 30 in order to generate the electromagnetic waves. In various embodiments, the apparatus 20a comprises a digital processing circuit 220b.
[0245] According to the first aspect, the digital processing circuit 220b is configured to generate a sequence of values S.sub.D corresponding to the signal S shown in
[0246] Generally, these values S.sub.D could be provided to the antenna via an A/D converter. Conversely, according to a second aspect, the digital processing circuit 220b is configured to generate a PWM signal DRV having a given duty cycle, wherein the PWM signal DRV is set, for each switching cycle T.sub.SW, to high for a switch-on period T.sub.ON and to low for a switch-off period T.sub.OFF. In this case, the apparatus 20a comprises also a switching stage 24a configured to generate an amplified PWM signal V.sub.240 by amplifying the PWM signal DRV and an analog low-pass or band-pass filter 28 configured to generate the supply current i.sub.out by filtering the amplified PWM signal V.sub.240.
[0247] Accordingly, in this case, the digital processing circuit 220b may be configured to generate the PWM signal DRV as a function of the digital value S.sub.D. For example, in various embodiments, the apparatus comprises also a current sensor 228 configured to provide a digital sample CS.sub.D indicative of the amplitude of the supply current i.sub.out. In this case, the digital processing circuit 220b may be configured to generate via the circuit or module 2238 the PWM signal DRV as a function of a digital value D indicative of a duty cycle of the PWM signal DRV. Moreover, the digital processing circuit 220b may be configured to vary the digital value D via a discrete proportional-integral regulation configured to regulate the difference between the digital value S.sub.D and the digital sample CS.sub.D to zero.
[0248] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.