Power supply device and method for controlling power supply device

Abstract

A chopper section of a power supply device includes a plurality of step-down chopper circuits, and multiphase control of the step-down chopper circuits is performed using gate signals having phases displaced from each other. This shortens the period with which output signals of the step-down chopper circuits are changed. Shortening the period reduces the amount of jitter resulting from a gap between the occurrence of a command signal and a sampling point that is a point in time at which a gate signal is generated. The number of phases of the gate signals equals the number of phases of the step-down chopper circuits. The control of the gate signal generator is asynchronous to feedback control by the controller. Points in time (sampling points) at which gate signals are generated are points in time of generation (sampling points) after a point in time at which the controller calculates a manipulated value.

Claims

1. A power supply device having variable output voltage, the power supply device comprising: a multiphase chopper section including step-down chopper circuits of a plurality of phases connected in parallel; a controller for calculating a manipulated value for controlling the chopper section from a feedback signal outputted from the chopper section and a command signal; and a gate signal generator for generating gate signals for performing multiphase control of turning on/off of switching elements included in the step-down chopper circuits of the respective phases based on the manipulated value in phases displaced from each other, wherein the number of phases of the gate signals equals the number of phases of the step-down chopper circuits, and in the gate signal generator, gate signals are generated with the same sampling period for the respective phases by sampling synchronous with generation of the gate signals and asynchronous to the command signal, and sampling points at which the gate signals are generated are sampling points after a point in time at which the controller calculates the manipulated value.

2. The power supply device according to claim 1, wherein the gate signal generator includes a pulse width modulator for generating gate signals having pulse widths according to the manipulated value for the respective phases, and a phase adjuster for performing phase adjustment in which phases of the gate signals of the respective phases are staggered by a phase difference obtained by dividing the sampling period by the number of phases.

3. The power supply device according to claim 2, wherein the gate signal generator has a configuration in which the pulse width modulator generates the gate signals of the respective phases having the pulse widths according to the manipulated value using carrier signals of the respective phases phase-adjusted by the phase adjuster, the gate signal generator includes a phase shifter for phase-shifting the manipulated value by a phase difference obtained by dividing the sampling period by the number of phases for each phase in order, the phase adjuster generates carrier signals for the respective phases with phases displaced from each other by a phase difference obtained by dividing the sampling period by the number of phases, and the pulse width modulator generates the gate signals based on amplitude comparison between the manipulated value and the carrier signals of the respective phases.

4. The power supply device according to claim 2, wherein the gate signal generator has a configuration in which the phase adjuster adjusts phases of the gate signals of the respective phases having the pulse widths according to the manipulated value generated by the pulse width modulator, the pulse width modulator generates a gate signal based on comparison between the manipulated value and the carrier signals, and the phase adjuster staggers the phases of the gate signals generated by the pulse width modulator by a phase difference obtained by dividing the sampling period by the number of phases to generate the gate signals of the respective phases.

5. A method for controlling a power supply device, the method capable of changing output voltage based on a command signal by feedback control of a multiphase chopper section including a plurality of step-down chopper circuits connected in parallel, the method comprising: a gate signal generation step for generating gate signals for performing multiphase control of turning on/off of switching elements included in the step-down chopper circuits of the respective phases based on a manipulated value of the feedback control in phases displaced from each other, by sampling performed with the same sampling period for the respective phases, wherein the gate signal generation step includes a pulse width modulation step for generating gate signals having pulse widths according to the manipulated value for the respective phases, and a phase adjustment step for performing phase adjustment in which phases of the gate signals of the respective phases are staggered by a phase difference obtained by dividing the sampling period by the number of phases, and the sampling is synchronous with generation of the gate signals and asynchronous to the command signal.

6. The method for controlling power supply device according to claim 5, wherein the gate signal generation step is the step of generating the gate signals of the respective phases having the pulse widths according to the manipulated value by the pulse width modulation step using carrier signals of the respective phases phase-adjusted in the phase adjustment step, the gate signal generation step includes a phase shift step for phase-shifting the manipulated value by a phase difference obtained by dividing the sampling period by the number of phases for each phase in order, the phase adjustment step generates carrier signals for the respective phases with phases displaced from each other by a phase difference obtained by dividing the sampling period by the number of phases, and the pulse width modulation step generates the gate signals based on amplitude comparison between the manipulated value and the carrier signals of the respective phases.

7. The method for controlling power supply device according to claim 5, wherein the gate signal generation step is the step of adjusting, by the phase adjustment step, phases of the gate signals of the respective phases having the pulse widths according to the manipulated value generated in the pulse width modulation step, and the pulse width modulation step generates the gate signals of the respective phases based on comparison between the manipulated values of the respective phases and the same carrier signal, and the phase adjustment step staggers the phases of the gate signals of the respective phases generated in the pulse width modulation step by a phase difference obtained by dividing the sampling period by the number of phases.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram for explaining a schematic configuration example of a power supply device of the present invention.

(2) FIG. 2 is a diagram for explaining a schematic configuration example of a first power supply device of the present invention.

(3) FIG. 3 is a diagram for explaining a schematic configuration example including a pulse width modulator using a carrier signal of the present invention.

(4) FIG. 4 is a diagram for explaining one configuration example including the pulse width modulator using the carrier signal of the present invention.

(5) FIG. 5 is a diagram for explaining sampling points in two-phase control in a power supply device of the present invention.

(6) FIG. 6 is a flowchart for explaining the generation of gate signals by two-phase control in the power supply device of the present invention.

(7) FIG. 7 is a diagram for explaining the generation of gate signals and jitter on output voltage by two-phase control in the power supply device of the present invention.

(8) FIG. 8 is a diagram for explaining sampling points in three-phase control in the power supply device of the present invention.

(9) FIG. 9 is a flowchart for explaining the generation of gate signals by three-phase control in the power supply device of the present invention.

(10) FIG. 10 is a diagram for explaining sampling points in three-phase control in the power supply device of the present invention.

(11) FIG. 11 is a diagram for explaining a schematic configuration example of a power supply device of a second embodiment of the present invention.

(12) FIG. 12 is a flowchart for explaining the generation of gate signals in the second embodiment of the present invention.

(13) FIG. 13 is a diagram for explaining a timing diagram of a manipulated value and gate signals in the second embodiment of the present invention.

(14) FIG. 14 is a diagram for explaining the circuit configuration of a step-down chopper circuit using a pulse width modulator (PWM controller).

(15) FIG. 15 is a diagram for explaining jitter occurring in a single-phase step-down chopper circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(16) A power supply device of the present invention and a method for controlling the power supply device will be described with reference to FIGS. 1 to 13. Hereinafter, a schematic configuration example of the power supply device of the present invention will be described with reference to FIG. 1, a first configuration example of the power supply device of the present invention and a first embodiment of the control method will be described with reference to FIGS. 2 to 10, and a second configuration example of the power supply device of the present invention and a second embodiment of the control method will be described with reference to FIGS. 11 to 13.

(17) [Schematic Configuration of Power Supply Device of the Present Invention]

(18) FIG. 1 is a diagram for explaining a schematic configuration example of the power supply device of the present invention.

(19) A power supply device 1 includes a chopper section 30 that controls an input voltage Vin and outputs an output voltage Vout, a controller 10 that performs voltage control for the chopper section 30, and a gate signal generator 20 that generates gate signals of two or more phases for controlling the chopper section 30 based on a manipulated value MV controlled by the controller 10.

(20) The chopper section 30 includes step-down chopper circuits 30A to 30N connected in parallel, and performs multiphase control in which the step-down chopper circuits 30A to 30N are driven in the respective phases.

(21) An output of the chopper section 30 is fed back to the controller 10. The controller 10 compares the feedback signal and a command voltage Vref to perform voltage control, and calculates the manipulated value MV for controlling the chopper section 30. The feedback signal may be, for example, the output voltage Vout, the input voltage Vin, inductance current iL flowing through inductances included in the step-down chopper circuits, or capacitor current iC flowing through capacitances included in the step-down chopper circuits.

(22) Based on the manipulated value MV calculated by the controller 10, the gate signal generator 20 generates gate signals for performing multiphase control of the turning on/off of switching elements (not illustrated in FIG. 1) included in the step-down chopper circuits 30A to 30N of the respective phases. The gate signals are gate signals (phase-A gate signal, phase-B gate signal, . . . , and phase-N gate signal) of the two or more phases displaced from each other, and are generated in the respective phases with the same sampling period. Accordingly, the gate signals of the respective phases have the same intervals between gate signals, and the gate signals of the respective phases have phase shifts therebetween. The number of phases of the gate signals of the gate signal generator 20 equals the number N of phases of the step-down chopper circuits 30A to 30N. It should be noted that in this example, N phase is described, where N (integer greater than or equal to two) is the number of phases of the two or more phases.

(23) In the gate signal generator 20, sampling is synchronous with the generation of the gate signals but not synchronous with a command signal. Meanwhile, in the main control of the controller 10, feedback control is performed based on the command signal and the feedback signal to find the manipulated value MV. Accordingly, sampling is synchronous with the generation of the gate signals but not synchronous with the command signal. Thus, the calculation timing of the manipulated value MV calculated by the controller 10 does not necessarily coincide with the generation timing of the gate signals generated by the gate signal generator 20.

(24) The gate signal generator 20 of the present invention performs sampling using a sampling point that is a point in time at which a gate signal is generated, as a sampling point appearing after a point in time at which the controller 10 calculates the manipulated value MV, thus generating a gate signal. In the following explanation, the points in time at which the gate signals are generated are referred to as sampling points.

(25) A displacement corresponding to one period between adjacent sampling points occurs between the point in time at which the manipulated value MV is calculated and a sampling point at the point in time of the next sampling point, at sampling points of the two or more phases at most.

(26) The gate signal generator 20 includes a pulse width modulator 20b that generates gate signals having a pulse width according to the manipulated value MV for the respective phases, and a phase adjuster 20a that performs phase adjustment in which the phases of the gate signals of the respective phases are staggered by a phase difference obtained by dividing the sampling period by the number of phases.

(27) The phase adjuster 20a adjusts the phases of the gate signals of the respective phases to reduce the gap between the gate signals of adjacent phases out of the two or more phases to a period corresponding to the phase difference obtained by dividing the sampling period by the number of phases. This reduces the amount of the gap between adjacent sampling points and reduces the amount of jitter, which is a gap in time between rising edges of the output voltage.

(28) FIG. 1(b) to FIG. 1(d) illustrate examples of a phase-A gate signal, a phase-B gate signal, and a phase-N gate signal. FIG. 1(e) illustrates an example of a gate signal of the two or more phases obtained by superimposing all the phases, phase A to phase N.

(29) The period Tph between signals is common to the phase-A gate signal, the phase-B gate signal, and the phase-N gate signal, the phases of which are staggered by T (=Tph/N) obtained by dividing the period Tph by the number N of phases. Thus, the period T of the gate signal of the two or more phases obtained by superimposing these phases is 1/N of the period Tph of each phase.

(30) The gate signal generator 20 includes a phase shifter 20c, and phase-shifts the manipulated value MV, which is calculated by the controller 10, by a phase difference obtained by dividing the sampling period by the number of phases for each phase in order. Shifting the manipulated value MV by the phase shifter 20c makes it possible to match the phase of the manipulated value and the phases of the generated gate signals of the respective phases in the generation of the gate signals by the pulse width modulator 20b.

First Embodiment of Power Supply Device and Control Method of the Present Invention

(31) Next, a first embodiment of the power supply device and the control method of the present invention will be described with reference to FIGS. 2 to 10. FIG. 2 illustrates a schematic configuration example of a first power supply device. FIGS. 3 and 4 illustrate a schematic configuration example including pulse width modulators using carrier signals and one configuration example.

(32) The schematic configuration example illustrated in FIG. 2 illustrates a configuration example of the gate signal generator 20. Other part of the configuration is common to the schematic configuration example illustrated in FIG. 1. Accordingly, an explanation about the configuration example of the gate signal generator 20 will be made here, and an explanation about other part will be omitted.

(33) A first embodiment of the gate signal generator included in the power supply device 1 has a configuration in which using a carrier signal of each phase with the phase adjusted by the phase adjuster 20a, the pulse width modulator 20b generates a gate signal of each phase having a pulse width according to the manipulated value MV.

(34) The gate signal generator 20 in FIG. 2 includes a phase-A gate signal generator 20A, a phase-B gate signal generator 20B, . . . , and a phase-N gate signal generator 20N, which generate multiphase gate signals (phase-A gate signal, phase-B gate signal, . . . , and phase-N gate signal) of phase A to phase N having phases displaced from each other.

(35) The gate signal generators of the respective phases have a common configuration. Accordingly, an explanation about the phase-A gate signal generator 20A will be made, and an explanation about the gate signal generators of the other phases will be omitted.

(36) The phase-A gate signal generator 20A includes a phase shifter 20c that receives the manipulated value MV calculated by the controller 10, a pulse width modulator 20b that receives the manipulated value MV phase-shifted by a phase difference obtained by dividing the sampling period by the number of phases in the phase shifter 20c, and a phase adjuster 20a that adjusts the phase of the carrier signal, amplitude of which is compared with that of the manipulated value MV in the pulse width modulator 20b.

(37) The phase adjusters 20a generate carrier signals with phases displaced from each other by a phase difference obtained by dividing the sampling period by the number of phases, for the respective phases. The pulse width modulators 20b compare the amplitude of the manipulated value MV and those of the carrier signals of the respective phases with the phases adjusted by the phase adjusters 20a to generate gate signals.

(38) The phase shifters 20c phase-shift the manipulated value by a phase difference obtained by dividing the sampling period by the number of phases for each phase in order. Accordingly, the amount of phase shift by the phase shifter 20Ac of the phase-A gate signal generator 20A, the amount of phase shift by the phase shifter 20Bc of the phase-B gate signal generator 20B, and the amount of phase shift by the phase shifter 20Nc of the phase-N gate signal generator 20N are different from each other, and the amounts of phase shift increase in order by the phase difference.

(39) FIG. 3 illustrates an example in which a triangle waveform signal is used as a carrier signal for use in pulse width modulation in the configuration of the gate signal generator 20 illustrated in FIG. 2. In FIG. 3, an explanation about the phase-A gate signal generator 20A will be made, and an explanation about the gate signal generators of the other phases will be omitted.

(40) In the phase-A gate signal generator 20A, the pulse width modulator 20Ab compares the amplitude of the manipulated value MV phase-shifted by the phase shifter 20Ac with that of the carrier signal having a triangle waveform to generate a gate signal. It should be noted that the triangle waveform may have any waveform shape having a linearly changing amplitude, such as a tooth wave with a waveform shape having an amplitude that linearly increases and decreases at a rising edge and a falling edge of the waveform or a waveform shape having an amplitude that rises at a rising edge of the waveform in one step and that linearly decreases at a falling edge thereof.

(41) In the configuration illustrated in FIG. 3, the phase adjuster 20C adjusts the phases of the carrier signals to be supplied to the respective pulse width modulators 20Ab, 20Bb, . . . , and 20Nb to form phase shifts between gate signals outputted from the pulse width modulators 20Ab, 20Bb, . . . , and 20Nb.

(42) The phase shifters 20Ac to 20Nc eliminate phase shifts from the manipulated value MV in the comparison with the carrier signals in all the pulse width modulators 20Ab to 20Nb by matching phases with the carrier signals, phases of which are compared in the pulse width modulators 20Ab to 20Nb. If the phase shifters 20Ac to 20Nc do not phase-shift the manipulated value MV, amplitude modulation is to be performed with carrier signals having phases displaced by phase adjustment, and phase displacement may occur in generated gate signals. However, since the phase shifters 20Ac to 20Nc match the phase of the manipulated value MV with the phases of the carrier signals, phase displacement of gate signals in phase adjustment can be prevented.

Embodiment for Two-Phase Control

(43) Hereinafter, an embodiment in which two-phase control is performed will be described with reference to FIGS. 4 to 7.

(44) FIG. 4 illustrates a circuit example of a power supply device in which two-phase control is performed by multiphase control of chopper circuits.

(45) The chopper section 30 includes a chopper circuit 30A of phase A and a chopper circuit 30B of phase B connected in parallel. The two chopper circuits 30A and 30B are connected to a capacitor C and a load R connected in parallel. The chopper section 30 performs two-phase control of the chopper circuits 30A and 30B in different phases, and controls the input voltage Vin to output the output voltage Vout.

(46) The chopper circuit 30A includes a switching element S1A connected in series, a switching element S2A connected in parallel, and an inductance LA connected in series. The chopper circuit 30B includes a switching element S1B connected in series, a switching element S2B connected in parallel, and an inductance LB connected in series.

(47) The turning on/off of the switching element S1A and the switching element S2A is controlled by a gate signal Gate1-A and a gate signal Gate2-A. Similarly, the turning on/off of the switching element S1B and the switching element S2B is controlled by a gate signal Gate1-B and a gate signal Gate2-B. It should be noted that the gate signal Gate1-A and the gate signal Gate2-A are in an inversion relation, and the gate signal Gate1-B and the gate signal Gate2-B are in an inversion relation. The switching elements, which are driven by the respective gate signals, are turned on/off in inverse phases.

(48) The main control of the chopper section 30 is performed by the controller 10. The controller 10 performs voltage control based on the difference between a feedback signal from the chopper section 30 and the command voltage Vref to output the manipulated value MV. With regard to the voltage control, for example, a high voltage and a low voltage are alternately inputted as the command voltage Vref to perform High/Low control.

(49) The manipulated value MV outputted from the controller 10 is inputted to the gate signal generator 20. The gate signal generator 20 includes a phase-A gate signal generator 20A and a phase-B gate signal generator 20B, which generate gate signals for driving the switching elements of the chopper circuit 30A and the chopper circuit 30B, respectively. The phase-A gate signal generator 20A includes a phase shifter (Shifter A) and a pulse width modulator (Comparator A). The phase-A gate signal generator 20A shifts the phase of the manipulated value MV by 0 or 180 degrees, and then compares the amplitude of the manipulated value MV with that of the triangle waveform (Triangle-A or Sawtooth-A) of the carrier signal to generate the gate signals (Gate1-A and Gate2-A) of phase A. The phase-B gate signal generator 20B, similar to the phase-A gate signal generator 20A, includes a phase shifter (Shifter B) and a pulse width modulator (Comparator B). The phase-B gate signal generator 20B shifts the phase of the manipulated value MV by 0 or 180 degrees, and then compares the amplitude of the manipulated value MV with that of the triangle waveform (Triangle-B or Sawtooth-B) of the carrier signal to generate the gate signals (Gate1-B and Gate2-B) of phase B.

(50) FIG. 5 illustrates sampling points in two-phase control. FIG. 5(a) illustrates sampling points (kA1, kA, kA+1, kA+2, and kA+3) of phase A, and FIG. 5(b) illustrates sampling points (kB1, kB, kB+1, kB+2, and kB+3) of phase B. The sampling points are points in time at which gate signals are generated. The sampling points of phase A and phase B have the same period and a phase shift of (=2/2) therebetween.

(51) FIG. 5(c) and FIG. 5(d) illustrate superimposed sampling points of two phases, phase A and phase B. By superimposing sampling points of two phases, the period of sampling points in two-phase control is reduced to of the period of sampling points of each of phase A and phase B.

(52) By reducing the period of sampling points to , the width of the time delay between the point in time at which the command signal is changed and the point in time at which the gate signal is updated can be reduced. FIG. 5(c) illustrates a state in which the command is changed before sampling point kA, and FIG. 5(d) illustrates a state in which the command is changed after sampling point kA. In the case where the command is changed before sampling point kA, the gate signal is updated between sampling point kA and sampling point kB+1. In the case where the command is changed after sampling point kA, the gate signal is updated at a point in time delayed by of the period of each phase between sampling point kB+1 and sampling point kA+1. Jitter results from the times of update of the above-described two gate signals, and the time width between the times of update of the two gate signals is of the single-phase period at most. Accordingly, the amount of jitter is smaller than that in single-phase control.

(53) Next, the generation of gate signals in two-phase control will be described with reference to the flowchart in FIG. 6. The following description will be made using the sign S.

(54) When the command voltage Vref is changed (S1), a controller for power supply control finds the manipulated value MV by main control in which an output signal of a chopper section and the command voltage Vref are compared (S3). It should be noted that the gate signals (GateA and GateB) found last time are maintained (S2) until the command voltage Vref is changed.

(55) Gate signals are generated at the first sampling point appearing after the command voltage Vref is changed (S4).

(56) If sampling point kA of phase A appears after the command voltage Vref is changed (S4), phase A is set as the reference phase (S5), and the amplitude of the manipulated value MV and that of the carrier signal of phase A are compared to generate a gate signal GateA of phase A (S6). The manipulated value MV of phase A as the reference phase is phase-shifted by (=2/2) to generate a manipulated value MV-B of phase B (S7). The amplitude of the manipulated value MV-B generated and that of the carrier signal of phase B are compared to generate a gate signal GateB of phase B (S8).

(57) If sampling point kB of phase B appears after the command voltage Vref is changed (S4), phase B is set as the reference phase (S9), and the amplitude of the manipulated value MV and that of the carrier signal of phase B are compared to generate the gate signal GateB of phase B (S10). The manipulated value MV of phase B as the reference phase is phase-shifted by (=2/2) to generate a manipulated value MV-A of phase A (S11). The amplitude of the manipulated value MV-A generated and that of the carrier signal of phase A are compared to generate the gate signal GateA of phase A (S12).

(58) FIG. 7 illustrates the generation of gate signals in two-phase control and jitter on the output voltage. FIG. 7(a) illustrates the generation of gate signals for the case where the command voltage Vref is changed immediately before sampling point kA. FIG. 7(b) illustrates the generation of gate signals for the case where the command voltage Vref is changed immediately after sampling point kA. FIG. 7(c) illustrates jitter on the output voltage.

(59) In FIG. 7(a), in the case where the command voltage Vref is changed immediately before sampling point kA, two-phase control is performed using phase A as the reference phase.

(60) With regard to gate signals of phase A as the reference phase, the manipulated value MV is used as the manipulated value MV-A, and gate signals (Gate1-A and Gate2-A) are generated at sampling point kA by comparing the amplitude of the manipulated value MV-A and that of the carrier signal (Triangle-A). On the other hand, with regard to gate signals of phase B, gate signals (Gate1-B and Gate2-B) are generated at the next sampling point kB+1, by comparing the amplitude of the manipulated value MV-B, which is obtained by phase-shifting the manipulated value MV-A of phase A as the reference phase by (=2/2), and that of the carrier signal (Triangle-B).

(61) By driving the chopper circuit of phase A using the gate signals (Gate1-A and Gate2-A) of phase A, an inductance current iL-A is passed through the inductance LA. By driving the chopper circuit of phase B using the gate signals (Gate1-B and Gate2-B) of phase B, an inductance current iL-B is passed through the inductance LB. iL is a current obtained by summing the inductance current iL-A and the inductance current iL-B.

(62) In FIG. 7(b), in the case where the command voltage Vref is changed immediately after sampling point kA, two-phase control is performed using phase B as the reference phase.

(63) With regard to gate signals of phase B as the reference phase, the manipulated value MV is used as the manipulated value MV-B, and the gate signals (Gate1-B and Gate2-B) are generated at sampling point kB+1 by comparing the amplitude of the manipulated value MV-B and that of the carrier signal (Triangle-B). On the other hand, with regard to gate signals of phase A, the gate signals (Gate1-A and Gate2-A) are generated at the next sampling point kA+1, by comparing the amplitude of the manipulated value MV-A, which is obtained by phase-shifting the manipulated value MV-B by (=2/2), and that of the carrier signal (Triangle-A).

(64) By driving the chopper circuit of phase B using the gate signals (Gate1-B and Gate2-B) of phase B, the inductance current iL-B is passed through the inductance LB. By driving the chopper circuit of phase A using the gate signals (Gate1-A and Gate2-A) of phase A, the inductance current iL-A is passed through the inductance LA. iL is a current obtained by summing the inductance current iL-A and the inductance current iL-B.

(65) FIG. 7(c) illustrates the output voltage and the inductance current iL (indicated by a solid line in the drawing) obtained in the state illustrated by FIG. 7(a) and the output voltage and the inductance current iL (indicated by a broken line in the drawing) obtained in the state illustrated by FIG. 7 (b). The time difference between the two output voltages is denoted by jitter.

(66) Jitter on the output voltage for the case where the command voltage is changed around sampling point kA is of the period for single-phase control at most.

Embodiment for Three-Phase Control

(67) Hereinafter, an embodiment in which three-phase control is performed will be described with reference to FIGS. 8 to 10.

(68) FIG. 8 illustrates sampling points of three-phase control. FIG. 8(a) illustrates sampling points (kA1, kA, kA+1, kA+2, and kA+3) of phase A. FIG. 8(b) illustrates sampling points (kB1, kB, kB+1, kB+2, and kB+3) of phase B. FIG. 8(c) illustrates sampling points (kC1, kC, kC+1, kC+2, and kC+3) of phase C. The sampling points are points in time at which gate signals are generated. The sampling points of phase A, phase B, and phase C have the same period and phase shifts of (=2/3) therebetween.

(69) FIG. 8(d) and FIG. 8(e) illustrate superimposed sampling points of three phases, phase A, phase B, and phase C. By superimposing sampling points of three phases, the period of sampling points of three-phase control is reduced to of the period of sampling points of each of phase A, phase B, and phase C.

(70) By reducing the period of sampling points to , the width of the time delay between the point in time at which the command signal is changed and the point in time at which the gate signal is updated can be reduced. FIG. 8(d) illustrates a state in which the command is changed before sampling point kA, and FIG. 8(e) illustrates a state in which the command is changed after sampling point kA. In the case where the command is changed before sampling point kA, the gate signal is updated between sampling point kA and sampling point kB+1. In the case where the command is changed after sampling point kA, the gate signal is updated at a point in time delayed by of the period of each phase between sampling point kB+1 and sampling point kC+2. Jitter results from the times of update of the above-described two gate signals, and the time width between the times of update of the two gate signals is of the period of each phase at most. Accordingly, the amount of jitter is smaller than that in single-phase control.

(71) Next, the generation of gate signals in three-phase control will be described with reference to the flowchart in FIG. 9. The following description will be made using the sign S.

(72) When the command voltage Vref is changed (S21), a controller for power supply control finds the manipulated value MV by main control in which an output signal of a chopper section and the command voltage Vref are compared (S23). It should be noted that the gate signals (GateA and GateB) found last time are maintained (S22) until the command voltage Vref is changed.

(73) Gate signals are generated at the first sampling point appearing after the command voltage Vref is changed (S24).

(74) If sampling point kA of phase A appears after the command voltage Vref is changed (S24) phase A is set as the reference phase (S25), and the amplitude of the manipulated value MV and that of the carrier signal of phase A are compared to generate the gate signal GateA of phase A (S26). The manipulated value MV of phase A as the reference phase is phase-shifted by 2/3 to generate the manipulated value MV-B of phase B (S27). The amplitude of the manipulated value MV-B generated and that of the carrier signal of phase B are compared to generate the gate signal GateB of phase B (S28). The manipulated value MV of phase A as the reference phase is phase-shifted by 4/3 (=2.Math.(2/3)) to generate the manipulated value MV-C of phase C (S29). The amplitude of the manipulated value MV-C generated and that of the carrier signal of phase C are compared to generate a gate signal GateC of phase C (S30).

(75) If sampling point kB of phase B appears after the command voltage Vref is changed (S24), phase B is set as the reference phase (S31), and the amplitude of the manipulated value MV and that of the carrier signal of phase B are compared to generate the gate signal GateB of phase B (S32). The manipulated value MV of phase B as the reference phase is phase-shifted by 2/3 to generate the manipulated value MV-C of phase C (S33). The amplitude of the manipulated value MV-C generated and that of the carrier signal of phase C are compared to generate the gate signal GateC of phase C (S34). The manipulated value MV of phase B as the reference phase is phase-shifted by 4/3 (=2.Math.(2/3)) to generate the manipulated value MV-A of phase A (S35). The amplitude of the manipulated value MV-A generated and that of the carrier signal of phase A are compared to generate the gate signal GateA of phase A (S36).

(76) If sampling point kC of phase C appears after the command voltage Vref is changed (S24), phase C is set as the reference phase (S37), and the amplitude of the manipulated value MV and that of the carrier signal of phase C are compared to generate the gate signal GateC of phase C (S38). The manipulated value MV of phase C as the reference phase is phase-shifted by 2/3 to generate the manipulated value MV-A of phase A (S39). The amplitude of the manipulated value MV-A generated and that of the carrier signal of phase A are compared to generate the gate signal GateA of phase A (S40). The manipulated value MV of phase C as the reference phase is phase-shifted by 4/3 (=2.Math.(2/3)) to generate the manipulated value MV-B of phase B (S41). The amplitude of the manipulated value MV-B generated and that of the carrier signal of phase B are compared to generate the gate signal GateB of phase B (S42).

(77) FIG. 10 illustrates the generation of gate signals in three-phase control. FIG. 10(a) illustrates the generation of gate signals for the case where the command voltage Vref is changed immediately before sampling point kA. FIG. 10(b) illustrates the generation of gate signals for the case where the command voltage Vref is changed immediately after sampling point kA. It should be noted that FIG. 10 illustrates an example in which phase A is used as the reference phase.

(78) In FIG. 10(a), in the case where the command voltage Vref is changed immediately before sampling point kA, three-phase control is performed using phase A as the reference phase.

(79) With regard to gate signals of phase A as the reference phase, the manipulated value MV is used as the manipulated value MV-A, and the gate signals (Gate1-A and Gate2-A) are generated at sampling point kA by comparing the amplitude of the manipulated value MV-A and that of the carrier signal (Triangle-A). With regard to gate signals of phase B, the gate signals (Gate1-B and Gate2-B) are generated at the next sampling point kB+1, by comparing the amplitude of the manipulated value MV-B, which is obtained by phase-shifting the manipulated value MV-A of phase A as the reference phase by 2/3, and that of the carrier signal (Triangle-B). With regard to gate signals of phase C, the gate signals (Gate1-C and Gate2-C) are generated at the sampling point after the next kC+2, by comparing the manipulated value MV-C, which is obtained by phase-shifting the manipulated value MV-A of phase A as the reference phase by 4/3, and that of the carrier signal (Triangle-C).

(80) In FIG. 10(b), in the case where the command voltage Vref is changed immediately after sampling point kA, three-phase control is performed using phase B as the reference phase.

(81) With regard to gate signals of phase B as the reference phase, the manipulated value MV is used as the manipulated value MV-B, and the gate signals (Gate1-B and Gate2-B) are generated at sampling point kB+1 by comparing the amplitude of the manipulated value MV-B and that of the carrier signal (Triangle-B). With regard to gate signals of phase C, the gate signals (Gate1-C and Gate2-C) are generated at the next sampling point kC+2, by comparing the amplitude of the manipulated value MV-C, which is obtained by phase-shifting the manipulated value MV-B of phase B as the reference phase by 2/3, and that of the carrier signal (Triangle-C). With regard to gate signals of phase A, the gate signals (Gate1-A and Gate2-A) are generated at the sampling point after the next kC+2, by comparing the amplitude of the manipulated value MV-A, which is obtained by phase-shifting the manipulated value MV-B of phase B as the reference phase by 4/3, and that of the carrier signal (Triangle-A).

Configuration Example of Second Power Supply Device and Embodiment of Control Method of the Present Invention

(82) Next, a second embodiment of the power supply device and the control method of the present invention will be described with reference to FIGS. 11 to 13. FIG. 11 illustrates a schematic configuration example of the power supply device of the second embodiment. FIG. 12 illustrates a flowchart of the second embodiment. FIG. 13 illustrates a timing diagram of a manipulated value and gate signals.

(83) The second embodiment has a configuration in which in a gate signal generator, the phases of gate signals of the respective phases having pulse widths according to the manipulated value generated by a pulse width modulator are adjusted by phase adjusters.

(84) The schematic configuration example illustrated in FIG. 11 represents a configuration example of the gate signal generator 20. Other part of the configuration is common to the schematic configuration example illustrated in FIG. 1. Accordingly, an explanation about the configuration example of the gate signal generator 20 will be made here, and an explanation about other part will be omitted.

(85) In the gate signal generator 20 of the second embodiment, the pulse width modulator 20b generates a gate signal using the amplitude of the manipulated value MV of the controller 10 and that of the carrier signal generated by the carrier signal generator 20d to generate a gate signal. Phase adjusters 20Aa, 20Ba, . . . , and 20Na stagger the phases of the gate signals generated by the pulse width modulator 20b by a phase difference obtained by dividing the sampling period by the number N of phases to generate gate signals (phase-A gate signal, phase-B gate signal, . . . , and phase-N gate signal) of the respective phases.

(86) The phase adjustment of gate signals by the phase adjusters 20Aa, 20Ba, . . . , and 20Na is performed in accordance with phase shifts from the reference phase. For example, in the case where phase A is used as the reference phase, the phase adjuster 20Aa of phase A does not need to perform phase adjustment, and outputs the gate signal of the pulse width modulator 20b as the phase-A gate signal without performing phase adjustment.

(87) On the other hand, in the case where phase A is used as the reference phase, the phase adjuster 20Ba of phase B adjusts the phase of the gate signal of the pulse width modulator 20b by a phase difference of 2/N and outputs the phase-adjusted gate signal as the phase-B gate signal, the phase adjuster 20Ca of phase C adjusts the phase of the gate signal of the pulse width modulator 20b by a phase difference of 2(2/N) and outputs the phase-adjusted gate signal as the phase-C gate signal, and the phase adjuster 20Na of phase N adjusts the phase of the gate signal of the pulse width modulator 20b by a phase difference of (N1).Math.(2/N) and outputs the phase-adjusted gate signal as the phase-N gate signal.

(88) The gate signal generator 20 of the second embodiment has a configuration in which the phase of the gate signal obtained by comparing the manipulated value MV and the carrier signal in the pulse width modulator 20b is adjusted for the respective phases by the phase adjusters 20Aa to 20Na. Accordingly, the phase shifter provided in the first embodiment to match the phase of the manipulated value and that of the carrier signal is unnecessary.

(89) Next, the generation of gate signals in the second embodiment will be described with reference to the flowchart in FIG. 12 by taking the case of two-phase control as an example. The following description will be made using the sign S.

(90) When the command voltage Vref is changed (S51), a controller for power supply control finds the manipulated value MV (S53) by main control in which an output signal of a chopper section and the command voltage Vref are compared. It should be noted that the gate signals (GateA and GateB) found last time are maintained (S52) until the command voltage Vref is changed.

(91) Gate signals are generated at the first sampling point appearing after the command voltage Vref is changed. If the first sampling point is a sampling point of phase A, the chopper circuit of phase A is controlled using the generated gate signal as the gate signal GateA of phase A. On the other hand, if the first sampling point is a sampling point of phase B, the chopper circuit of phase B is controlled using the generated gate signal as the gate signal GateB of phase B (S54).

(92) Next, the generated gate signal is shifted by to generate a gate signal of the other phase at the next sampling point.

(93) If the first sampling point is a sampling point of phase A, the phase of the gate signal generated previously is adjusted by , and the chopper circuit of phase B is controlled using the phase-adjusted gate signal as the gate signal GateB. On the other hand, if the first sampling point is a sampling point of phase B, the phase of the gate signal generated previously is adjusted by , and the chopper circuit of phase A is controlled using the phase-adjusted gate signal as the gate signal GateA (S55).

(94) FIG. 13 illustrates the generation of gate signals in two-phase control in the second embodiment. FIG. 13 illustrates the generation of gate signals for the case where the command voltage Vref is changed immediately before sampling point kA.

(95) In FIG. 13, in the case where the command voltage Vref is changed immediately before sampling point kA, two-phase control is performed using phase A as the reference phase.

(96) With regard to gate signals of phase A as the reference phase, the gate signals (Gate1-A and Gate2-A) are generated at sampling point k by comparing the amplitude of the manipulated value MV and that of the carrier signal. On the other hand, with regard to gate signals of phase B, the phase-B gate signals (Gate1-B and Gate2-B) are generated by shifting the phases of the phase-A gate signals (Gate1-A and Gate2-A) by .

(97) The chopper circuit of phase A is driven using the gate signals (Gate1-A and Gate2-A) of phase A, and the chopper circuit of phase B is driven using the gate signals (Gate1-B and Gate2-B) of phase B.

(98) According to the first and second embodiments of the present invention, jitter on the output voltage can be reduced in accordance with the number of phases by performing High/Low pulse control in the power supply device.

(99) For example, the time width Jitter of jitter can be represented by the following arithmetic equation:
Jitter=(1/fsw)(1/N)
where fsw is the switching frequency and N is the number of phases.

(100) According to the first and second embodiments of the present invention, even if the switching frequencies with which chopper circuits are driven cannot be increased due to limitations such as losses in switching elements, the time width of jitter on the output voltage can be greatly reduced by increasing the number N of phases of chopper circuits.

(101) For example, even if switching elements such as low-frequency IGBTs having a switching frequency fsw of approximately 20 kHz are used, a time width of jitter of 100 ns can be realized with 500 (=( 1/20 kHz)/100 ns) phases based on the equation N=(1/fsw)/Jitter.

(102) It should be noted that the above-described descriptions in the embodiments and the modified examples are examples of the power supply device according to the present invention. The present invention is not limited to the embodiments, and various modifications can be made to the embodiments based on the spirit of the present invention. These modifications are not excluded from the scope of the present invention.

INDUSTRIAL APPLICABILITY

(103) The power supply device of the present invention can be applied to the supply of high-frequency power to an apparatus using high frequency such as an apparatus for manufacturing a semiconductor, a liquid crystal panel, or the like, a vacuum deposition apparatus, or a heating and melting apparatus.

DESCRIPTION OF REFERENCE NUMERALS

(104) 1 power supply device 10 controller 20 gate signal generator 20A phase-A gate signal generator 20Aa phase adjuster 20Ab-20Nb pulse width modulator 20Ac-20Nc phase shifter 20B phase-B gate signal generator 20Ba phase adjuster 20Bb pulse width modulator 20Ca phase adjuster 20N phase-N gate signal generator 20a phase adjuster 20b pulse width modulator 20c phase shifter 20d carrier signal generator 30 chopper section 30A-30N step-down chopper circuit Gate1 gate signal Gate2 gate signal GateA gate signal GateB gate signal GateC gate signal iC capacitor current iL inductance current iL-A inductance current iL-B inductance current Jitter time width k sampling point kA sampling point kB sampling point kC sampling point LA inductance LB inductance MV manipulated value MV-A manipulated value MY-B manipulated value MV-C manipulated value S1, S2 switching element S1A switching element S1B switching element S2A switching element S2B switching element Vout output voltage Vref command voltage