Receiver automatic gain control systems and methods for asymmetrical or unbalanced constellations

Abstract

An automatic gain control system for a receiver for an asymmetrical and/or unbalanced constellation, the system including: an automatic gain control loop adapted to be coupled to both a first transimpedance amplifier coupled to a first analog-to-digital converter forming a first tributary and a second transimpedance amplifier coupled to a second analog-to-digital converter forming a second tributary; wherein the automatic gain control loop is operable for providing an offset gain control voltage to gain balance a transimpedance amplifier voltage and a power associated with the first tributary and a transimpedance amplifier voltage and a power associated with the second tributary. The automatic gain control loop includes an analog automatic gain control loop. The automatic gain control loop is implemented in hardware or firmware.

Claims

1. An automatic gain control system for a receiver, the system comprising: an automatic gain control loop adapted to be coupled to both a first transimpedance amplifier coupled to a first analog-to-digital converter forming a first tributary and a second transimpedance amplifier coupled to a second analog-to-digital converter forming a second tributary; wherein the automatic gain control loop is operable to provide an offset gain control voltage to gain balance a transimpedance amplifier voltage and a power associated with the first tributary and a transimpedance amplifier voltage and a power associated with the second tributary.

2. The system of claim 1, wherein the automatic gain control loop comprises an analog automatic gain control loop.

3. The system of claim 1, wherein the automatic gain control loop is implemented in hardware and comprises a first detector operable to measure a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic operable to compare the first detected voltage and the second detected voltage and a reference voltage, and a loop filter operable to integrate a voltage difference to provide the offset gain control voltage.

4. The system of claim 1, wherein the automatic gain control loop is implemented in firmware and comprises a first detector operable for measuring a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic operable for comparing the first detected voltage and the second detected voltage to a reference voltage, and a loop filter operable for integrating a voltage difference to provide the offset gain control voltage.

5. The system of claim 1, wherein the automatic gain control loop comprises a first digital power detector coupled to the first analog-to-digital converter and operable for measuring a detected power of the first tributary and a second digital power detector coupled to the second analog-to-digital converter and operable for measuring a detected power of the second tributary.

6. The system of claim 1, wherein the automatic gain control loop is configured to be selectively operated in a common mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are gain balanced and a normal mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are not gain balanced.

7. A receiver comprising: a first transimpedance amplifier coupled to a first analog-to-digital converter configured to form a first tributary; a second transimpedance amplifier coupled to a second analog-to-digital converter configured to form a second tributary; and an automatic gain control loop coupled to both the first transimpedance amplifier and the second transimpedance amplifier, wherein the automatic gain control loop is operable to provide an offset gain control voltage to gain balance a transimpedance amplifier voltage and a power associated with the first tributary and a transimpedance amplifier voltage and a power associated with the second tributary.

8. The receiver of claim 7, wherein the automatic gain control loop comprises an analog automatic gain control loop.

9. The receiver of claim 7, wherein the automatic gain control loop is implemented in hardware and comprises a first detector configured to measure a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic configured to compare the first detected voltage and the second detected voltage and a reference voltage, and a loop filter configured to integrate a voltage difference to provide the offset gain control voltage.

10. The receiver of claim 7, wherein the automatic gain control loop is implemented in firmware and comprises a first detector configured to measure a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic configured to compare the first detected voltage and the second detected voltage to a reference voltage, and a loop filter configured to integrate a voltage difference to provide the offset gain control voltage.

11. The receiver of claim 7, wherein the automatic gain control loop comprises a first digital power detector coupled to the first analog-to-digital converter and configured to measure a detected power of the first tributary and a second digital power detector coupled to the second analog-to-digital converter and configured to measure a detected power of the second tributary.

12. The receiver of claim 7, wherein the automatic gain control loop is configured to be selectively operated in a common mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are gain balanced and a normal mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are not gain balanced.

13. An automatic gain control method for a receiver, the method comprising: providing an automatic gain control loop adapted to be coupled to both a first transimpedance amplifier coupled to a first analog-to-digital converter forming a first tributary and a second transimpedance amplifier coupled to a second analog-to-digital converter forming a second tributary; and using the automatic gain control loop, providing an offset gain control voltage to gain balance a transimpedance amplifier voltage and a power associated with the first tributary and a transimpedance amplifier voltage and a power associated with the second tributary.

14. The method of claim 13, wherein the automatic gain control loop comprises an analog automatic gain control loop.

15. The method of claim 13, wherein the automatic gain control loop is implemented in hardware and comprises a first detector operable for measuring a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic operable for comparing the first detected voltage and the second detected voltage and a reference voltage, and a loop filter operable for integrating a voltage difference to provide the offset gain control voltage.

16. The method of claim 13, wherein the automatic gain control loop is implemented in firmware and comprises a first detector operable for measuring a first detected voltage associated with the first tributary and a second detected voltage associated with the second tributary, logic operable for comparing the first detected voltage and the second detected voltage to a reference voltage, and a loop filter operable for integrating a voltage difference to provide the offset gain control voltage.

17. The method of claim 13, wherein the automatic gain control loop comprises a first digital power detector coupled to the first analog-to-digital converter and operable for measuring a detected power of the first tributary and a second digital power detector coupled to the second analog-to-digital converter and operable for measuring a detected power of the second tributary.

18. The method of claim 13, wherein the automatic gain control loop is configured to be selectively operated in a common mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are gain balanced and a normal mode in which the transimpedance amplifier voltage and the power associated with the first tributary and the transimpedance amplifier voltage and the power associated with the second tributary are not gain balanced.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated and described herein with reference to the various drawings, in which like reference numbers are used to denote like system components/method steps, as appropriate, and in which:

(2) FIG. 1 is a plot illustrating that the powers on the I and Q axes are constant independent of for symmetrical constellations;

(3) FIG. 2 is a schematic diagram illustrating a conventional per channel AGC loop configuration, with a dedicated AGC loop for each TIA and ADC;

(4) FIG. 3 is a plot illustrating that the powers on the I and Q axes are not constant independent of for asymmetrical constellations;

(5) FIG. 4 is a schematic diagram illustrating a conventional digital per channel or common AGC loop configuration, with a dedicated or common AGC loop for each or all TIA(s) and ADC(s);

(6) FIG. 5 is a plot illustrating that the XI.Math.XQ and YI.Math.YQ powers fluctuate in complement to each other as the IF between a Tx and a Rx changes, thus the powers XI+XQ and YI+YQ are constant accordingly;

(7) FIG. 6 is a schematic diagram illustrating one exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating an IQ gain balancing adjustment;

(8) FIG. 7 is a plot illustrating why IQ gain balancing is required;

(9) FIG. 8 is a schematic diagram illustrating another exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a hardware-based IQ gain balancing loop;

(10) FIG. 9 is a schematic diagram illustrating a further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a firmware-based IQ gain balancing loop;

(11) FIG. 10 is a schematic diagram illustrating a still further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a firmware-based IQ gain balancing loop incorporating a post-ADC digital power detector instead of the analog power detector of the TIA;

(12) FIG. 11 is a plot illustrating that before the IQ gain balancing loop is initiated, the power of XI, XQ, YI, and YQ are all different, even though PXI+PXQ=target and PYI+PYQ=target, and, with the IQ gain balancing loop running, the power of all channels converge to a target;

(13) FIG. 12 is a schematic diagram illustrating a still further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a hardware-based IQ gain balancing loop, operable in both normal and common modes; and

(14) FIG. 13 is a schematic diagram illustrating a still further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a firmware-based IQ gain balancing loop incorporating a post-ADC digital power detector instead of the analog power detector of the TIA, operable in both normal and common modes.

DESCRIPTION OF EMBODIMENTS

(15) As illustrated in FIG. 5, the XI.Math.XQ and YI.Math.YQ powers fluctuate in complement to each other as the IF between the Tx and the Rx changes. The powers XI+XQ and YI+YQ are constant accordingly, as indicated by the dashed line.

(16) Referring now specifically to FIG. 6, in one exemplary embodiment, the receiver 10 includes a pair of TIAs 12 that utilize a common analog AGC loop 40 to control the gain of the I and Q channels that locks the sum of the I and Q RF powers to the AGC loop 40 to a constant value; that is:
error=VREFVDET_IVDET_Q.fwdarw.0(5)
DET 42 is the power detector of the TIA RF output, VDET_ch 44 is the detector output voltage, VREF 46 is the reference voltage of the AGC loop 40, 48 is the voltage summing (error=VREFV DET_IVDET_Q), VGC_ch 50 is the TIA gain control voltage, the loop filter 52 is the integrator loop (VGC_I=K.sub.LFerror dt, VGC_Q=VGC_I+VGC_off), and P.sub.ADC,ch 54 is the RF power at the ADC input.

(17) The error voltage is integrated by the loop filter 52; its output controls the TIA gain of both the I-axis and the Q-axis. Since the receiver (TZ) gain as a function of VGC is not the same from one TIA 12 to another, a DC offset (VGC_off) 56 is added to one of the two channels for IQ gain balancing. The method to determine and set VGC_off 56 to balance the receiver gain between the I and Q-axis per polarization is described herein below.

(18) FIG. 7 illustrates a sample receiver optical-electrical conversion gain (OE-CG) per tributary. For a single gain setting for XI:XQ or YI:YQ, each tributary would have a different OE-CG. In order to preserve the power distinction of BPSK/4ASK signals and the power ratio of asymmetrical modulated signals, the OE-CG of each IQ pair should be the same, to the extent possible.

(19) Referring now specifically to FIG. 8, in another exemplary embodiment, a TIA implementation is illustrated with a common AGC loop 40 and a hardware-based IQ gain balancing loop 60. The gain balancing of the I-axis and the Q-axis is performed by a slow loop. Its function is:
VGC_off(t)=K.sub.GBVDET dt, where K.sub.GB=gain balancing loop filter gain(6)
VDET=VDET_IVDET_Q(7)
The IQ gain balancing loop 60 forces VDET.fwdarw.0. Because the TIA 12 must operate when IF0, the time constant of the IQ gain balancing loop filter 52 has to be slow to generate a stable VGC_off 56 when VDET_I 44 and VDET_Q 44 are fluctuating at a slow rate. The selected value for the gain balancing loop for is 40 sec, for example.

(20) Referring now specifically to FIG. 9, in a further exemplary embodiment, a TIA implementation is illustrated with a common AGC loop 40 and a firmware-based IQ gain balancing loop 70 to balance the TIA gain of the I-axis and the Q-axis. Firmware reads VDET_I 44 and VDET_Q 44 via the TIA's ADC-SPI interface (not illustrated), subtracts for the difference VDET and integrates VDET. The output of the integrated value drives an offset gain control voltage of the Q-axis via the TIA's SPI-DAC interface (not illustrated). Again, DET 42 is the power detector of the TIA RF output, VDET_ch 44 is the detector output voltage, VREF 46 is the reference voltage of the AGC loop 40, 48 is the voltage summing (error=VREFV DET_IVDET_Q), VGC_ch 50 is the TIA gain control voltage, the loop filter 52 is the integrator loop (VGC_I=K.sub.LFerror dt, VGC_Q=VGC_I+VGC_off, K.sub.LF=loop filter gain constant), and P.sub.ADC,ch 54 is the RF power at the ADC input.

(21) Referring now specifically to FIG. 10, in a still further exemplary embodiment, a TIA implementation is illustrated with a common AGC loop 40 and an alternative firmware-based IQ gain balancing loop 70 to balance the TIA gain of the I-axis and the Q-axis. Here, the IQ gain balancing loop 70 makes use of a more accurate post-ADC digital power detector 80 instead of the analog power detector of the TIA 12.

(22) FIG. 11 illustrates that before the IQ gain balancing loop is initiated at 13 hr:19 min, the power of XI, XQ, YI, and YQ are all different, even though PXI+PXQ=target and PYI+PYQ=target. With the IQ gain balancing loop running, the power of all channels converge to the target 16130. It is a slow loop and takes 90 sec for 90% convergence, for example.

(23) FIG. 12 is a schematic diagram illustrating a still further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a hardware-based IQ gain balancing loop, operable in both normal and common modes.

(24) FIG. 13 is a schematic diagram illustrating a still further exemplary embodiment of the analog AGC loop implementation of the present disclosure, incorporating a common AGC loop and a firmware-based IQ gain balancing loop incorporating a post-ADC digital power detector instead of the analog power detector of the TIA, operable in both normal and common modes.

(25) Thus, the present disclosure provides a multi-channel (dual or quad) TIA that has an integrated AGC function to provide a constant total I and Q power to the ADC (P.sub.(ADC,Total)=P.sub.(ADC,I)+P.sub.(ADC,Q)) per polarization for a single-axis modulated signal, e.g., BPSK, 4ASK, or for an otherwise asymmetrically modulated signal. The integrated AGC includes a function to balance the receiver's I and Q gain to preserve the signal's asymmetrical I-Q power ratio. The IQ gain balancing function can be implemented in hardware or in firmware.

(26) The multi-channel (dual or quad) TIA has the capability to switch between a dedicated AGC per tributary or a common AGC per pair of tributaries. This is a likely solution when the IQ gain balancing loop is a very slow loop, as it is more suitable to be implemented in firmware without adding more risk and complexity to the TIA design.

(27) When the TIA chip is set to NORMAL mode, i.e., one dedicated AGC per tributary, each TIA gain will be controlled by its associated AGC to output a constant RF power to the ADC. Each tributary output power is set by its reference voltage, VREF_I and VREF_Q. When the TIA chip is set to COMMON mode, i.e., one common AGC per pair of tributaries (I and Q), the gain of the pair of TIAs will be controlled by a common AGC to output a constant total I and Q power to the ADC (P.sub.ADC,Total)=P.sub.(ADC,I)+P.sub.(ADC,Q)). The I-axis AGC is used as the common AGC, for example. The total I and Q output power is set by VREF_I. The I-axis TIA is controlled directly by the output of the AGC loop. To balance the I and Q gain, a facility is provided to add a DC offset voltage (VGC.sub.off) to the Q-axis TIA gain. The algorithm of IQ gain balancing can again be implemented either in hardware (slide-7) or in firmware (slide-8,9) as shown.

(28) In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

(29) By way of example, and not limitation, such computer-readable storage media can include random-access memory (RAM), read-only memory (ROM), electrically-erasable-programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

(30) Instructions may be executed by one or more processors, such as one or more DSPs, general purpose microprocessors, ASICSs, FPGAs, complex programmable logic devices (CPLDs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term processor, as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules. Also, the techniques could be fully implemented in one or more circuits or logic elements.

(31) The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

(32) Although the present disclosure is illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those of ordinary skill in the art that other embodiments and examples may perform similar functions and/or achieve like results. All such equivalent embodiments and examples are within the spirit and scope of the present disclosure, are contemplated thereby, and are intended to be covered by the following non-limiting claims for all purposes.