VOLTAGE REGULATOR

Abstract

A voltage regulator is arranged to receive an input voltage (V.sub.in) and produce a regulated output voltage (V.sub.out) and comprises: a current source transistor (M.sub.source) and a current sink transistor (M.sub.sink) arranged to provide the output voltage at a node therebetween; a first error amplifier; and a second error amplifier. The first error amplifier is arranged to apply a first control voltage to the gate terminal of the current source transistor, wherein the first control voltage is dependent on the difference between the feedback voltage (V.sub.fb) and the reference voltage (V.sub.ref). The second error amplifier arranged in parallel to the first error amplifier, the second error amplifier being arranged to apply a second control voltage to the gate terminal of the current sink transistor, wherein the second control voltage is dependent on the difference between the feedback voltage and the reference voltage. The feedback voltage is derived from the output voltage.

Claims

1. A voltage regulator arranged to receive an input voltage and produce a regulated output voltage, the voltage regulator comprising: a current source transistor and a current sink transistor arranged to provide the output voltage at a node therebetween; a first error amplifier arranged to compare a feedback voltage to a reference voltage and apply a first control voltage to a gate terminal of the current source transistor, wherein said first control voltage is dependent on a difference between the feedback voltage and the reference voltage; a second error amplifier arranged in parallel to the first error amplifier, said second error amplifier being arranged to compare the feedback voltage to the reference voltage and apply a second control voltage to a gate terminal of the current sink transistor, wherein said second control voltage is dependent on a difference between the feedback voltage and the reference voltage; wherein said feedback voltage is derived from the output voltage and wherein the first error amplifier is arranged to vary a bias current provided to the second error amplifier.

2. The voltage regulator as claimed in claim 1, comprising a feedback network arranged to provide the feedback voltage which depends on the output voltage.

3. The voltage regulator as claimed in claim 2, wherein the feedback network comprises a ladder of diode-connected metal-oxide-semiconductor field-effect-transistors.

4. The voltage regulator as claimed in claim 1, wherein the current source transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor.

5. The voltage regulator as claimed in claim 1, wherein the current sink transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor.

6. The voltage regulator as claimed in claim 1, wherein the source terminal of the current source transistor is connected to the input voltage.

7. The voltage regulator as claimed in claim 1, wherein the source terminal of the current sink transistor is connected to ground.

8. The voltage regulator as claimed in claim 1, wherein the respective drain terminals of the current source transistor and the current sink transistor are connected together at the node arranged to provide the output voltage.

9. The voltage regulator as claimed in claim 1, wherein the first error amplifier comprises first and second differential n-channel metal-oxide-semiconductor field-effect-transistors, arranged such that the gate terminal of the first differential n-channel metal-oxide-semiconductor field-effect-transistor is connected to the feedback voltage, and the gate terminal of the second differential n-channel metal-oxide-semiconductor field-effect-transistor is connected to the reference voltage.

10. The voltage regulator as claimed in claim 1, wherein the first error amplifier comprises a constant current source.

11. The voltage regulator as claimed in claim 9, wherein the first error amplifier comprises a constant current source connected to the source terminals of said first and second differential n-channel metal-oxide-semiconductor field-effect-transistors.

12. The voltage regulator as claimed in claim 9, wherein the first error amplifier comprises a first current mirror comprising first and second mirror p-channel metal-oxide-semiconductor field-effect-transistors arranged such that: the gate and drain terminals of the first mirror p-channel metal-oxide-semiconductor field-effect-transistor are connected to the gate terminal of the second mirror p-channel metal-oxide-semiconductor field-effect-transistor and the drain terminal of the first differential n-channel metal-oxide-semiconductor field-effect-transistor; the drain terminal of the second mirror p-channel metal-oxide-semiconductor field-effect-transistor is connected to the drain terminal of the second differential n-channel metal-oxide-semiconductor field-effect-transistor; and the source terminals of the first and second mirror p-channel metal-oxide-semiconductor field-effect-transistors are connected to the input voltage.

13. The voltage regulator as claimed in claim 12, wherein the second error amplifier comprises a tail transistor arranged such that its drain terminal is connected to the respective source terminals of the first and second differential p-channel metal-oxide-semiconductor field-effect-transistors and its gate terminal is connected to the gate and drain terminals of the first mirror p-channel metal-oxide-semiconductor field-effect-transistor.

14. The voltage regulator as claimed in claim 13, wherein the tail transistor is a p-channel metal-oxide-semiconductor field-effect-transistor.

15. (canceled)

16. The voltage regulator as claimed in claim 1, wherein the second error amplifier comprises first and second differential p-channel metal-oxide-semiconductor field-effect-transistors, arranged such that the gate terminal of the first differential p-channel metal-oxide-semiconductor field-effect-transistor is connected to the feedback voltage, and the gate terminal of the second differential p-channel metal-oxide-semiconductor field-effect-transistor is connected to the reference voltage.

17. The voltage regulator as claimed in claim 16, wherein the second error amplifier further comprises a second current mirror comprising first and second mirror n-channel metal-oxide-semiconductor field-effect-transistors arranged such that: the gate and drain terminals of the first mirror n-channel metal-oxide-semiconductor field-effect-transistor are connected to the gate terminal of the second mirror n-channel metal-oxide-semiconductor field-effect-transistor and the drain terminal of the first differential p-channel metal-oxide-semiconductor field-effect-transistor; the drain terminal of the second mirror n-channel metal-oxide-semiconductor field-effect-transistor is connected to the drain terminal of the second differential p-channel metal-oxide-semiconductor field-effect-transistor; and the source terminals of the first and second mirror n-channel metal-oxide-semiconductor field-effect-transistors are connected to ground.

Description

[0029] Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0030] FIG. 1 is a circuit diagram of a low-dropout voltage regulator in accordance with an embodiment of the present invention;

[0031] FIG. 2 is a simulated graph illustrating the behaviour of the circuit shown in FIG. 1 when sinking current; and

[0032] FIG. 3 is a simulated graph further illustrating the behaviour across a range of values of a current being sinked into the circuit shown in FIG. 1.

[0033] FIG. 1 shows a low-dropout (LDO) voltage regulator 2 in accordance with an embodiment of the present invention. While it will be appreciated that the LDO voltage regulator 2 itself comprises the components in the on-chip domain 4, FIG. 1 also shows the bond wire domain 6 and the off-chip domain 8. The LDO voltage regulator 2 comprises: a first error amplifier 10; a second error amplifier 12; a feedback network 14; a current source transistor M.sub.source; and a current sink transistor M.sub.sink. The LDO voltage regulator 2 is arranged to receive an input voltage V.sub.in and generate a regulated output voltage V.sub.out.

[0034] The feedback network 14 may comprise a ladder of diode-connected pMOS transistors arranged to generate a feedback voltage V.sub.fb which is input to the first and second error amplifiers 10, 12. This feedback voltage V.sub.fb is derived from the output voltage V.sub.out and is compared to a reference voltage \f.sub.ref via each of the error amplifiers 10, 12. It will be appreciated that while the two error amplifiers 10, 12 could utilise different local feedback voltages each derived from the output voltage V.sub.out, this may lead to undesirable mismatch errors together with an increase in circuit area and power consumption and so it is preferred that each error amplifier 10, 12 receives the same feedback voltage V.sub.fb. It is also preferred that the reference voltage used by each error amplifier 10, 12 is the same for analogous reasons.

[0035] The first error amplifier 10 comprises a differential pair of nMOS transistors M.sub.1, M.sub.2 and a current mirror load constructed from two pMOS transistors M.sub.3, M.sub.4. The differential pair transistors M.sub.1, M.sub.2 are arranged such that their respective source terminals are connected to ground 26 via a current source 16 which provides the differential pair with a constant bias current. The gate terminal of the first nMOS differential pair transistor M.sub.1 is connected to the output of the feedback network 14 such that the feedback voltage V.sub.fb is applied to the gate terminal of M.sub.1. The gate terminal of the second nMOS differential pair transistor M.sub.2 is connected to the reference voltage V.sub.ref. The drain terminal of M.sub.1 is connected at a node 18 to the drain terminal of M.sub.3 and the gate terminals of both M.sub.3 and M.sub.4. The drain terminal of M.sub.2 is connected at a node 20 to the drain terminal of M.sub.4 and to the gate terminal of the current source transistor M.sub.source. The respective source terminals of the pMOS mirror transistors M.sub.3, M.sub.4 are connected to the input voltage V.sub.in.

[0036] The second error amplifier 12 comprises a differential pair of pMOS transistors M.sub.5, M.sub.6 and a current mirror load comprising a pair of nMOS mirror transistors M.sub.7, M.sub.8. The gate terminal of the first pMOS differential transistor M.sub.5 is connected to the output of the feedback network 14 such that the feedback voltage V.sub.fb is applied to the gate terminal of M.sub.5 while the gate terminal of M.sub.6 is connected to the reference voltage V.sub.ref. The drain terminal of M.sub.5 is connected to the drain terminal of M.sub.7 and the respective gate terminals of M.sub.7 and M.sub.8. The drain terminal of M.sub.6 is connected to the drain terminal of M.sub.8 and to the gate terminal of the current sink transistor M.sub.sink. The respective source terminals of M.sub.7, M.sub.8, M.sub.sink are connected to ground 26.

[0037] The respective source terminals of the pMOS differential pair transistors M.sub.5, M.sub.6 are connected to the drain terminal of a pMOS tail transistor M.sub.9, which has its respective source terminal connected to the input voltage V.sub.in and its gate terminal connected to the node 18 and thus the respective drain terminals of M.sub.1 and M.sub.3 within the first error amplifier 10.

[0038] While not a part of the voltage regulator 2, the inductance and resistance of the bond wire 6 are depicted in FIG. 1 as L.sub.bond and R.sub.bond respectively. A load capacitance C.sub.load and equivalent series resistance R.sub.ESR are shown connected to the output of the voltage regulator 2, i.e. the output voltage V.sub.ont is applied across these in the off-chip domain 8.

[0039] The technical operation of the LDO voltage regulator 2 shown in FIG. 1 will now be described. When sourcing load current in normal use, the conductance of the source transistor M.sub.source is high enough that current flows from the input voltage V.sub.in to the output of the LDO voltage regulator 2. The feedback network 14 varies the feedback voltage V.sub.fb in order to regulate the output voltage V.sub.out, assuming that each loop including the error amplifier 10, 12, the corresponding pass-FET M.sub.source, M.sub.sink, and the feedback network 14 provides sufficient gain, in a manner known per se.

[0040] FIG. 2 illustrates the behaviour of a number of voltages and currents in the LDO voltage regulator 2 in response to a load current I.sub.sink (shown in FIG. 1 as a current source 22) being abruptly sunk into the output of the LDO voltage regulator 2. Assuming that the abrupt sinking occurs a time t.sub.1, the output voltage V.sub.ont is seen thereafter to increase linearly due to the charging of the load capacitance (i.e. Vout/T=Isink/Cload). At the time of the abrupt change in current, the capacitor is the lowest impedance path and thus the path along which the current is sinked. This results in an increase of the feedback voltage V.sub.fb which subsequently deviates from the reference voltage V.sub.ref which, due to the behaviour of the differential pair comprising M.sub.1 and M.sub.2, decreases the voltage at the node 18 between the respective drain terminals of M.sub.1 and M.sub.3. The decreased voltage at this node 18 increases the bias current provided to the second error amplifier 12 due to the increased conductance of the pMOS tail transistor M.sub.9. The current I.sub.cload through the load capacitance C.sub.load undergoes a sharp increase in response to the increased current I.sub.sink sunk into the output, but eventually reduces to zero when the feedback voltage V.sub.fb reaches its final value.

[0041] This deviation of the feedback voltage V.sub.fb from the reference voltage V.sub.ref also causes the voltage at the node 24 between the respective drain terminals of M.sub.6 and M.sub.8 to increase which, due to its connection to the gate terminal of the current sinking transistor M.sub.sink, increases the conductivity of the sinking transistor M.sub.sink thus providing a direct path to ground 26 from the current source 22, i.e. the current I.sub.Msink through the sinking transistor M.sub.sink increases. This prevents the charging of the load capacitance C.sub.load and as a result limits the increase in the output voltage V.sub.out due to the current being sunk into the output of the LDO voltage regulator 2.

[0042] It will be appreciated that the second error amplifier 12 provides a parallel feedback loop that only operates when a current is sunk into the output of the LDO voltage regulator 2, allowing the LDO voltage regulator 2 to continue regulating the output voltage V.sub.out even under such circumstances while requiring very low bias current during normal operation (i.e. current sourcing operation) due to the connection between the pMOS tail transistor M.sub.9 and the node 18 in the first error amplifier 10.

[0043] FIG. 3 illustrates the behaviour of a number of voltages and currents in the LDO voltage regulator 2 in response to different values of load current I.sub.sink (shown in FIG. 1 as a current source 22) being sunk into the output of the LDO voltage regulator 2. The various plots shown in FIG. 3 are a function of the current I.sub.sink on a logarithmic scale. The uppermost plot simply shows a plot of the load current I.sub.sink on a linear scale (in microamps).

[0044] The second plot shows the voltage at the node 18, the third plot shows the current I.sub.M9 through the pMOS tail transistor M.sub.9, the fourth plot shows the current I.sub.Msource through M.sub.source, and the fifth plot shows the output voltage Vout, and all four plots are shown as a function of the current I.sub.sink. As the sinking current I.sub.sink increases, the current I.sub.Msource through M.sub.source decreases non-linearly until a particular threshold current I.sub.threshold, after which M.sub.source is fully disabled and the current I.sub.Msource falls to 0 A. When the current I.sub.sink sinked into the output of the LDO voltage regulator 2 exceeds this value (i.e. I.sub.sink is larger than the threshold current I.sub.threshold), the feedback voltage V.sub.fb increases due to the capacitor C.sub.load and thus deviates from the reference voltage V.sub.ref as described previously. This decreases the voltage at the node 18 between the respective drain terminals of M.sub.1 and M.sub.3 which increases the current I.sub.M9 through the pMOS tail transistor M.sub.9. This increase in the current I.sub.M9 biases the second differential amplifier 12 which, due to the difference between the voltages V.sub.fb and V.sub.ref applied to the respective gate terminals of M.sub.5 and M.sub.6, causes M.sub.sink to conduct and sink the current I.sub.sink as described previously. The increase in the conductivity of the sinking transistor M.sub.sink provides a direct path to ground 26 from the current source 22, which prevents the charging of the load capacitance C.sub.load and limits the increase in the output voltage V.sub.out due to the current being sunk into the output of the LDO voltage regulator 2.

[0045] Thus it will be seen that embodiments of the present invention provide an improved low-dropout voltage regulator that is arranged such that a current can be sunk from the output, for example when the regulator receives leakage current from another regulator. The current that can be sunk may be orders of magnitude greater than the quiescent current of the feedback path while maintaining the desired value of the regulated output voltage. It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.