Abstract
This disclosure relates to a synaptic component for a neural network having a layer of a semiconductor and a source electrode connected to the semiconducting layer and a drain electrode connected to the semiconducting layer, wherein the source electrode is spatially separated from the drain electrode, wherein the source electrode and the semiconducting layer form a Schottky diode, wherein the source electrode is separated from a first gate electrode by ferroelectric material. This disclosure further relates to a method for operating a synaptic component according to the disclosure in which the first Schottky diode is connected in reverse direction and an electric voltage is applied on the first gate electrode in a pulsed manner.
Claims
1. A synaptic component for a neural network, comprising: a layer of a semiconductor; a source electrode connected to the semiconducting layer; and a drain electrode connected to the semiconducting layer, wherein the source electrode is spatially separated from the drain electrode, wherein the source electrode and the semiconducting layer form a first Schottky diode, and wherein the source electrode is separated from a first gate electrode by ferroelectric material.
2. The synaptic component according to claim 1, wherein the drain electrode forms with the semiconducting layer a second Schottky diode.
3. The synaptic component according to claim 1, wherein the drain electrode is separated from a second gate electrode by ferroelectric material, and wherein the first gate electrode is spatially separated from the second gate electrode.
4. The synaptic component according to claim 3, wherein the source electrode and the drain electrode are located on one side of the semiconducting layer and/or at opposite ends of the semiconducting layer.
5. The synaptic component according to claim 1, wherein the semiconducting layer is located above a substrate or in that the semiconducting layer is a substrate.
6. The synaptic component according to claim 1, wherein the semiconducting layer is a semiconductor heterostructure.
7. The synaptic component according to claim 1, wherein ferroelectric material is present as a layer which is at least partially located on the semiconducting layer.
8. The synaptic component according to claim 1, wherein ferroelectric material is present as a layer which is at least partially located on the source electrode and/or the drain electrode.
9. The synaptic component according to claim 8, wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
10. The synaptic component according to claim 1, wherein ferroelectric material is present as a layer and the first gate electrode and/or the second gate electrode are located on one side of the ferroelectric layer and the source electrode and/or the drain electrode are located on the opposite side of the ferroelectric layer.
11. The synaptic component according to claim 1, wherein the component is electrically connected to at least one further component in series or in parallel to form a crossbar structure.
12. The synaptic component according to claim 1, wherein the ferroelectric material is selected from: doped HfO2 ferroelectric, a perovskite ferroelectric, an organic ferroelectric.
13. The synaptic component according to claim 1, wherein the metal for a Schottky diode is selected from: Al, Ag, Au, Cu, Cr, Mo, Ni, Nb, Pt, Ti, Ni, TiN, TaN, or a metal semiconductor alloy such as silicides, germanides, metal-SiGeSn alloys.
14. The synaptic component according to claim 1, wherein the semiconducting layer is partially covered with a layer of electrically insulating material.
15. A neural network, comprising: the synaptic component according to claim 1; and a neuron electrically connected to the synaptic component.
16. A method of operating a synaptic component according claim 1, wherein the first Schottky diode is connected in reverse direction and an electric voltage is applied to the first gate electrode in a pulsed manner.
17. The synaptic component according to claim 7, wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
Description
[0034] The figures show
[0035] FIG. 1: Functional principle of a neural gate;
[0036] FIG. 2a: Configuration of a synapse;
[0037] FIG. 2b: Symbol representation of the synapse according to FIG. 2a;
[0038] FIG. 3: Configuration of a synapse;
[0039] FIG. 4a: Modulation of a Schottky diode by a positive gate voltage;
[0040] FIG. 4b: Modulation of a Schottky diode by a negative gate voltage;
[0041] FIG. 5a: Band model of a Schottky diode with positive gate voltage;
[0042] FIG. 5b: Band model of a Schottky diode with negative gate voltage;
[0043] FIG. 6a: Current-voltage curve;
[0044] FIG. 6b: Configuration of a synapse;
[0045] FIG. 7: Pulse-current graph;
[0046] FIG. 8a: Configuration for a plurality of synapses
[0047] FIG. 8b: Sectional view of FIG. 8a;
[0048] FIG. 9a: Configuration of a synapse;
[0049] FIG. 9b: Symbol representation of the synapse from FIG. 9a;
[0050] FIG. 10: Vertical arrangement of a synaptic element;
[0051] FIGS. 11a, b: Symbol representations of a neural element;
[0052] FIG. 12: Neural network;
[0053] FIG. 13: Real representation of a synapse;
[0054] FIG. 14: NAND gate;
[0055] FIG. 15: AND gate.
[0056] FIG. 1 shows the operating principle of a neural gate, which consists of several input synapses xi to x.sub.n and a neuron. The input signals of the synapses x.sub.i with the weights w.sub.i are integrated with the following function:
[00001]
[0057] S here is the integration over the input signals with the associated weights and 0 is an offset. The neural function ƒ(s) acts as a threshold function. Once S reaches a threshold value, the neuron with the function ƒ(s) is activated.
[0058] FIG. 2 shows a first configuration of a synapse. The synapse comprises a layer 101 consisting of a semiconductor. On the semiconducting layer 101, there are a source electrode 102 and a drain electrode 103. The two electrodes 102, 103 are spatially separated from each other. The two electrodes 102, 103 may be present adjacent to the end faces of the semiconducting layer 101. The two electrodes 102, 103 consist of metal. The two electrodes 102, 103 may be in the form of layers. An electric potential Vs may be applied to the source electrode 102. An electric potential V.sub.D may be applied to the drain electrode 103. The electric potential Vs is different from the electric potential V.sub.D.
[0059] The metal of the source electrode 102 and the semiconductor material of the semiconducting layer 101 are selected such that the junction between the source electrode 102 and the semiconducting layer 101 is a Schottky contact. Thus, there is a first Schottky diode formed by the source electrode 102 and the semiconducting layer 101.
[0060] The metal of the drain electrode 103 and the semiconductor material of the semiconducting layer 101 may be selected such that the junction between the drain electrode 103 and the semiconducting layer 101 is a Schottky contact. Thus, the drain electrode 103 and the semiconducting layer 101 may form a second Schottky diode.
[0061] In an equivalent circuit, the first Schottky diode and the second Schottky diode are connected “back-to-back”. A potential difference between the electrical potential Vs and the electrical potential V.sub.D therefore results in one Schottky diode being connected in the reverse direction and the other Schottky diode being connected in the forward direction.
[0062] An electric current can flow from the source electrode 102 to the drain electrode 103 due to the potential difference between the electric potential Vs and the electric potential V.sub.D. When an electric current flows from the source electrode 102 to the drain electrode 103, the electric current passes the first Schottky diode in the reverse direction and the second Schottky diode in the forward direction. Flowing of the electric current in reverse direction can be done by electrons tunneling through the junction of the first Schottky diode. If the electric current flows through the second Schottky diode in the forward direction, the second Schottky diode acts like an ohmic resistor.
[0063] Above the source electrode 102 there is a first ferroelectric layer 104a. The first ferroelectric layer 104a may cover a part of the source electrode 102. The first ferroelectric layer 104a overlaps with the semiconducting layer 101.
[0064] Above the drain electrode 103A there is a second ferroelectric layer 104b. The second ferroelectric layer 104b covers a part of the source electrode 103. The second ferroelectric layer 104b overlaps with the semiconducting layer 101.
[0065] A first electrode 105a is located on the first ferroelectric layer 104a. A second electrode 105b is located on the second ferroelectric layer 104b. Both electrodes 105a and 105b may consist of metal.
[0066] The synapse is configured such that an electric potential V.sub.g1 can be applied to the first electrode 105a. The Schottky barrier of the first Schottky diode may be modulated by an applied electrical potential V.sub.g1. The synapse is configured such that an electrical potential V.sub.g2 can be applied to the second electrode 105a. The Schottky barrier of the second Schottky diode may be modulated by an applied electrical potential V.sub.g2.
[0067] The first electric potential V.sub.g1 can be understood as a synaptic input signal within a neural network. The second electrical potential V.sub.g2 may be used to control weights within a neural network.
[0068] The ferroelectric layers 104a and/or 104b may overlap regions of the electrodes 102 and 103, applied on the semiconducting layer 101. Production may thus be facilitated. Also, the Schottky barriers of the first and second Schottky diodes can be modulated in a more controlled manner.
[0069] FIG. 2b shows an electrical symbol of the synapse shown in FIG. 2a with the source electrode S and the drain electrode D.
[0070] In FIG. 3, a second configuration of a synapse is shown that has only one continuous ferroelectric layer 204 instead of two ferroelectric layers 204a and 204b. In addition, the synapse shown here has a layer 201 that consists of a semiconductor. On the semiconducting layer 201, as in the case of FIG. 2a, there are a source electrode 202 and a drain electrode 203. The metal of the source electrode 202 and the semiconductor material of the semiconducting layer 201 are selected such that the junction between the source electrode 202 and the semiconducting layer 201 is a Schottky contact. The metal of the drain electrode 203 and the semiconductor material of the semiconducting layer 201 may be selected such that the junction between the drain electrode 203 and the semiconducting layer 201 is a Schottky contact. A first electrode 205a and a second electrode 205b are located on the ferroelectric layer 204. The electrical symbol of FIG. 2b may also represent the synapse shown in FIG. 3.
[0071] FIGS. 4a and 4b illustrate the modulation of the Schottky barriers by applying an electric potential V.sub.gi, wherein V.sub.gi with i = 1 or i =2. FIG. 4a illustrates the case where a voltage and/or electric potential applied to electrode 305 is positive. The polarization of the ferroelectric causes non-volatile memory effects so that electrons are present in the semiconductor layer 301. FIG. 4b illustrates the situation when a negative voltage V.sub.gi is applied to the first and/or second electrodes 305, respectively, wherein positive charges (holes) are present in the semiconductor layer 301 due to polarization-induced non-volatile memory effects. Consequently, the thickness of a Schottky barrier can be modulated by applying potentials V.sub.gi. This affects the flow of electrical tunnel currents.
[0072] FIG. 5 illustrates, using the band model, a modulation of a Schottky barrier from the metal layer 302 shown in the figure to the n-type doped semiconducting layer 301. When a positive voltage V.sub.gi is applied, as shown in FIG. 4a, more electrons are generated at the metal-semiconductor interface. The band curvature (dashed line) is enhanced. A smaller Schottky barrier results. This causes a higher tunnel current density along the arrow, which can be formulated as follows:
[00002]
[0073] Here ∅.sub.bn is the height of the Schottky barrier for the electrons. q is the charge of the electrons. N.sub.D is the doping concentration at the surface of the semiconductor 301.
[0074] If the voltage V.sub.gi shown in FIG. 4b is negative, the depletion causes a smaller N.sub.D and thus a wider Schottky barrier. A smaller current density along the arrow is the result. Thus, by modulating the multidomain polarization of the ferroelectric, the doping concentration in the metal-semiconductor interface can be regulated and hence the conductivity of the Schottky diode.
[0075] For a p-type doped semiconductor, the polarization and bias points in the opposite direction. The Schottky barrier is ∅.sub.bp.Math.
[0076] FIG. 6a presents an example of a measurement of an electric current I.sub.D as a function of V.sub.g1 from a source electrode 402 to a drain electrode 403. A potential of -0.5 volts was applied to the drain electrode. The solid line shows the measurement curves determined at a voltage V.sub.g2 = -1 V. The dashed line shows the measurement curves determined at a voltage V.sub.g2 = +1 V. The current-voltage characteristic I.sub.d — V.sub.g1 in FIG. 6a shows a counterclockwise hysteresis. This is typical for ferroelectric materials. Thus, a memory effect desired for a synapse is achieved by the ferroelectric material. By changing the voltage V.sub.g2, the initial current is also influenced. This demonstrates the weight function of V.sub.g2 of a synapse.
[0077] The measurement curves shown in FIG. 6a were performed using the component shown in FIG. 6b. A thin p-doped silicon layer is separated from a Si substrate by an insulating layer. This is called silicon-on-insulator and abbreviated SOI. The insulating layer is formed by “buried silicon oxide”, which is also called BOX. The source electrode 402 and the drain electrode 403 formed by monocrystalline NiSi.sub.2. The layers 402 and 403 are deposited on the thin p-doped silicon layer 401 by silicidation on very thin Ni. The layer 401 is 55 nm thick and is low p-doped. HfZrO was deposited as a ferroelectric layer 404 by atomic layer deposition (ALD). The thickness of the ferroelectric layer 404 may be 3 to 30 nm. The first electrode 405a and the second electrode 405b are produced from TiN. The first electrode 405a and the second electrode 405b serve as gate electrodes.
[0078] FIG. 7 shows an example of the measured synaptic characteristic of the element from FIG. 6 under the influence of a pulsed signal at the first gate, i.e. at the first gate electrode 405a. The current ID is plotted against the number of pulses PN. Thus, a voltage V.sub.g1 was applied to the first gate electrode in a pulsed manner. As indicated in FIG. 7, a long term potentiation (LTP) is generated by positive pulsed signals. A long-term depression (LTD) will be generated by negatively pulsed signals.
[0079] FIGS. 8a and 8b show several synapses with a crossbar structure. A cross-sectional view from A to A′ from FIG. 8a is shown in FIG. 8b. Two Schottky diodes of a synapse have a common semiconducting layer 501. A metal layer 502a of the first Schottky diode serves as a source electrode. A metal layer 502b serves as drain electrode. For producing, an electrically insulating layer 505 was first produced on the semiconducting layer in such a way that two accesses to the semiconducting layer remain. Subsequently, the two layers 502a and 502b were produced in such a way that they are electrically separated from each other. Then, the shown ferroelectric layers 502a and 502b with the gate electrodes 504a and 504b were produced. Advantageously, conventional producing techniques can be used to produce a plurality of synapses in the form of a crossbar structure in a technically simple manner.
[0080] FIG. 9 shows an example of a synapse comprising a first Schottky diode. The Schottky diode comprises a drain electrode 602 consisting of metal. The drain electrode 602 consisting of metal is applied on a semiconductor layer 601. The first Schottky diode can be modulated through a ferroelectric layer 604 with a gate electrode 605 according to the invention by means of a voltage V.sub.g. A second Schottky diode with the semiconducting layer 601 and the drain electrode 603 consisting of metal may be present. This can be operated with a bias voltage V.sub.D in the flow direction. However, the semiconducting layer 601 and the drain electrode 603 consisting of metal need not be selected such that a second Schottky diode is present. Instead, the semiconducting layer 601 and the drain electrode 603 consisting of metal may be a ohmic contact.
[0081] The first Schottky diode 602, 601 is operated under a reverse bias voltage. This synaptic element operates like a single gate transistor, which can be represented by the symbol of FIG. 9b.
[0082] FIG. 10 shows a synaptic element in a vertical arrangement. A layer 701 consisting of metal may serve as a substrate. However, the layer 701 consisting of metal can also be applied on a substrate. The layer 701 consisting of metal serves as a drain electrode. The layer 701 consisting of metal is therefore configured such that it can be connected to a voltage V.sub.D. A semiconducting layer 702 is applied on the layer 701 consisting of metal. The layer 701 consisting of metal and the semiconducting layer 702 may be a Schottky diode. On the semiconducting layer an insulator layer 703a, 703b has been applied on in such a way that an access to the semiconducting layer 702 remains on the upper side. The access may also have been created subsequently after deposition of the insulating layer 703a, 703b, such as by etching. A metallic layer 704 was subsequently deposited on the upper side. This contacts the semiconducting layer 702 through the access. The metallic layer 704 serves as a source electrode. It can therefore be connected to a voltage Vs. The metallic layer 704 and the semiconducting layer 702 form a Schottky diode. A ferroelectric layer 705 was deposited on the metallic layer 704. A metallic layer 706 was deposited on the ferroelectric layer 705. The metallic layer 706 serves as a gate electrode. It can therefore be connected to a voltage V.sub.G.
[0083] The structure shown in the FIG. 10 can be rotated by 180°. This structure shown in FIG. 10 is C2 rotation invariant.
[0084] FIGS. 11a and 11b symbolize a neural element with a synapse according to the invention, wherein a transistor and a resistor are present. The transistor may be either a dual-gate transistor 801 or a single-gate transistor 803. These transistors represent a synaptic element. The resistors 802 and 804 act as pull-up / pull-down resistors. By adjusting the conductance of the resistors, the activation of a neuron can be adjusted.
[0085] FIG. 12 illustrates a neural network with multiple synapses according to the invention and with conventional CMOS neurons. The synapses are shown in transistor representation Xi, Wi, ..., X.sub.n, W.sub.n on the left. A conventional neural element is shown on the right. The synapse can be a single-gate element as shown in FIG. 9 and FIG. 10. The producing of the synapses can be performed according to the CMOS neuron method to avoid the high-temperature treatment during the CMOS process. Synapses according to the invention may be combined with conventional neurons, which is illustrated by FIG. 12.
[0086] FIG. 13 sketches a synapse serving as a neuron-to-neuron connection. A signal 904 flows in one direction and that is from the presynaptic neuron 901 to the postsynaptic neuron 903. Also shown is a neuromodulator 902. The structure shown in FIG. 13 can be realized by the invention. The first gate (V.sub.g1) of FIGS. 2 and 3, formed by 105a/205a, may serve as a presynaptic neuron. The source electrode serves as a postsynaptic neuron. The second gate (V.sub.g2), formed by 105b/205b, serves as a neuromodulator. Thus, processing, learning and modulation functions can be realized simultaneously.
[0087] FIG. 14 illustrates how the component shown in FIG. 11a can be used as a two-input NAND gate.
[0088] FIG. 15 illustrates how a component according to FIG. 2b can be used as an AND gate, where I.sub.out is the current flowing out through D.
