Method for controlling an active pixel image sensor

Abstract

In a sensor comprising active pixels including a photodiode PHD, a memory node MN and a read-out node SN, the memory node being provided to hold the charge generated by the photodiode at the end of an integration period enabling integration in global-shutter mode and a correlated double sampling read-out, provision is made for the charge-storage capacity of the memory node to be at least N times higher than the charge-storage capacity of the photodiode (N being an integer higher than or equal to 2) and provision is made to carry out, in each integration and read-out cycle, during the integration duration Tint(i), N transfers Tri.sub.1, Tri.sub.2, Tri.sub.3 of charge from the photodiode to the memory node, the N transfers being equally distributed over the integration duration. The dynamic range of the sensor is improved under high light levels.

Claims

1. A method for taking images with an active-pixel sensor comprising at least one row of active pixels, in which the active pixels each comprise a photosensitive element, a read-out node and a memory node between the photosensitive element and the read-out node, and at least one first charge-transfer transistor between the photosensitive element and the memory node, one second charge-transfer transistor between the memory node and the read-out node, one transistor for resetting the read-out node, one follower transistor having its gate connected to the read-out node and one pixel-selection transistor that is connected between the source of the follower transistor and a column conductor, the image-taking method being such that each integration and read-out cycle comprises simultaneously initialization all the photosensitive elements by emptying charge from the photosensitive elements to a removal drain, integrating charge in the photosensitive elements during a common integration duration that starts at the end of the initialization of all the photosensitive elements, transferring charge from the memory node to the read-out node after the end of the common integration duration and, for each row in succession, reading out charge contained in the memory node via correlated double sampling, after the end of the common integration duration, wherein for each integration and read-out cycle, the image-taking method comprises, during the common integration duration, N regularly spaced transfers of charge from the photosensitive element to the memory node, N being an integer higher than or equal to 2, the photosensitive element accumulating charges throughout said integration duration, the memory node being configured to have a charge-storage capacity that is at least N times that of the photosensitive element, the N transfers being commanded by applying, at regular intervals during said common integration duration, N control pulses to the gate of the first transfer transistor, and the end of the Nth transfer setting the end of the common integration duration.

2. The method according to claim 1, wherein the read-out node has at least N times the charge-storage capacity of the photosensitive element.

3. The method according to claim 1, wherein N is equal to 2 or 3.

4. The method according to claim 2, wherein N is equal to 2 or 3.

5. The method of claim 4, wherein N is equal to 2.

6. The method of claim 4, wherein N is equal to 3.

7. The method of claim 3, wherein N is equal to 2.

8. The method of claim 3, wherein N is equal to 3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention are presented in the following description, with reference to the appended drawings, in which:

(2) FIG. 1 illustrates a general active-pixel structure to which the invention may be applied;

(3) FIG. 2 is a timing diagram of the control signals of an active pixel implementing an image-taking method according to the invention;

(4) FIGS. 3a to 3d show diagrams of the potentials in the structure of the pixel corresponding to various steps a) to d) of the integration duration; and

(5) FIGS. 4a to 4c show diagrams of the potentials in the structure of the pixel corresponding to various steps a) to c) of the read-out phase.

DETAILED DESCRIPTION

(6) Active pixels are produced in CMOS technology in a doped (for example p-doped) active semiconductor layer and in addition comprise photodiodes, which are in principle what are called pinned photodiodes, capacitive storage nodes and transistors. Embodiments thereof employ various CMOS technologies well known to those skilled in the art.

(7) In this description, a substrate with a p-doped active semiconductor layer, which substrate is biased to a zero reference potential and the circuits of which are supplied with a positive supply voltage denoted Vdd, is described. Those skilled in the art will know that it is necessary to invert the biases if a substrate with an n-doped active semiconductor layer is used.

(8) FIG. 1 is an equivalent circuit of a general structure of an active pixel comprising a photosensitive element, memory node and read-out node, to which structure the invention may be applied. In this example, the pixel PIX comprises a photodiode PHD, a first capacitive storage node called the memory node and referenced MN, a second capacitive storage node called the read-out node and referenced SN and at least 5 transistors that are:

(9) a first transfer transistor TRA.sub.1 (in practice a simple transistor gate), allowing charge to be transferred from the photodiode PHD to the memory node MN.

(10) a second transfer transistor TRA.sub.2 (in practice a simple transistor gate), allowing the memory node MN to be emptied into the read-out node.

(11) a transistor RST for resetting the read-out node SN, the source of which is electrically connected to the read-out node and the drain of which is connected to the positive supply voltage Vdd.

(12) a follower transistor SF, the gate of which is electrically connected to the read-out node SF, and the drain of which is biased to the supply voltage Vdd.

(13) a selection transistor SEL the gate of which receives a pixel-row selection command, the drain of which is electrically connected to the source of the follower transistor and the source of which is connected to a column conductor (Col) of the matrix array (the pixels being arrayed in a matrix of rows of pixels and columns of pixels), each column conductor being connected, at the bottom of the column, to a read-out circuit CL common to all the pixels of the column.

(14) It may comprise a sixth transistor AB, which allows the photodiode to be initialized, by allowing charge to be removed via its drain. One advantage of this sixth transistor is that it enables what is called an anti-blooming function, i.e. by biasing its gate to a set voltage under the threshold voltage of the transistor, it is possible to adjust the potential of the barrier of the semiconductor region under the gate to a level that allows excess charge to be removed from the photodiode via the drain of the transistor. When it is not provided, the photodiodes are initialized by activating, together in each pixel, the transistors TRA.sub.1, TRA.sub.2 and RST.

(15) It will be noted that certain transistors of the pixel may in practice be shared between at least two pixels, this possibly being advantageous when it is sought to produce small pixels with a high fill factor. For example, the follower transistor and the row-selection transistor are shared between two or four pixels of a given column. The photodiode-initialization transistor may also be shared between at least two pixels. The area of active layer required to control the pixels is thus decreased. The invention also applies to these shared-transistor pixel structures.

(16) The photodiode PHD is usually a pinned photodiode pinned to a voltage denoted V.sub.pin and defined by the technology, i.e. it includes, in the n-type diffusion region, a superficial p-type diffusion region and the superficial region is brought to the (zero) reference potential of the substrate.

(17) The read-out node SN, which is the equivalent of a capacitor, in practice consists of a floating n-doped semiconductor region. The charge-storage capacity of the read-out node at least corresponds to that of the photodiode. This capacity especially depends on the dopant concentration and the geometry of the memory node.

(18) The memory node MN is the equivalent of a capacitor for storing the charge generated and accumulated by the photodiode at the end of an integration period. In practice, this memory node is not a floating diffusion like the read-out node. Specifically, it must be possible to set its potential to a given level that must be higher than the photodiode voltage V.sub.pin, at least in the phase of transfer of charge from the photodiode to the memory node; and which must be lower than the supply voltage Vdd, at least in the phase of transfer of charge from the memory node to the read-out node. Its potential may therefore change, depending on the phase in question, i.e. depending on whether the memory node is the source or the destination of the transferred charge. But it may also be set. In the rest of the description, and in the drawings, it is this option (set potential) that is shown, for the sake of greater simplicity.

(19) For example, the memory node is a semiconductor region surmounted by a gate, and this gate is biased to a potential that allows a given potential level between the level V.sub.pin of the photodiode and Vdd to be applied to the memory-node semiconductor region under the gate. The charge-storage capacity under this gate then depends on the gate capacitance (and therefore its geometry), on the dopant concentration, etc. Other exemplary embodiments of memory nodes may be found in the prior art of what are called (at least) six-transistor pixels; for example, patent publications WO2006130443, U.S. Pat. No. 598,629 and FR2961631.

(20) In an example in which the substrate is p-type, these various transistors will be nMOS transistors, i.e. they will have source and drain regions that are n-type diffusions on either side of a p-type channel under the gate.

(21) The term transistor is used to facilitate comprehension in terms of an equivalent circuit diagram such as the diagram in FIG. 1. However, in the physical make-up of the pixel, these transistors are not necessarily all formed in the conventional way, independently of the other elements of the pixel, with a source region, a drain region, a channel region separating the source from the drain and an insulated gate on top of the channel. In the actual physical make-up of the pixel, certain transistors in fact essentially consist of an insulated gate to which a control potential may be applied. Thus, for example, the first transfer transistor TRA.sub.1 will consist of a simple transfer gate TRA.sub.1-g insulated from the substrate, surmounting a p-type channel region that is located between the n-type photodiode PHD region (source of TRA.sub.1) and the n-type region of the memory node NM (drain of TRA.sub.1). Likewise: the source of the second transfer transistor TRA.sub.2 may be the n-type region of the memory node NM, and the drain of this transistor TRA.sub.2 may be the n-type region of the read-out node SN. Furthermore, the source of the initialization transistor AB may be the n-type region of the photodiode that accumulates the charge generated by the light; and the source of the transistor RST may be the n-type region of the read-out node.

(22) The invention does not relate to a particular active-pixel technology, but indeed to the use of an active-pixel structure comprising a photodiode, a read-out node and a memory node between the photodiode and read-out node and, for example, to a structure such as described above, with or without an anti-blooming transistor AB. Furthermore, the active-pixel structure may comprise one or more transistors shared with at least one other pixel.

(23) In the invention, provision is made, as regards control of the active pixel, for the following two measures:

(24) the charge-storage capacity of the memory node is at least N times higher than the charge-storage capacity of the photodiode (N being an integer higher than or equal to 2); and

(25) charge is transferred N times from the photodiode to the memory node, these transfers being regularly spaced, during each integration duration of a periodic charge integration and read-out cycle.

(26) Thus, as illustrated by the timing diagram in FIG. 2 for an example in which N is equal to 3, after the start of the integration duration Tint(i) of an ith integration and read-out cycle, which start is set by the falling edge of the gate control pulse AB-g of the photodiode-initialization transistor AB, N=3 control pulses Tri.sub.1, Tri.sub.2 and Tri.sub.3 are applied in succession, at regular intervals, to the gate TRA.sub.1-g of the first transfer transistor TRA.sub.1. The falling edge of the last (Nth) pulse Tri.sub.3 marks the end of the current integration duration Tint(i).

(27) In this way, in case of high light levels, as charge is transferred a plurality of times during the integration period, the photodiode will be able to continue to accumulate charge throughout the integration duration; the charge is added in the memory node on each transfer. The transfers are carried out at regular intervals that are equally distributed over the integration duration Tint. In other words, in this example in which N=3, the time interval between the start of integration and the 1st transfer, between the 1st and 2nd transfers, and between the 2nd and 3rd transfers, is substantially the same.

(28) The two measures of the invention allow a method for controlling pixels to be implemented that has the technical effect of multiplying by N the charge accumulation capacity in each pixel over the duration of the integration period for a given photodiode capacity. However, this accumulation does not occur in the photodiode. In the invention, this accumulation occurs in the memory node, because charge is transferred at regular intervals from the photodiode to the memory node throughout the integration duration. As indicated above, the memory node is not subject to the same technological limitations as the photodiode: therefore it is possible to produce a memory node with the desired storage capacity, at least equal to N times the capacity of the photodiode, without adversely affecting the size of the pixel.

(29) The read-out node also preferably has, for its part, a capacity at least equal to N times that of the photodiode.

(30) Preferably, N is equal to 2 or 3.

(31) An active-pixel sensor having the general (electrical) structure in FIG. 1 is especially suitable for an image-taking method employing an integration duration that is common to all the pixels (global shutter) and a row-by-row correlated double sampling (CDS) read-out of the pixels by the read-out circuit at the bottom of each column.

(32) The control method according to the invention, which uses a memory node the capacity of which is at least N times that of the photodiode, is particularly suitable and advantageous for such an image-taking method.

(33) Such an image-taking method is now described with reference to the timing diagram of the control signals of the transistors, which diagram is shown in FIG. 2, and the diagrams of potentials in FIGS. 3 and 4. In FIGS. 3 and 4, the value of the potential of the various gates, which are represented by rectangles, is indicated by the fill colour of each rectangle: white=zero; black=V.sub.dd; grey=intermediate potential. Furthermore, to facilitate comprehension, the steps and the FIG. 3 or 4 that correspond to these steps are referenced by one and the same letter. Lastly, it will be noted that the timing diagrams and potential-barrier representation in FIGS. 2 to 4 correspond to a context in which the sensor is produced in a p-type active layer. Those skilled in the art will be able make the conversion to a context in which the active layer is n-type.

(34) An initial state (not shown in FIGS. 3 and 4) is started from, in which state the transistors are all in the off state.

(35) Each periodic integration and read-out cycle comprises an integration duration Tint common to all the pixels, then a CDS read-out of the pixels, row by row.

(36) As illustrated in FIG. 2, each integration and read-out cycle starts with a step a) of initializing all the photodiodes simultaneously. A corresponding diagram of the potentials in the structure is illustrated in FIG. 3a.

(37) In this step, an initialization control pulse AB(G) is applied simultaneously to the gates AB-g of all the initialization transistors AB: these are then fully turned on and empty the associated photodiode of all charge, via the drain D.sub.AB of the associated transistor. In a structure without an anti-blooming transistor AB, the photodiodes would be initialized by simultaneously turning on, for the time of the initialization pulse, the first and second transfer transistors and the reset transistor of the read-out node. The charge would then be evacuated to the drain of the reset transistor.

(38) The end of the common initialization pulse AB(G) causes the transistors AB to return to the off state and sets the start Start-INT of the integration duration Tint(i) for all the photodiodes PHD simultaneously: the photodiodes may, from this moment in time, once again accumulate the charge generated under the effect of the light to which they are exposed. This is step b) illustrated in FIGS. 2 and 3b.

(39) The following step c) (FIGS. 2 and 3c) consists in applying via the control signal TRA1(G) applied to all the gates TRA.sub.1-g of the pixels, a first control pulse Tri.sub.1: the first transfer transistors TRA.sub.1 are at this moment fully turned on, and the charge generated and accumulated by each photodiode from the start Start-INT of the current integration duration is transferred to the associated memory node. In the example, the voltage level corresponding to the active state of the control pulse Tri.sub.1 is a level V1 intermediate between 0 and Vdd, in order to lower the potential barrier of the semiconductor region under the gate TRA.sub.1-g to a level that allows the charge to transfer from the photodiode to the memory node.

(40) At the end of the control pulse Tri.sub.1, the photodiode again begins to accumulate charge: this is step d) (FIGS. 2 and 3d), until the next control pulse Tri.sub.2.

(41) Thus, steps c) and d) are applied to all the pixels simultaneously and are repeated in succession until the Nth transfer pulse, which is the 3rd pulse Tri.sub.3 in the example illustrated in FIG. 2: the end of this Nth pulse marks the end Stop-INT of the current integration duration Tint(i).

(42) A new integration duration Tint(i+1) of a new periodic cycle (of integration then read-out) may then start, repeating the steps a, b, c and d described above.

(43) With the end Stop-INT of the current integration duration Tint(i), the following phase of read-out of the pixels may start. It is a sequential row-by-row read-out. The pixels of a row are selected by applying a selection control pulse to the gate SEL-g of the selection transistor SEL of each pixel (FIG. 2: signal SEL(0) for the first row of rank 0), this causing, for each pixel of the selected row, the source of the follower transistor SF of the pixel to be electrically connected to the corresponding column conductor and therefore to the corresponding read-out circuit CL, for the time of this selection pulse. The CDS read-out of the pixels of the selected row is carried out during this selection time, and comprises the series of following steps a) to d):

(44) a) the gate RST-g of the reset transistor of the read-out node of each of the pixels of the selected row is drawn to the zero potential (FIG. 2: control signal RST(0) at zero for the row of rank 0), this gate being maintained at Vdd otherwise. The potential on the column conductor then reaches a reference level that is sampled by the read-out circuit at the bottom of the column. This sampling is represented in FIGS. 2 and 4a by the signal SHR.

(45) b) the second transfer transistor TRA.sub.2 of each pixel of the selected row is turned on, for the time of a control pulse of level Vdd, which is applied to their gate TRA.sub.2-g (signal TRA.sub.2(0) for the selected row of rank 0FIG. 2), allowing charge to be transferred from the memory node to the read-out node (FIGS. 2 and 4b).

(46) c) at the end of this transfer pulse, the potential of the column conductor reaches a signal level representative of the amount of charge on the read-out node, and this signal level is sampled by the read-out circuit at the bottom of the column (SHS, FIGS. 2 and 4c).

(47) d) the gate RST-g of the transistor is returned to the potential Vdd (RST(0)=Vdd) then the row is deselected (end of the selection pulse SEL(0)FIG. 2).

(48) Steps a to d are applied simultaneously to all the pixels of the selected row.

(49) The sequence of read-out steps a) to d) is repeated for each of the rows of pixels in succession, as illustrated in FIG. 2, for the following row of rank 1, with the corresponding control signals SEL(1), RST(1) and TRA.sub.2(1).

(50) At the same time as the following read-out phase, an integration duration Tint(i) is ongoing, or after this read-out phase, a new integration duration (Tint(i+1)) of a following integration and read-out cycle may start.

(51) However, the read-out of all the rows must be terminated before the first transfer pulse Tri1 produced after a duration Tint(i+1)/N following the start of the following integration duration Tint(i+1).

(52) The invention just described allows the dynamic range of an active pixel comprising an intermediate memory node between the photosensitive element and the read-out node to be improved by obviating technological constraints without increasing the area of the photosensitive element. It may even be envisaged to decrease this photosensitive-element area while compensating for the loss of fill factor by using a microlens on each pixel to concentrate the light toward the photosensitive area of the pixel.

(53) The invention is particularly advantageous for miniaturized sensors if it is furthermore envisaged to implement it with memory-node technologies that provide a capacitance per unit area that is intrinsically higher than that achieved with the technologies of pinned photodiodes.