Handle for semiconductor-on-diamond wafers and method of manufacture

Abstract

Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Claims

1. A method of forming a composite wafer, comprising: (a) preparing a stack of layers including a carrier plate, an adhesive layer disposed directly on the carrier plate, and a semiconductor-on-diamond wafer disposed directly on the adhesive layer, the carrier plate including a diamond material, the semiconductor-on-diamond wafer including a layer of single-crystal semiconductor and a layer of diamond that is in direct contact with the adhesive layer; (b) exerting axial pressure to the stack of layers to join the semiconductor-on-diamond wafer with the carrier plate to make a composite wafer, wherein a thickness variation of the composite wafer over a total area of the composite wafer is more than 30 m; (c) determining whether the composite wafer generated in the step (b) has a thickness variation of no more than 30 m over the total area of the composite wafer; and (d) responsive to a determination that the composite wafer has a thickness variation of more than 30 m over the total area of the composite wafer in the step (c), separating the carrier plate from the semiconductor-on-diamond wafer and returning to the step (a).

2. The method of claim 1, further comprising, after the step (b): (e) wherein the composite wafer generated in the step (b) has a bow of more than a third value over the total area of the composite wafer; (f) determining whether the composite wafer in the step (e) has a bow of no more than the third value over the total area of the composite wafer; and (g) responsive to a determination that the composite wafer has a bow of more than the third value over the total area of the composite wafer, separating the carrier plate from the semiconductor-on-diamond wafer and returning to the step (a).

3. The method of claim 2, wherein the third value is 30 m.

4. The method of claim 1, further comprising, prior to the step (a): mounting a semiconductor side of the semiconductor-on-diamond wafer to a temporary carrier.

5. The method of claim 4, further comprising: removing the temporary carrier from the semiconductor side of the semiconductor-on-diamond wafer.

6. The method of claim 1, further comprising, prior to the step (b): raking an adhesive in the adhesive layer to form ridges in the adhesive layer.

7. The method of claim 1, further comprising: providing a beveled edge to the adhesive layer.

8. The method of claim 1, further comprising, after the step (b): sealing areas on the composite wafer where an adhesive in the adhesive layer is exposed with a sealant; curing the sealant; processing the composite wafer; and removing the sealant.

9. The method of claim 8, wherein the sealant is chemically resistant to hydrofluoric acid.

10. The method of claim 1, further comprising, after the step (b): sealing areas on the composite wafer where an adhesive in the adhesive layer is exposed with a sealant, the sealant being capable of maintaining a seal at a temperature of 900 C.; and curing the sealant.

11. The method of claim 10, further comprising, after the step of curing the sealant: (e) wherein the composite wafer having the cured sealant has a thickness variation of more than a fourth value over the total area of the composite wafer; (f) determining whether the composite wafer in the step (e) has a thickness variation of no more than the fourth value over the total area of the composite wafer; and (g) responsive to a determination that the composite wafer has a thickness variation of more than the fourth value over the total area of the composite wafer in the step (f), separating the carrier plate from the semiconductor-on-diamond wafer and returning to the step (a).

12. The method of claim 11, wherein the fourth value is 30 m.

13. The method of claim 1, wherein an adhesive in the adhesive layer comprises a material having a melting point higher than 1000 C. and being capable of withstanding a temperature change of at least 900 C. in no more than 1.5 minutes while maintaining bonding between the semiconductor-on-diamond wafer and the carrier plate.

14. The method of claim 1, further comprising, after the step (b): (e) wherein the composite wafer generated in the step (b) has a tilt of more than a fifth value over the total area of the composite wafer, wherein the tilt corresponds to a variation in edge height around the composite wafer when the composite wafer is laid on a flat surface; (f) determining whether the composite wafer in the step (e) has a tilt of no more than the fifth value over the total area of the composite wafer; and (i) responsive to a determination that the composite wafer has a tilt of more than the fifth value over the total area of the composite wafer, separating the carrier plate from the semiconductor-on-diamond wafer and returning to the step (a).

15. The method of claim 14, wherein the fifth value is 30 m.

16. The method of claim 1, further comprising: forming a protection layer on the semiconductor side of the semiconductor-on-diamond wafer; and boiling the composite wafer in a water to separate the carrier plate from the semiconductor-on-diamond wafer.

17. The method of claim 16, wherein the step of forming a protection layer includes: spinning a photoresist on the semiconductor side of the semiconductor-on-diamond wafer.

18. The method of claim 16, wherein the step of forming a protection layer includes: forming a wax layer on the semiconductor side of the semiconductor-on-diamond wafer.

19. The method of claim 16, further comprising: placing the composite wafer in KOH.

20. The method of claim 19, further comprising: performing sonification on the composite wafer in KOH.

21. The method of claim 1, wherein the layer of single-crystal semiconductor comprises one or more of gallium nitride, aluminum nitride, and indium nitride.

22. A method of forming a composite wafer, comprising: (a) preparing a stack of layers including a carrier plate, an adhesive layer disposed directly on the carrier plate, and a semiconductor-on-diamond wafer disposed directly on the adhesive layer, the carrier plate including a diamond material, the semiconductor-on-diamond wafer including a layer of single-crystal semiconductor and a layer of diamond that is in direct contact with the adhesive layer; (b) exerting axial pressure to the stack of layers to join the semiconductor-on-diamond wafer with the carrier plate to make a composite wafer; (c) curing the adhesive layer to secure the semiconductor-on-diamond wafer to the carrier plate, wherein the composite wafer having the cured adhesive layer has a thickness variation of more than 30 m over a total area of the composite wafer; (d) determining whether the composite wafer generated in the step (c) has a thickness variation of no more than 30 m over the total area of the composite wafer; and (e) responsive to a determination that the composite wafer has a thickness variation of more than 30 m over the total area of the composite wafer in the step (d), separating the carrier plate from the semiconductor-on-diamond wafer and returning to the step (a).

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1: Illustration of definition of surface-roughness metrics R.sub.a and R.sub.t

(2) FIG. 2A: Illustration of definition of wafer bow

(3) FIG. 2B: Illustration of definition of wafer tilt

(4) FIG. 2C: Illustration of definition of total-thickness variation of wafer (TTV)

(5) FIG. 3: Illustration of the method to mount semiconductor-on-diamond wafers onto diamond handle wafers

(6) FIG. 4A: Illustration of the semiconductor-on-diamond wafer and the diamond handle wafer before bonding

(7) FIG. 4B: Illustration of the semiconductor-on-diamond wafer and the diamond handle wafer after bonding

(8) FIG. 5: Illustration of the method to dismount semiconductor-on-diamond wafers from diamond handle wafers and recycling of diamond handle wafer

(9) FIG. 6A: Illustration of the processed composite wafer before separation FIG. 6B: Illustration of the processed composite wafer after separation

(10) FIG. 7: Illustration of the method to process semiconductor-on-diamond wafers by mounting them onto a diamond handle wafer before processing and dismounting them after processing

DETAILED DESCRIPTION OF THE INVENTION

(11) The specifications on the mechanical rigidity, flatness, chemical inertness and processing temperature of wafers manufactured in commercial foundries depend on the type of lithography, the specific manufacturer's recipes for contact anneal and chemical processing. Hence there are both mechanical, temperature processing, and chemical inertness constrains on the SOD and DH wafers. The target specifications addressed in this application are given as follows (they do not represent a limitation on the invention is used):

(12) Starting GaN/Diamond wafer parameters are, but are not limited to the following: Average GaN/Diamond wafer thickness (W.sub.G): between 25 and 200 m, typically 100 m; Wafer diameter (D.sub.G): any standard wafer diameter; Maximum height of the surface profile (R.sub.tG): typical values are several tens of micrometers.

(13) Starting diamond-carrier wafer parameters are, but are not limited to the following: Average diamond carrier-wafer thickness (W.sub.c): typical values are between 500 m and 1000 m; Carrier wafer diameter (D.sub.c): matched to the size of the GaN/Diamond wafer; Maximum height of the surface profile (R.sub.tC): typical values are less than 10 m.
Composite Wafer Specifications (Non-Limiting Example Specific to this Application) (1) Bow (H.sub.B) less than 20 m over entire wafer; this specification is based on typical stepper specifications where as wafer diameter increases the bow specification generally stays the same. The specification will vary stepper to stepper. (2) Total thickness variation (TTV) is less than 30 m over entire wafer. (3) Tilt (H.sub.T) less than 30 m. (4) Thickness of competed composite wafer 62525 m. Maximum thickness is denoted with W.sub.F(min) and minimum W.sub.F(max). (5) Able to withstand peak process temperature (Tp) of 900 C. temperature change in less than 1.5 minutes. (6) Chemical resistance to: HF, HCl, H.sub.2SO.sub.4, HNO.sub.3, KOH, Tetramethylammonium hydroxide (TMAH), H.sub.2O.sub.2, Piranha, Nanostrip, Acetone, IPA, Methanol, Methylene Chloride, N-Methyl-2-pyrrolidone (NMP, 1165), Methyl Isobutyl ketone (MIBK), Methyl Ethyl Ketone (MEK), and other photoresist Developer solutions. (7) Removable after device processing, which includes 900 C. temperature exposure and multiple chemical exposures.

(14) FIG. 1 shows a schematic of a rough surface, such as one would find on a grown diamond wafer. The surface height profile is quantified with z(x,y) and the two typical surface roughness attributes are the arithmetic average of absolute values Ra and the maximum height of the profile R.sub.t. Maximum height of the surface profile is defined with the help of FIG. 1 as the difference between the maximum peak and the maximum valley depth of the surface profile provided that the average of the surface profile is horizontal. Both of these quantities can be measured as is well known in the art. The mathematical definitions are as shown in FIG. 1.

(15) FIG. 2 illustrates the wafer physical attributes: bow, tilt, and total-thickness variation (TTV) that may be used to quantify the physical adequacy of the wafer for semiconductor-device processing. In FIG. 2A, bow of the wafer is defined as the difference between the maximum and the minimum heights of the wafer when the wafer is positioned on a flat surface. Wafer tilt, shown in FIG. 2B, is a result of the wafer having non-uniform thickness so that when it is laid flat on a flat surface one side of the wafer may be higher than the opposite side. The tilt is measured at the wafer edges and the tilt value is the difference between the highest and the lower value of the edge height. FIG. 2C illustrates the definition of total thickness variation (TTV) which is a common metric for semiconductor wafers. Any one of these metric or all may be used to determine the suitability of a wafer to be used in a semiconductor device fabrication process.

(16) One embodiment of a method 300 for attaching a SOD wafer to a DH wafer is described with the help of the block diagram shown in FIG. 3. The method is described for attaching 75-mm GaN/Diamond wafers to similarly-sized DH wafer, but is applicable to any other wafer size without departing from the spirit of the invention. The method for mounting GaN/Diamond wafers is comprises of the following steps: A DH wafer 407 is provided in Step 301. In Step 302, cement 391 is provided. This process has been developed using Aremco BN-based cement, product number 690, but similar cements can be found and used as long as they satisfy the following conditions: it does not outgas appreciably once cured, is porous or easily removable, low expansion coefficient, chemical resistant to wafer processing chemistry, mechanically robust, and able to withstand a large thermal cycle range from room temperature to in excess of the peak process temperature Tp without going through any phase change or any alteration in chemical susceptibility.

(17) In Step 303, a GaN/Diamond wafer 401 is provided in free-standing form or mounted on a temporary carrier from which the GaN/Diamond wafer 401 can be removed using a low temperature or wet process.

(18) The thickness W.sub.c of the DH wafer 407 may be of any commercially available thicknesses, but is chosen so that to combined thicknesses W.sub.BN+W.sub.G+W.sub.C of the DH wafer 407, the GaN/Diamond wafer 401 and the expected thickness W.sub.BN of the cement 391 when squished between the two falls within the required final carrier-mounted wafer thickness: W.sub.F(min)W.sub.BN+W.sub.G+W.sub.C W.sub.F(max). Average thickness of the BN cement once cured (W.sub.BN); the thickness of the cement spread uniformly over the entire GaN/Diamond wafer and the entire DH wafer and need to planarize both wafers: W.sub.BN |R.sub.tCR.sub.tG|. The typical thickness of the cement 391 is between 20 and 70 micrometers though the cement can be over 200 microns and function correctly provided the carrier is thinner.

(19) In Step 304, the DB wafer 407 is placed on a tech-cloth and cement 391 evenly dispersed on top of the carrier wafer 407 so that it fills the roughness of the surface of the DB wafer 407 selected for bonding. A tech-cloth is a fabwipe or other clean room cleaning cloth. The cement 391 has to be sufficiently thick to completely fill and planarize the surfaces of both wafers once the cement-coated DB-wafer 407 is placed in contact with the GaN/Diamond wafer 401 in the next step. Often the wafers 407 or 401 will have 100-m tall super-grains on the surface to be bonded and the cement has to be thick enough to planarize the surface in their presence. The quantity of cement to be deposited on the wafer 407 is to be determined beforehand based on the surface roughness and the presence of super-grains.

(20) In Step 305, the cement-coated DB-wafer 407 is placed in contact with the GaN/Diamond wafer 401. This is illustrated in FIG. 4A where the GaN/Diamond wafer 401 with the top surface 402 and bottom surface 403 is brought into contact with the DB wafer 407 that has been coated with the cement 391 indicated with the surface 404. The bottom surface 403 of GaN/Diamond wafer 401 is the diamond surface and the top surface 402 is made out of GaN (or any other semiconductor) which may be coated with a dielectric. The wafers are placed in contact as indicated with the arrows 406. As shown in FIG. 4B, the composite wafer sandwich 410 now comprises GaN/Diamond wafer 401 and DB wafer 407 with a layer of cement 404 in between the two wafers. The cement layer 404 comprises cement 391. The composite wafer 410 is placed between two aluminum foils. When the composite-wafer 410 diameter is 75 mm, the wafer 410 is placed onto a 150 mm base wafer (base wafer larger than the composite wafer) and a ring that has an opening to fit the composite wafer 410 and an outer diameter equal to the base wafer. The stack is now covered with six more cover wafers of the same size as the base wafer. The ring is made of the same material as the base and the cover wafers. In one embodiment, the ring, base, and the cover are silicon wafers.

(21) In Step 306, axial force approximately equal to 150 N is applied in the direction of the arrows 406 in FIG. 4A in order to make the wafers flat and parallel. Once attached and pressed, the composite wafer 410 comprises of the semiconductor-on-diamond wafer 401, the diamond handle wafer 407, and the cement layer 404 sandwiched between them. The exposed edge of the cement layer 404 may be coated with a high-temperature sealant in a later step. In one embodiment, the wafer 401 and 407 are intended to be of the same size and shape. In yet another embodiment, the 401 wafer is slightly smaller than the wafer 407.

(22) In Step 307, the bow, tilt, and/or total thickness variation is measured on the composite wafer 410 and compared to the specification required by the process. If the specification is met one proceeds to step 308, otherwise one proceeds with rework in Step 310. In Step 310, the composite wafer 410 is immersed in water and separated into the original GaN/Diamond wafer 401 and DH wafer 407 and the process starts from step 301.

(23) In Step 308, the composite wafer 410 is cured at elevated temperature under axial pressure of at least 25 N. The weight used to apply the pressure must be able to withstand 400 C. For this purpose, ceramic weights are preferred as they are less thermally conductive. The temperature ramp applied to the composite wafer 410 follows for a 75-mm wafer: 6 hours at 90 C., 2 hours at 130 C., 6 hours at 260 C., and 6 hours at 370 C. This ramp can be accelerated for 50-mm wafers to approximately half the time. The ramp rate for 100-mm wafer bonds is expected to be 1.5 to double the time at each step. Failure to ramp at this interval may result in cement that isn't cured in the center, or non-uniformly cured wafers. This will lead to premature failure in subsequent steps. After the cement has been cured, while the hot plate is at maximum temperature, the weight should be removed and the hotplate turned off to allow the stack to cool to below 300 C. The entire assembly (cover wafers, the composite wafer, the wafer ring, and the base wafer) should be disassembled when sufficiently cool. The foil can be removed by gently pealing it back from the wafer/carrier. It may pop off by itself, but sometimes the cement weakly bonds it to the wafer. The composite wafer 410 is left on a cooling plate until the temperature reduces to room temperature.

(24) In Step 309, the composite wafer 410 is measured for bow, tilt, and/or TTV to check whether the wafer 410 meets specification. If the wafer fails this measurement, the composite wafer 410 has to be re-worked by proceeding with Step 311 in which hot KOH is used remove the GaN/Diamond wafer from the DH wafer and re-start the procedure. The wafer should be exposed to hot KOH for 5 or more minutes, until the wafer releases. Alternatively the wafer can be soaked in boiling water for 30 minutes and then hot KOH (this may shorten the KOH exposure requirements). Then sonication or mechanical cleaning methods can be used to remove the cement, followed by DI rinse to remove any excess KOH. The cement can be wiped off the carrier and sonication used on the wafer. This can be done in water after the cement has been broken up by the KOH. In one embodiment, the rework step 311 involves wafer separation described with method 500. If the wafer conforms to the specification proceed with Step 312.

(25) Step 312, is optional. It should be executed if there is silicon nitride, silicon oxide, or other material deposited on top of the GaN surface that needs to be removed using hydrofluoric acid. To etch the surface material, the cemented edge (between GaN/Diamond wafer) and the DH wafer should be sealed so the wafer can be cleaned. The sealing of the cement 391 is performed using a temporary (low-temperature) sealant, such as, I-line photo resist (OCG OiR-700 10). The type and thickness of the temporary sealant is not critical except that during the application it has be sufficiently dilute that it flows readily. The sealant is applied onto the exposed cement edges and it wicks into the pores of the cement filling them. It happens that due to wicking, sealant can get smeared on top of the wafer several centimeters towards the center composite wafer 410. The photoresist on the surface can be readily removed by wiping with a tech cloth and acetone (acetone applied to the cloth and not directly on to the wafer). The sealant (in this case photoresist) is then partially cured at 90 C. for 5 minutes, and then 135 C. for 5 minutesit should not be excessively cross-linked (occurs at higher temperatures) so that it can be later removed. Once the resist is cured, the wafer surface is cleaned from excess cement. The cleaning of the cement is done at 135 C. and using a cloth soaked into concentrated solution of KOH (saturated or near saturated solution). The KOH wiping is followed by wiping with a cloth soaked in DI water to remove the excess KOH, and then rinsed using a spray gun and dried.

(26) The silicon nitride or other material is removed using concentrated HF (49%) for as much time as is required to remove the silicon nitride or other material. After the nitride or material has been removed, the temporary sealant is removed. If photoresist is used, the wafer should be soaked in acetone (typical time is at least 1 minute, but not more than 5 minutes, followed by IPA for 1 minute, rinse in IPA, and nitrogen gun dry).

(27) In Step 313, the composite wafer undergoes a high temperature seal. This permanent sealant has to withstand the same temperature required on the composite wafer. In this specific application, that temperature is 900 C. The high-temperature sealant is 6% to 20% solution of hydrogen silsesquioxane (HSQ) in MIBK. These are standard products available from Dow Corning (such as the 6% and 20% solutions of XR-1541, and there are alternate lower grades that may be suitable for this application). The high-temperature sealant is applied along the cement edge as to cover the cement completely, it usually takes three applications. This step should be done under a fume hood as HSQ is toxic when uncured. The excess HSQ that accidentally appears on the front surface of the composite wafer should be removed using an acetone or other suitable solvent-soaked cloth. It is critical that all the HSQ is removed from the surface as it will turn into silicon dioxide upon cure. The composite wafer is dried at 90 C. and any excess HSQ flowing out from the wafer is removed. At this point no bubbles should be forming, and if there are any, more HSQ should b e added to those places. The 90 C. bake should last 5 minutes, and then the temperature should be increased up to 130 C. and baking should last another 5 minutes. The temperature is then increased to 375 C. in 25 C. increments with soaking for 5 minutes at each temperature. At 375 C. the soak time is at least 15 minutes. After this curing, the composite wafer should be left to cool.

(28) In Step 314, the composite wafer is characterized for bow, tilt, and/or TTV. If the final specifications are met, the method for mounting semiconductor-on-diamond wafers is complete: The composite wafer is ready for further processing. The exemplary view of the completed composite wafer 410 is given in FIG. 4B.

(29) Various versions of the aforementioned process may be performed. One exemplary process utilizes the following method steps: 1. Secure the GaN side of the GaN/D wafer onto an optically flat surface (could be quartz, diamond or other material) using heat tape. 2. Press and flatten the upside down GaN/D onto the optically flat surface to remove any bubble at the interface of heat tape and diamond. a. There is an advantage in using the clear optical flat (like quartz), as one can visually check for the presence of bubbles. The disadvantage would be the difference in CTE. i. With quartz this step is done at about 90-100 C. ii. With diamond this step is done at room temperature. 3. Make a thickness map (5 or more points) of the secured GaN/D+heat tape stack. 4. Apply ceramic adhesive onto the diamond side of the GaN/D wafer (clean excess material from the optical flat). 5. Gently rake the ceramic adhesive to form ridges (ridges allow for more porosity in the adhesive and make the adhesive thinner). 6. Press the handle wafer (HW) onto the ceramic adhesive+upside down GaN/D+heat tape stack. 7. Using pressure and localized sonication the stack is flattened to a predetermined height at multiple (5 or more) locations (objective is achieve parallelism) to within the resolution of the measurement tool (1 m). 8. Allow the ceramic adhesive to air dry at room temperature for 4 hours. 9. Soft bake at 90 C. for 1 to 2 hours and 130 C. for 1 to 2 hours. a. At 200 C. the heat tape will fail and allow to free the GaN/D+ceramic adhesive+HD from the optical flat. 10. Make multiple point measurements to assure parallelism and achievement of the thickness specifications between top of the GaN and bottom of HW. 11. Bake the completed stack at 260 C. for 1 to 2 hours and 370 C. for 1 to 2 hours. 12. Final bake of the stack at 700 C. for 5 to 10 minutes in an inert atmosphere. 13. Apply a beveled layer of ceramic adhesive at the periphery of the mounted GaN/D wafer. a. The objective of the beveled adhesive layer is to guard against debris build up and ease of flow of solutions associated with any subsequent fabrication processes. 14. Apply a glass layer (HSQ) to seal the adhesive ceramic and guard against unintended dismount due to subsequent fabrication processes. 15. Bake the HSQ coated wafer to 350 C. for 10 minutes to harden the HSQ.

(30) Several advantageous nuances of the aforementioned process may be noted including the following: (1) Providing a beveled edge to the ceramic adhesive layer is advantageous as it improves subsequent fabrication steps. (2) The porous nature of ceramic adhesive is advantageous as open pores allow for solution delivery and easy dismount of the semiconductor-on-diamond wafer from the diamond handle wafer. (3) Providing a sealant around the ceramic adhesive layer is advantageous for preventing solutions entering the porous adhesive layer during subsequent fabrication steps.

(31) Achievable flatnesses for the top surface of the semiconductor-on-diamond wafer when bonded to a diamond handle wafer in the aforementioned manner can be better than 30 m, 20 m, 10 m, 5 m, or 1 m.

(32) According to one embodiment the ceramic adhesive is applied to a surface of the diamond handle wafer and then the semiconductor-on-diamond wafer is bonded thereto. According to another embodiment the ceramic adhesive is applied to the diamond side of the semiconductor-on-diamond wafer and then the diamond handle wafer is bonded thereto. For example, based on the curvature of a GaN/D wafer it may be advantageous to dispense the ceramic adhesive onto the diamond side of with GaN/D wafer while otherwise proceed according the flow chart illustrated in FIG. 3.

(33) A method 500 for releasing the semiconductor-on-diamond wafer from the DH wafer is illustrated with the help FIG. 5.

(34) In Step 501, a composite wafer 610 is provided. This wafer has a semiconductor surface 602 (front) and DH surface 605 (back) as shown in FIG. 6A. The front surface 602 contains electronic or optoelectronic devices 609 disposed on it. These devices have been manufactured or are partly manufactured on the surface 602 while the semiconductor-on-wafer 601 has been attached to the DH 607 using the cement 604 between the two wafers.

(35) In Step 502 the front surface 602 of the composite wafer 610 is protected by spinning photoresist on it so that all features 609 are covered in resist. Choose a resist and spinning speed to ensure the devices are fully protected. The selection of resist is not criticala generic positive photoresist is sufficient. Pre-bake as specified for the specific resist. The resist must be able to withstand KOH at elevated temperatures for longer than the duration of the entire removal process. It is recommended that an extended bake be used. Alternatively the front side of the wafer can be covered in wax, and a handle wafer can be temporarily bonded to the front surface for additional protection. Using a cotton swab dipped in appropriate solvent, clean the edge interface between the GaN on diamond wafer and the DH wafer. Wick acetone into this opening using a cotton swab, and ensure that the resist still protects the devices. This interface must be very clean or the rest of the procedure may fail.

(36) In Step 503, the coated composite wafer 610 is etched in 49% HF for 1 minute or until a white solution is observed leaching out from the edges between the wafers. This etching is halted by soaking the composite wafer in DI water for 1 minute and rinsing with flowing DI water for at least 30 seconds.

(37) In Step 504, the composite wafer 610 is boiled in DI water for up to 30 minutes. The composite wafer 610 may separate into GaN/Diamond 601 and diamond-carrier 607 wafers.

(38) In Step 505, the composite wafer 610 (or the separated wafers 601 and 607) are placed in concentrated hot KOH for 5 minutes. If it has not separated already, the composite wafer 610 should separate from the cement during this step.

(39) If during Step 505, the composite wafer 610 separates, denoted by the test in Step 506, one may proceed to Step 508. If no separation is observed one proceeds with Step 507 where sonification is used to assist in the separation of the composite wafer 610. The sonification is performed while the wafer is in the KOH solution. The sonification schedule is one minute of sonication in solution every 5 minutes. Once the wafers have separated (yes in Step 506), one can either use a cotton swab to gently rub off the excess cement from the back of the wafer and carrier in KOH solution, or use sonication to do it. The cement will separate from the parts quickly. The KOH bath process is terminated using a rinse of all parts in DI water.

(40) In Step 508, using an appropriate solvent, the protective photoresist is removed from the GaN on diamond wafer and the front surface is cleaned as necessary.

(41) At the end of the process (Step 509), two wafers are produced as illustrated in FIG. 6B. A GaN/Diamond wafer 620 with now processed electronic or optoelectronic devices 609 on its top surface 602 and a DH wafer 630 which is now reused for similar mounting, i.e., provided again in Step 301 in FIG. 3.

(42) It will be clear to a person skilled in the art that variation in the specific times and order of process steps may be employed to accomplish similar results as is disclosed above and that these variations do not depart from the spirit of the invention.

(43) The overall process 700 of using the disclosed mounting method and apparatus is described with the help of FIG. 7. In Step 701, a semiconductor-on-diamond wafer 710 on top of which one desires to fabricate semiconductor devices is provided. The wafer 710 is typically too thin to be processed free-standing or may have bow, tilt, or TTV that does not comply with the requirements for lithography during the semiconductor-device process. Such a wafer is mounted on a DH wafer according to the method described above (500). In Step 702, a DH wafer 720 is provided and in step 703 the semiconductor-on-diamond wafer is mounted on top of said DH wafer 720. Such a composite wafer will have mechanical rigidity and bow, tilt, and/or TTV satisfying standard semiconductor-device manufacturing process wafer requirements. In Step 704, the composite wafer is processed and electronic or optoelectronic devices are fabricated on its surface. The devices may be partly fabricated when the semiconductor-on-diamond wafer needs to be separated from the DH wafer in step 705. At this point semiconductor-on-diamond wafer 740 has electronic devices (or at least part of the electronic devices) manufactured on its surface and the wafer 740 is ready for further processing which may require free-standing semiconductor-on-diamond wafer. The wafer 740 may eventually be mounted onto a DH wafer again and the process 700 may be repeated with the same semiconductor-on-diamond wafer. The DH wafer 730 can be reused as is indicated with 706 in FIG. 7. In this way, an expensive substrate is not wasted, but its mechanical and thermal properties are used during the semiconductor-device processing.