TWO-TERMINAL MEMORY DEVICE, A METHOD FOR MANUFACTURING THE SAME, AND A SEMICONDUCTOR DEVICE INCLUDING A TWO-TERMINAL MEMORY DEVICE

Abstract

A two-terminal memory device including: a substrate; a source and a drain formed to face each other on an upper surface of the substrate; a ferroelectric layer connected to the source and the drain and formed between the source and the drain; and an extended drain extending from the drain and laminated on the ferroelectric layer. The two-terminal memory device may be applied as a cross-point type and neuromorphic device capable of implementing multi-resistance levels with multi-layer switchable resistance layers.

Claims

1. A two-terminal memory device comprising: a substrate; a source and a drain formed to face each other on an upper surface of the substrate; a ferroelectric layer connected to the source and the drain, and formed between the source and the drain; and an extended drain extending from the drain and laminated on the ferroelectric layer.

2. The two-terminal memory device of claim 1, wherein the extended drain covers an upper region of the drain and the ferroelectric layer of a region between the source and the drain.

3. The two-terminal memory device of claim 2, wherein the ferroelectric layer is laminated in a form of covering the substrate, the source, and the drain other than the extended drain.

4. The two-terminal memory device of claim 2, wherein the ferroelectric layer is made of a material with a spontaneous polarization property.

5. The two-terminal memory device of claim 4, wherein the ferroelectric layer is made of an oxide film consisting of any one material of polyvinylidene fluoride (PVDF), or an oxide material, such as hafnium zirconium oxide (HfZrO.sub.2), haflanthanum oxide (La:HfO.sub.2), aluminum (Al):hafnium oxide (HfO.sub.2), or silicon (Si):hafnium oxide (HfO.sub.2).

6. The two-terminal memory device of claim 2, further comprising: a semiconductor layer connected to the source and the drain, and laminated on the substrate, wherein the ferroelectric layer is laminated on an upper surface of the semiconductor layer.

7. The two-terminal memory device of claim 2, wherein the polarization of the ferroelectric layer is adjusted by an input voltage pulse applied to the drain.

8. The two-terminal memory device of claim 7, wherein an electrical conductance of a channel region between the source and the drain is linearly changed depending upon a change in the input voltage pulse.

9. A semiconductor device comprising: the two-terminal memory device of claim 3; a metal oxide semiconductor field effect transistor (MOSFET) source sharing a source as an intermediate electrode, and formed on the substrate to face the intermediate electrode; an insulator formed between the intermediate electrode and the MOSFET source; and a gate formed on the insulator.

10. A two-terminal memory device comprising: a substrate; an extended drain extending from a drain and a lower surface of the drain, and laminated on the substrate; a ferroelectric layer connected to the drain, and covering the extended drain and the substrate; and a source laminated on the ferroelectric layer to face the drain.

11. The two-terminal memory device of claim 10, wherein the ferroelectric layer is made of an oxide film consisting of any one material of polyvinylidene fluoride (PVDF), or an oxide material, such as hafnium zirconium oxide (HfZrO.sub.2), haflanthanum oxide (La:HfO.sub.2), aluminum (Al):hafnium oxide (HfO.sub.2), or silicon (Si):hafnium oxide (HfO.sub.2).

12. The two-terminal memory device of claim 10, further comprising: a semiconductor layer connected to the source and the drain and laminated on the ferroelectric layer.

13. A semiconductor device comprising: the two-terminal memory device of claim 10; a metal oxide semiconductor field effect transistor (MOSFET) source sharing a source as an intermediate electrode, and disposed to face the intermediate electrode; a gate formed on the substrate; and an insulator covering the gate and formed between the intermediate electrode and the MOSFET source.

14. A method for manufacturing a two-terminal memory device, the method comprising: forming a semiconductor layer on a substrate; forming a source and a drain connected to the semiconductor layer and facing each other on the substrate; laminating a ferroelectric layer covering the substrate, the semiconductor layer, the source, and the drain; etching a region of the ferroelectric layer covering the drain; and forming an extended drain extending from an upper surface of the drain and covering a partial region of the ferroelectric layer.

15. The method for manufacturing the two-terminal memory device of claim 14, wherein the partial region of the ferroelectric layer is a region between the source and the drain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG. 1 schematically illustrates a conventional ferroelectric memory device.

[0040] FIG. 2 illustrates a memory device according to a first embodiment of the present disclosure.

[0041] FIG. 3 illustrates an aligned state where a voltage is initially applied to the memory device according to the first embodiment of the present disclosure.

[0042] FIGS. 4-6 sequentially illustrate polarization according to the application of a positive voltage to the memory device according to the first embodiment of the present disclosure.

[0043] FIG. 7 illustrates a current measurement result when the positive voltage is applied as illustrated in FIGS. 4-6.

[0044] FIGS. 8-10 sequentially illustrate polarization according to the application of a negative voltage to the memory device according to the first embodiment of the present disclosure.

[0045] FIG. 11 illustrates a current measurement result when the negative voltage is applied as illustrated in FIGS. 8-10.

[0046] FIGS. 12A-17B sequentially illustrate a method for manufacturing the memory device according to the first embodiment of the present disclosure, in which FIGS. 12A, 13A, 14A, 15A, 16A, and 17A illustrate shapes of side surfaces of the memory device, and FIGS. 12B, 13B, 14B, 15B, 16B, and 17B illustrate shapes of upper surfaces thereof.

[0047] FIG. 18 illustrates a semiconductor device according to a first application embodiment of the present disclosure.

[0048] FIG. 19 illustrates a memory device according to a second embodiment of the present disclosure.

[0049] FIG. 20 illustrates a semiconductor device according to a second application embodiment of the present disclosure.

[0050] FIG. 21 illustrates a memory device according to a third embodiment of the present disclosure.

DESCRIPTION OF SPECIFIC EMBODIMENTS

[0051] To fully understand the present disclosure, the operational advantages of the present disclosure, and the object achieved by the practice of the present disclosure, reference should be made to the accompanying drawings illustrating embodiments of the present disclosure and the contents described in the accompanying drawings.

[0052] In describing embodiments of the present disclosure, a description of well-known techniques or repetitive descriptions that may unnecessarily obscure the gist of the present disclosure has been decreased or omitted.

[0053] FIG. 2 illustrates a memory device according to a first embodiment of the present disclosure. Hereinafter, a two-terminal memory device according to a first embodiment of the present disclosure is described with reference to FIG. 2.

[0054] The memory device according to the present disclosure is a device that has the features of a transistor-based synaptic device in which an insulator is substituted with a ferroelectric and has a two-terminal structure unlike the conventional three-terminal structure.

[0055] Unlike the general three-terminal-based ferroelectric-based synaptic device illustrated in FIG. 1, the memory device according to the present disclosure has a structure in which a drain extends to an upper portion of a ferroelectric to overlap the ferroelectric, and a structure capable of being applied to a cross-point structure, such as a resistance type memristor, by improving an increase in complexity of the three-terminal structure.

[0056] The conventional three-terminal ferroelectric memory structure separately uses the gate for adjusting the state of the memory, and the drain/source necessary for confirming the stored state of the memory. In other words, two operations are separately used, but when the structure according to the present disclosure is used, two operations may be implemented even without the gate. As a result, it is possible to perform an analog multiply-accumulate (MAC) operation used for a resistance type memory-based array research. Further, it is possible to implement an operation suitable for implementing a process-in-memory by implementing multiple levels according to the application of the voltage. Such an operation may not be applied to the conventional three-terminal structure.

[0057] To this end, the structure according to the present disclosure is composed of a substrate 110, a semiconductor layer 120, a source 130, a drain 140, a ferroelectric layer 150, and an extended drain 160.

[0058] The substrate 110 may be formed of a silicon, germanium, or silicon oxide substrate, a glass, a PET film, or the like.

[0059] The semiconductor layer 120 formed on the substrate 110 includes a semiconductor material, such as silicon, germanium, group III-V semiconductor, oxide semiconductor, organic semiconductor, transition metal dichalcogenide, or phosphorene.

[0060] The source 130 and the drain 140 are laminated to face each other on both sides of an upper surface of the substrate 110, and the source 130 and the drain 140 are connected by the semiconductor layer 120.

[0061] The ferroelectric layer 150 is laminated in a form of covering all regions other than the upper surface of the drain 140, including an upper surface of the semiconductor layer 120 between the source 130 and the drain 140.

[0062] The ferroelectric layer may be formed by growing, depositing, or directly transferring a material with a spontaneous polarization property, for example, a polymer material, such as polyvinylidene fluoride (PVDF), or an oxide film, such as hafnium zirconium oxide (HfZrO.sub.2), haflanthanum oxide (La:HfO.sub.2), aluminum (Al):hafnium oxide (HfO.sub.2), or silicon (Si):hafnium oxide (HfO.sub.2).

[0063] Further, according to the present disclosure, the extended drain 160 is formed in a form of covering the drain 140 and a partial region of the ferroelectric layer 150.

[0064] In other words, the extended drain 160 has a structure of covering the upper region of the drain 140 and the ferroelectric layer 150 of the region between the drain 140 and the source 130.

[0065] The corresponding structure is formed in a form in which the extended drain 160 connected to the drain 140 overlaps a channel region, and therefore, the source 130 may be grounded and the polarization of the ferroelectric layer 150 may be adjusted by an input voltage pulse applied to the drain 140, thereby gradually increasing conductance of the semiconductor channel.

[0066] The corresponding structure does not require a new additional process other than the ferroelectric process in the conventional silicon metal oxide semiconductor field effect transistor (MOSFET) process, thereby becoming a very easy form to apply to the industry.

[0067] The conventional three-terminal ferroelectric memory may perform only the read operation through the drain, and should perform the write and erase operations through the gate, but the two-terminal ferroelectric memory device according to the present disclosure may perform the write and erase operations as well as the read operation through the drain 140, thereby significantly decreasing complexity upon forming the memory array, thereby being greatly advantageous in forming a high integration memory array. It may be seen that the process is not largely different from that of the conventional three-terminal transistor, thereby being easily used.

[0068] Next, FIG. 3 illustrates an aligned state where a voltage is initially applied to the memory device according to the first embodiment of the present disclosure.

[0069] FIGS. 4-6 sequentially illustrate polarization according to the application of a positive voltage to the memory device according to the first embodiment of the present disclosure, and FIG. 7 illustrates a measurement result of the electrical conductance that is changed as the positive voltage is applied as illustrated in FIGS. 4-6.

[0070] Assume that since the resistance of the channel in the lower region is changed depending upon the alignment of the polarization, a change in the resistance (conductance) inside the channel may be equally operated even if the contact resistance is large.

[0071] As illustrated in FIG. 4, before the alignment occurs in the ferroelectric layer 150 initially, a potential of the channel (semiconductor) region may be evenly changed. The alignment of the polarization occurs from the ferroelectric around the source 130 in which a voltage difference is largely caused by the applied input voltage pulse (e.g., +3 V or more, the magnitude of the voltage that is enough to generate the polarization).

[0072] FIGS. 4-6 illustrate the height of the voltage difference (potential difference) by expressing the potential of the device with shades (gradation). The height is indicated such that a rapid potential difference may be caused by a voltage distribution phenomenon in a region with a large resistance. It may be seen that the alignment of the polarization sequentially occurs from the ferroelectric around the source 130.

[0073] In other words, when the positive input voltage pulse is sequentially input, the resistance of the channel of the lower portion is decreased while the polarization of the ferroelectric of the region around the source 130 is aligned.

[0074] Therefore, in FIGS. 4-6, the gradual increase in the region with the low potential (thin portion) within the channel region means that the resistance of the channel at the corresponding position is decreased by the aligned polarization. A section in which the resistance is decreased is increased from the source 130 toward the drain 140 by the application of the continuous positive input voltage pulse, thereby gradually increasing the electrical conductance of the comprehensive channel.

[0075] Referring to the measurement result of the FIG. 7, for example, a change in the electrical conductance of the device may be a current value confirmed by applying the read voltage of +0.1 V. The read voltage has the magnitude of the degree that does not change the resistance of the device and may be determined by a value capable of confirming the electrical conductance (for example, it is an expressed value and may be fluctuated).

[0076] It may be seen that the alignment of the polarization is caused by a constant positive input voltage pulse and the electrical conductance may be gradually increased. A synaptic device potentiation operation may be performed by the gradual increase in the electrical conductance and applied to a neuromorphic chip using the above operation.

[0077] Further, FIGS. 8-10 sequentially illustrate the polarization according to the application of the negative voltage of the memory device according to the first embodiment of the present disclosure. FIG. 11 illustrates the measurement result of the electrical conductance that is changed as the negative voltage is applied as illustrated in FIGS. 8-10.

[0078] As illustrated in FIG. 8, to decrease the electrical conductance of the device, a negative input voltage pulse (e.g., −3 V) may be applied to the drain 140 and the ground may be applied to the source 130. Therefore, the drain 140 has a low potential, and the grounded source 130 has a high potential.

[0079] The read voltage has the magnitude of the degree that does not change the resistance of the device and may be determined by the value capable of confirming the electrical conductance.

[0080] It may be seen that the alignment of the polarization occurs from the ferroelectric around the source 130 in which the voltage difference is largely caused by the applied input pulse.

[0081] Therefore, a rapid potential difference is caused by the voltage distribution property as the resistance of the semiconductor channel in the corresponding region increases. When the negative input voltage pulse is input, the resistance of the channel at the corresponding position is increased as the polarization is sequentially aligned from the source 130 toward the drain 140, thereby gradually decreasing the resistance of the channel as illustrated in FIG. 11.

[0082] A synaptic device depression operation may be performed by the gradual decrease in the electrical conductance and may be applied to the neuromorphic chip using the above operation.

[0083] Next, FIGS. 12A-17B sequentially illustrate a method for manufacturing the memory device according to the first embodiment of the present disclosure. FIGS. 12A, 13A, 14A, 15A, 16A, and 17A illustrate shapes of side surfaces of the memory device, and FIGS. 12B, 13B, 14B, 15B, 16B, and 17B illustrate shapes of upper surfaces thereof.

[0084] Hereinafter, a method for manufacturing the memory device according to the first embodiment of the present disclosure is described with reference to FIGS. 12A-17B.

[0085] First, the substrate 110 (e.g., bare Si wafer) is provided, and the semiconductor layer 120 is deposited on the substrate 110.

[0086] Further, the source 130 and the drain 140 are deposited and formed to face each other on both sides of the upper surface of the substrate 110, and each of a part of the source 130 and a part of the drain 140 is connected to the semiconductor layer 120.

[0087] Then, the ferroelectric layer 150 is deposited to entirely cover the substrate 110, the semiconductor layer 120, the source 130, and the drain 140.

[0088] Further, the ferroelectric layer 150 covering the upper surface of the drain 140 is etched.

[0089] Then, the extended drain 160 is formed. The extended drain 160 is manufactured by being deposited to cover the upper region of the drain 140 and the ferroelectric layer 150 of the region between the drain 140 and the source 130.

[0090] Next, FIG. 18 illustrates a semiconductor device according to a first application embodiment of the present disclosure.

[0091] A semiconductor device according to a first application embodiment of the present disclosure may be formed in a 1Transfer1Receiver (1T1R) form in which a memory device 210 according to the aforementioned first embodiment is positioned on a left portion of an upper end of the substrate and a MOSFET device 220 is positioned on a right portion thereof, in which a source of a central portion thereof, as an intermediate electrode, is shared by the respective devices.

[0092] It is possible to solve a leakage current problem that occurs upon forming the cross-point array by adjusting a gate voltage of the MOSFET device 220 connected to the two-terminal memory device 210.

[0093] The two-terminal ferroelectric memory positioned on the left portion has the semiconductor region (Semi.) on the substrate and the ferroelectric on the semiconductor region (Semi.), and has the drain, the intermediate electrode, and the extended drain positioned on both ends of the two-terminal ferroelectric memory.

[0094] Further, the MOSFET device 220 positioned on the right portion shares the intermediate electrode, and has a semiconductor region (Semi.) positioned on the substrate, a source (may be referred to as a MOSFET source for distinguishing it from the source of the two-terminal memory device) connected to the semiconductor region (Semi.) disposed on the right of the MOSFET device 220, and an insulator and a gate sequentially positioned on the semiconductor region (Semi.).

[0095] Upon manufacturing the corresponding structure, since the processes other than the ferroelectric and insulator processes may be performed together due to the similar structural features, there also exists an advantage in that the process is simplified.

[0096] Next, FIG. 19 illustrates a memory device according to a second embodiment of the present disclosure.

[0097] As illustrated, a memory device according to a second embodiment has a drain 360 and a source 350 positioned on both ends of the device, and an extended drain 320 positioned on one side of the upper end of the substrate 310. The ferroelectric layer 330 is formed on the substrate 310 while partially covering the extended drain 320 and formed by being etched to cover the region other than the region of the drain 360.

[0098] A semiconductor layer (semiconductor channel) 340 is formed on the ferroelectric layer 330 in an upward direction corresponding to the extended drain 320. Also, the source 350 is formed on the ferroelectric layer 330 on one side or end of the semiconductor layer 340 and the drain 360 is formed on the extended drain 320 on the other side or end of the semiconductor layer 340.

[0099] The changed point of the operation of the device is not caused by the changed structure, and the thickness of the insulator between the extended drain 320 and the source 350 may be easily secured, thereby minimizing the influence of the undesired leakage current.

[0100] FIG. 20 illustrates a semiconductor device according to a second application embodiment of the present disclosure illustrated in FIG. 19.

[0101] Similar to the first application embodiment of the present disclosure, the second application embodiment of the present disclosure has a memory device 410 according to the second embodiment positioned on a left portion of the upper end of the substrate and a MOSFET device 420 positioned on a right portion thereof.

[0102] The two-terminal ferroelectric memory positioned on the left portion has an extended drain positioned on the substrate, and a ferroelectric layer positioned on the extended drain. The two-terminal ferroelectric memory has a structure of the form (bottom gate form) that has a drain connected to the extended drain, a semiconductor layer (Semi.), and an intermediate electrode disposed therein, has a gate, an insulator, and the semiconductor layer (Semi.) sequentially disposed on the substrate at the right portion thereof, and has the intermediate electrode and the source (may be referred to as a MOSFET source for distinguishing it from the source of the two-terminal memory device) contacting the semiconductor layer (Semi.).

[0103] Through the corresponding structure, it is possible to implement the 1T1R structure, and to easily secure the thickness of the insulator between the extended drain and the intermediate electrode, thereby minimizing the influence of the undesired leakage current.

[0104] Lastly, FIG. 21 illustrates a memory device according to a third embodiment of the present disclosure. The same description as that of the aforementioned first embodiment is be omitted.

[0105] A memory device according to a third embodiment may have a channel region formed in a region of an upper end of a substrate (P-type).

[0106] A doping concentration of the substrate (semiconductor) may be adjusted into an N or P type using, for example, an ion implantation technique and the channel region may be formed on a lower end of a ferroelectric layer depending upon the alignment degree of the polarization of the ferroelectric layer.

[0107] The present disclosure has been described above with reference to the drawings but is not limited to the described embodiments. It should be apparent to those having ordinary skill in the art that various modifications and changes may be made without departing the spirit and scope of the present disclosure. Therefore, the modified examples or the changed examples are included in the claims of the present disclosure, and the scope of the present disclosure should be interpreted based on the appended claims.