Encoder device, decoder device, and methods thereof

Abstract

An embodiment encoder device for encoding an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] having K information bits, c.sub.i, includes an encoder for a tail biting convolutional code having a constraint length, L, where K<L1; the encoder being configured to receive the K information bits; and encode the K information bits so as to provide an encoded code word. An embodiment decoder device for determining an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1], having K information bits, c.sub.i, includes a decoder for a tail biting convolutional code having a constraint length, L, where K<L1; the decoder being configured to: receive an input sequence; compute at least one reliability parameter based on the received input sequence; and determine an information word c based on the at least one reliability parameter.

Claims

1. A device, comprising: an encoder comprising a tail biting convolutional code having a constraint length, wherein L represents a length of the constraint length of the tail biting convolutional code, the encoder being configured to: receive K information bits c.sub.i of an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1], wherein K represents a number of information bits c.sub.i received, K is less than L minus one; and encode the K information bits to provide an encoded code word using the tail biting convolutional code.

2. The device according to claim 1, wherein the encoder comprises an initial state of bit values and a final state of bit values for encoding of the K information bits, and wherein the initial state of bit values is the same the final state of bit values.

3. The device according to claim 2, wherein the encoder further is configured to: append at least one bit to the information word c to obtain an appended information word c having K information bits, wherein c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] and KL1; and use the appended information word c as the initial state of bit values.

4. The device according to claim 3, wherein the at least one appended bit has a predetermined value.

5. The device according to claim 3, wherein the encoder further is configured to append L1K fixed bits, f.sub.0, . . . , f.sub.L-2-K, to the information word c to obtain the appended information word c according to: $c_{{}_k}^{}=\{\begin{array}{cc}{c}_k,& k=0,\mathrm{.Math.},K-1\\ f_{k-K},& k=K,\mathrm{.Math.},L-2\end{array}$ where =[.sub.0, . . . , .sub.L-2] is a permutation of integers [0, . . . , L2].

6. The device according to claim 3, wherein the device is configured to: input the appended information word c to the encoder to encode the K information bits.

7. The device according to claim 3, wherein the at least one appended bit is obtained from a cyclic extension of the information word c.

8. The device according to claim 7, wherein the initial state of bit values are:
s.sub.i=c.sub.(K-1-i)mod K, i=0, . . . , L1 where (K1i)mod K is the smallest non-negative integer that can be expressed as (K1i)+pK for an integer p.

9. The device according to claim 7, wherein the device further is configured to: input the information word c to the encoder to encode the K information bits.

10. The device according to claim 2, wherein the encoder comprises a shift register of length L1 for encoding the K information bits, and wherein the initial state of the bit values in the shift register s=[s.sub.0, s.sub.1, . . . , s.sub.L-2], is the same as the final state of the bit values in the shift register.

11. A device, comprising: a decoder comprising a tail biting convolutional code having a constraint length, wherein L represents a length of the constraint length of the tail biting convolutional code, the decoder being configured to: receive an input sequence; compute at least one reliability parameter based on the received input sequence; and determine an information word c using the tail biting convolutional code and based on the at least one reliability parameter, wherein the information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] has K information bits c.sub.i, wherein K represents a number of information bits c.sub.i, K is less than L minus 1.

12. The device according to claim 11, wherein the decoder further is configured to compute the at least one reliability parameter based on: the received input sequence; and information comprising an initial state of bit values and a final state of bit values used in encoding the K information bits.

13. A method comprising: receiving, by an encoder, K information bits c.sub.i of an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1], wherein K represents a number of information bits c.sub.i received; and encoding, by the encoder, the K information bits using a tail biting convolutional code to provide an encoded code word, wherein the tail biting convolutional code has a constraint length, L represents a length of the constraint length of the tail biting convolutional code, and K is less than L minus one.

14. The method according to claim 13, further comprising: appending at least one bit to the information word c to obtain an appended information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] having KL1 bits; and using the appended information word c as an initial state of bit values to encode the K information bits.

15. The method according to claim 14, wherein the at least one appended bit has a predetermined value.

16. The method according to claim 14, wherein the at least one appended bit is obtained from a cyclic extension of the information word c.

17. The method according to claim 16, wherein the initial state of bit values are:
s.sub.i=c.sub.(K-1-i)mod K, i=0, . . . , L1 where (K1i)mod K is the smallest non-negative integer that can be expressed as (K1i)+pK for an integer p.

18. A method, comprising: receiving, by a decoder, an input sequence; computing, by the decoder, at least one reliability parameter based on the received input sequence; and determining, by the decoder, an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] using a tail biting convolutional code and based on the at least one reliability parameter, wherein the information word c has K information bits c.sub.i, K is a number of information bits c.sub.i, the tail biting convolutional code has a constraint length, L represents a length of the constraint length of the tail biting convolutional code, and K is less than L minus one.

19. The method according to claim 18 further comprising: computing the at least one reliability parameter based on the received input sequence and information comprising an initial state of bit values and a final state of bit values used in encoding the K information bits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The appended drawings are intended to clarify and explain different embodiments of the present application, in which:

(2) FIG. 1 shows a device for encoding (encoder device) according to an embodiment of the present application;

(3) FIG. 2 shows a method according to an embodiment of the present application;

(4) FIG. 3 shows a further embodiment of a device for encoding to the present application;

(5) FIG. 4 shows an appended control information word;

(6) FIG. 5 shows another appended control information word;

(7) FIG. 6 shows a device for determining an information word (decoder device) according to an embodiment of the present application;

(8) FIG. 7 shows another method according to an embodiment of the present application; and

(9) FIG. 8 shows a wireless communication system according to an embodiment of the present application.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(10) FIG. 1 shows a device 100 for encoding information words according to an embodiment of the present application. The device 100 comprises an encoder 102. The present device 100 is configured to encode one or more information words c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] having K information bits, c.sub.i, by using an encoder 102 for a tail biting convolutional code having a constraint length L, where K<L1. Therefore, the encoder 102 of the device 100 is configured to receive the K information bits of an information word as illustrated with the arrow pointing to the encoder 102 (note the encoder input is not shown in FIG. 1). The encoder 102 is further configured to encode the K information bits so as to provide an encoded code word. Further, the encoder 102 is configured to output the encoded code word which is illustrated with the arrow pointing away from the encoder 102.

(11) FIG. 2 shows a corresponding method which may be implemented in a device for encoding 100, such as the one shown in FIG. 1. The method 200 comprises the step of receiving 202 the K information bits. The method 200 further comprises the step of encoding 204 the K information bits so as to provide an encoded code word. The method 200 may also comprise the optional step of outputting 206 the encoded code word as illustrated with the dotted box in FIG. 2.

(12) Furthermore, the information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] to be encoded is at least one of control information, data information, cyclic redundancy check bits, and padding bits. The information words for encoding may relate to different content. For example, data and/or control information for uplink transmissions or downlink transmissions in cellular communication systems, such as LTE. Further, the information word may also comprise cyclic redundancy check bits for improving the decoding performance. Also, other padding bits not used for carrying data or control information may be comprised in the information words.

(13) According to an embodiment the encoder 102 comprises an initial state of bit values and a final state of bit values used in the encoding of the K information bits, and the initial state of bit values is the same the final state of bit values.

(14) The present encoder 102 of the device 100 may be a software implementation, a hardware implementation, or a combination thereof.

(15) In the case of a software implementation the encoding is performed by a processor (not shown in FIG. 1), such as a Digital Signal Processor (DSP). A digital signal processor may implement the encoder in different ways, since a convolutional code could be represented, e.g., as a linear filter, a set of difference equations or a generator matrix well known in the art.

(16) In the case of a hardware implementation a shift register for convolutional codes may be used for encoding. Hence, in this embodiment the encoder 102 comprises a shift register 104 of length L1, where K<L1, for encoding the K information bits. The initial state of the bit values of the shift register 104, s=[s.sub.0, s.sub.1, . . . , s.sub.L-2], is the same as the final state of the bit values in the shift register 104 as explained above.

(17) FIG. 3 shows an example of such a shift register 104 comprising inter-coupled delays and adders. The shift register 104 in the example in FIG. 3 uses the generator polynomials of LTE in octal representation but is not limited thereof. The information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] at the encoder 102 input consists of K bits. We denote the shift register of the encoder 102 by s=[s.sub.0, s.sub.1, . . . , s.sub.L-2]. Here, L is the constraint length of the encoder 102, which corresponds to the number of memory bits in the shift register plus 1. We have L=7 for the encoder 102 shown in FIG. 3. It is however realized that L may have another value.

(18) The encoding procedure in FIG. 3 using the shift register 104 is defined as follows.

(19) In the first step, the initial values of the shift register is set to
s.sub.i=c.sub.(K-1-i), i=0, . . . , L2;(1)

(20) In the second step, the information word c is sent to the encoder 102 as encoder input which generates three encoded output streams d.sub.k.sup.(0), d.sub.k.sup.(1) and d.sub.k.sup.(2), in this particular example. The total number of coded bit obtained after encoding is therefore N=3K and the rate of the code is

(21) $R_c=\frac{K}{N}=1/3.$

(22) Using the shift register initialization values defined in equation (1), only information words with length KL1 bits can be encoded because, when the input word has K<L1 bits, the shift register initial values s.sub.K, . . . , s.sub.L-2 are not defined.

(23) A solution is to extend the information word c with additional appended bits until the minimum length L1 bits is reached, and then send the appended word to the encoder 102 input. This solution has the advantage of being simple to implement. However, the number of coded bits obtained after encoding would be 3 (L1) independently of the value of K, therefore the code rate would be

(24) $R_c=\frac{K}{3\left(L-1\right)}<1/3.$

(25) Therefore, in the following embodiments of the present application the encoder 102 is further configured to append at least one bit to the information word c so as to obtaining an appended information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1] having KL1 bits. Further, the encoder 102 is configured to using the appended information word c as the initial state of bit values for the encoding of the information word c.

(26) According to an approach corresponding to an embodiment, K<L1 information bits are available at the encoder 102 input and at least one appended bit has a predetermined value and possibly a fixed position.

(27) In the first step the information word c is appended (padded) with L1K fixed bits f.sub.0, . . . , f.sub.L-2-K (e.g., f.sub.0= . . . =f.sub.L-2-K=0) so as to obtain an appended information word c=[c.sub.0, c.sub.1, . . . , c.sub.L-2] using

(28) $\begin{array}{cc}{c}_{{}_k}^{}=\{\begin{array}{cc}{c}_k,& k=0,\mathrm{.Math.},K-1\\ f_{k-K},& k=K,\mathrm{.Math.},L-2\end{array}& \left(2\right)\end{array}$
where =[.sub.0, . . . , .sub.L-2] is a permutation of integers [0, . . . , L2].

(29) In a second step, the L1 bits in the appended information word c are used to set the initial value of the shift register according to equation (1).

(30) In a third step, the appended information word c is sent as input to the encoder 102 and three encoded output streams d.sub.k.sup.(0), d.sub.k.sup.(1) and d.sub.k.sup.(2) are generated in this particular example.

(31) FIG. 4 shows the appended information word according to this embodiment with the fixed bits f.sub.0= . . . =f.sub.L-2-K=0 and where =[0, 1, . . . , L2]. The device 100 is here configured to input the appended information word c to the encoder 102 so as to encode the K information bits according to this embodiment.

(32) These embodiments have the advantages of providing a simple way to use the existing encoder 102 also when K<L1 control information bits are available at the encoder 102 input. Therefore, the same encoder 102 could be used as for KL1. Moreover, it has the advantage that the fixed bits and their positions are known at the encoder 102 and decoder 302 (see FIG. 6), thereby allowing the receiver to exploit their knowledge to improve the reliability of transmission.

(33) An alternative solution to appending with fixed bit values is to initialize the encoder 102 of length L1 using the K<L1 input bits of the information word in a way that, after encoding the K<L1 input bits, the encoder 102 has the same state as the initial state, thereby resulting in a tail-biting codeword. In this way, N=3K coded bits would be obtained and the resulting code rate would be R.sub.c=1/3. This solution is detailed in the following.

(34) According to this embodiment, K<L1 information bits are available at the encoder 102 input.

(35) In a first step, the shift register is initialized as
s.sub.i=c.sub.(K-1-i)mod K, i=0, . . . , L1.(3)
where (K1i)mod K is the remainder of (K1i)/K.

(36) In a second step, the K information bits are sent to the encoder 102 and three encoded output streams d.sub.k.sup.(0), d.sub.k.sup.(1) and d.sub.k.sup.(2) are generated in this particular example.

(37) FIG. 5 shows the shift register initialization proposed in this embodiment according to equation (3). The device 100 is further is configured to input the information word c to the encoder 102 so as to encode the K information bits according to this embodiment.

(38) This embodiment has the advantage of providing a way to initialize the shift register 104 of length L1 when K<L1 information bits are available at the encoder 102 input. Moreover, it has the advantage that, after the K<L1 information bits have been processed by the encoder 102, the final encoder state coincides with the initial state defined in equation (2), thereby resulting in a valid codeword of the tail-biting convolutional code. Therefore, a standard tail-biting decoder can be used at the receiver as. Furthermore, with this embodiment encoding short information words yields the same code rate as encoding long information words.

(39) A decoder 302 corresponding to the encoder 102 of the previous embodiments would utilize knowledge of the structure of the tail biting convolutional code (e.g., the generator polynomials, the number of information bits) in the decoding. The decoder 302 takes an input sequence and applies a decoding algorithm on the input sequence. The input sequence may consist of bits (e.g., used for hard decoding) or log-likelihood ratios (e.g., used for soft decoding). The input sequence can comprise a codeword from the encoder 102. However, the decoder 302 can produce an information word for any input sequence and may not need to assume that the input sequence comprises a codeword.

(40) The disclosed application is applicable to different kinds of decoding algorithms. For example, maximum likelihood decoding could be achieved by using the Viterbi algorithm, while maximum aposteriori decoding could be utilized by using the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. In both cases, the decoding algorithm, would assume that the initial state of the encoder was the same as the final state of the encoder 102 and based on some reliability measure or parameter, the decoding algorithm will determine the most probable codeword or information word, based on this constraint. Reliability parameters (or measures) could include a Hamming distance, a log-likelihood ratio, or the like, which is well known in the art.

(41) FIG. 6 shows a device 300 for determining an information word (decoder device) according to an embodiment of the present application. The device 300 is configured to determine an information word c=[c.sub.0, c.sub.1, . . . , c.sub.K-1], having K information bits, c.sub.i, corresponding to the encoding at the encoder 102. The device 300 comprising a decoder 302 for a tail biting convolutional code having a constraint length, L, and where K<L1. The decoder 302 is configured to receive an input sequence illustrated with the rightwards directed arrow to the decoder 302. The decoder 302 is further configured compute at least one reliability parameter based on the received input sequence. Finally, the decoder 302 is configured to determine an information word c based on the at least one reliability parameter.

(42) FIG. 7 shows a corresponding method which may be implemented in a device 300 for decoding, such as the one shown in FIG. 6. The method 400 comprises the step of receiving 402 an input sequence. The method 400 further comprises the step of computing 404 at least one reliability parameter based on the received input sequence. The method 400 finally comprises the step of determining 406 an information word c based on the at least one reliability parameter.

(43) In an embodiment the decoder 302 is further configured to compute the at least one reliability parameter based on the received input sequence and on information comprising initial state of bit values and final state of bit values used in the encoding of the K information bits at the encoder 102. Such information could be pre-determined (e.g., rules could be defined on how the encoder is setting the initial state of the bit values, i.e., how the appended information word is generated) or be signalled to the decoder. By using information about the initial state of bit values and final state of bit values improved decoding performance is provided.

(44) In a further embodiment for improved decoding performance the information used for computing the at least one reliability parameter further comprises at least one bit in the initial state of bit values and the position of the at least one bit in the initial state of bit values. This embodiment relates to the case when the encoding has been performed with an appended code word c in which at least one appended bit has a predetermined value. For example if N of the bits in the initial state of the shift register s.sub.i, i=0, . . . , L1 are known (i.e., their values and positions), the number of states could be reduced from 2.sup.L to 2.sup.N. This reduces the search space for the decoding algorithm and eliminates a number of false candidate states, which improves the decoding performance.

(45) In an alternative of the embodiment for improved decoding performance the information used for computing the at least one reliability parameter further comprises that at least two bits in the initial state of bit values have the same value and that one of the two bits in the initial state of bit values is obtained from a cyclic extension of the information word c. This embodiment relates to the case when the encoding has been performed with an appended code word c in which the at least one appended bit is obtained from a cyclic extension of the information word c. For example if N of the bits in the initial state of the shift register s.sub.i, i=0, . . . , L1 are obtained from a cyclic extension of the information word, the last N bits in the shift register are the same as the first N bits in the shift register. Hence, the number of states could be reduced from 2.sup.L to 2.sup.N. This reduces the search space for the decoding algorithm and eliminates a number of false candidate states, which improves the decoding performance.

(46) FIG. 8 shows a wireless communication system 500, such as LTE, according to an embodiment of the present application. A user device 502 (the transmitter device in this example) comprises a device 100 for encoding according to embodiments of the present application. Information words c are encoded by the device 100 for encoding. The encoded word is thereafter signal processed in the user device 502, such as modulation, amplification, etc., and transmitted in a communication signal S in an uplink channel in the wireless communication system 500 to a base station 504 (the receiver device in this example) as illustrated in FIG. 8. The base station 504 comprises a decoder device 300 according to embodiments of the present application. The base station 504 receives the communication signal in the uplink channel. After suitable signal pre-processing an input sequence is provided to the decoder device 300 which decodes the input sequence as explained previously.

(47) It is to be noted that the user device 502 may also comprise a device 300 for decoding. The base station 504 may also comprise a device for encoding 100.

(48) The present transmitter or receiver in the form of a user device 502 discussed in the present disclosure may be any of a User Equipment (UE), mobile station (MS), wireless terminal or mobile terminal which is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system. The UE may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability. The UEs in the present context may be, for example, portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile devices, enabled to communicate voice or data, via the radio access network, with another entity, such as another receiver or a server. The UE can be a Station (STA), which is any device that contains an IEEE 802.11-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).

(49) The present transmitter or receiver in the form of a base station 504 may be a (radio) network node or an access node or an access point or a base station, e.g., a Radio Base Station (RBS), which in some networks may be referred to as transmitter, eNB, eNodeB, NodeB or B node, depending on the technology and terminology used. The radio network nodes may be of different classes such as, e.g., macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size. The radio network node can be a Station (STA), which is any device that contains an IEEE 802.11-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).

(50) Furthermore, any method 200 or 400 according to embodiments of the present application may be implemented in a computer program, having code means, which when run by processing means causes the processing means to execute the steps of the method. The computer program is included in a computer readable medium of a computer program product. The computer readable medium may comprises of essentially any memory, such as a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable PROM), a Flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

(51) Moreover, it is realized by the skilled person that the user device and base station comprise the necessary communication capabilities in the form of e.g., functions, means, units, elements, etc., for performing the present solution. Examples of other such means, units, elements and functions are: processors, memory, buffers, control logic, encoders, decoders, rate matchers, de-rate matchers, mapping units, multipliers, decision units, selecting units, switches, interleavers, de-interleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiver units, transmitter units, DSPs, MSDs, TCM encoder, TCM decoder, power supply units, power feeders, communication interfaces, communication protocols, etc. which are suitably arranged together for performing the present solution.

(52) Especially, the processors of the present user device and base station may comprise, e.g., one or more instances of a Central Processing Unit (CPU), a processing unit, a processing circuit, a processor, an Application Specific Integrated Circuit (ASIC), a microprocessor, or other processing logic that may interpret and execute instructions. The expression processor may thus represent a processing circuitry comprising a plurality of processing circuits, such as, e.g., any, some or all of the ones mentioned above. The processing circuitry may further perform data processing functions for inputting, outputting, and processing of data comprising data buffering and device control functions, such as call processing control, user interface control, or the like.

(53) Finally, it should be understood that the present application is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.