TEST VEHICLE AND TEST METHOD FOR MICROELECTRONIC DEVICES

Abstract

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

Claims

1. A test structure for a buried gate transistor, said transistor comprising: a substrate, a gate having a part buried in the substrate, a gate dielectric electrically insulating the gate from the substrate, a first transistor contact located on a first side of the gate and having a first end connecting a conduction path in the substrate, a second transistor contact located on a second side of the gate, opposite the first side, and having a second end connecting the conduction path in the substrate, said test structure comprising: a first test contact located on a side of the first transistor contact opposite the gate, a second test contact located on a side of the second transistor contact opposite the gate, a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3 and having a face which is tangent to the buried part of the gate, a first insulation structure configured to electrically insulate the first test contact and the first transistor contact from each other, and a second insulation structure configured to electrically insulate the second test contact and the second transistor contact from each other, wherein the first and second test contacts each have an end connected to the buried layer.

2. The test structure according to claim 1, wherein the first and second insulation structures respectively comprise first and second amorphous zones.

3. The test structure according to claim 1, wherein the first and second insulation structures respectively comprise first and second wells based on a dielectric material.

4. The test structure according to claim 1, wherein the first and second insulation structures respectively comprise first and second gates disposed on a surface of the substrate.

5. The test structure according to claim 1, wherein the face of the buried layer passes within the gate dielectric located at an end of the buried gate.

6. The test structure according to claim 1, wherein the buried gate transistor comprises a barrier layer on the substrate configured to form a two-dimensional electron gas (2DEG) confined under the barrier layer in the substrate, wherein the 2DEG gas forms the conduction path, the first and second transistor contacts passing through said hairier layer.

7. The test structure according to claim 6, wherein the substrate is GaN-based and the buried layer is N-doped GaN-based.

8. The test structure according to claim 1, wherein the buried layer has a thickness greater than or equal to 100 nm.

9. The test structure according to claim 1, wherein the first and second transistor contacts are symmetrically disposed on either side of the gate, and wherein the first and second test contacts are symmetrically disposed on either side of the gate.

10. A test method using a test structure according to claim 1, comprising: polarising the gate at a gate voltage of between 0 and 15V, positively polarising the first test contact vis-à-vis the first transistor contact, without polarising the second test contact nor the second transistor contact, so as to determine a first resistance value along a first side of the buried part of the gate, and negatively polarising the second test contact vis-à-vis the second transistor contact, without polarising the first test contact nor the first transistor contact, so as to determine a second resistance value along a second side of the buried part of the gate.

11. The method according to claim 10, further comprising: positively polarising the first test contact vis-à-vis the second test contact, without polarising the first and second transistor contacts nor the gate, so as to determine a resistance value along the buried layer between the first and second test contacts.

12. The method according to claim 10, wherein the first and second insulation structures respectively comprise first and second gates disposed on the surface of the substrate, further comprising: during the determination of the first resistance value, negatively polarising the first gate of the first insulation structure below a first threshold voltage so as to block an electrical current flow between the first test contact and the first transistor contact (21), and during the determination of the second resistance value, negatively polarising the second gate of the second insulation structure below a second threshold voltage so as to block an electrical current flow between the second test contact and the second transistor contact.

13. The test structure according to claim 1, wherein the layer buried in the substrate has a doping between 10.sup.19 and 10.sup.20 cm.sup.−3.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0044] The aims, objectives, as well as the features and advantages of the invention will best emerge from the detailed description of embodiments of the latter, which are illustrated by the following accompanying drawings, wherein:

[0045] FIG. 1 schematically illustrates a buried gate transistor according to an embodiment of the present invention. The resistances along different portions of the conduction path are indicated.

[0046] FIG. 2 schematically illustrates a test structure according to an embodiment of the present invention.

[0047] FIG. 3 schematically illustrates a first conduction path in the test structure illustrated in FIG. 2, according to an embodiment of the present invention.

[0048] FIG. 4 schematically illustrates another conduction path in a test structure according to an embodiment of the present invention.

[0049] FIG. 5 schematically illustrates a test structure according to another embodiment of the present invention.

[0050] FIG. 6 schematically illustrates a first conduction path in the test structure illustrated in FIG. 5, according to an embodiment of the present invention.

[0051] The drawings are given as examples and are not limiting of the invention. They constitute principle schematic representations intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, in the principle diagrams, the thicknesses of the different layers, and the dimensions of the different patterns (gate, source, drain, etc,) are not representative of reality.

DETAILED DESCRIPTION

[0052] Before starting a detailed review of embodiments of the invention, optional features are stated below which can optionally be used in association or alternatively:

[0053] According to an example, the first and second insulation structures respectively comprise first and second amorphous zones.

[0054] According to an example, the first and second insulation structures respectively comprise first and second wells based on a dielectric material.

[0055] According to an example, the first and second insulation structures respectively comprise first and second gates disposed on the surface of the substrate. These gates are typically separated from the surface of the substrate by a dielectric layer. They are not necessarily directly in contact with the surface of the substrate.

[0056] According to an example, the face of the buried layer passes within the gate dielectric under an end of the buried gate. This face is configured to be in the immediate proximity of the bottom end of the gate, typically at the portion of the conduction path corresponding to R.sub.Channel. At close manufacturing tolerances, this face can be substantially tangent to the bottom end of the gate or at the bottom end of the gate dielectric, or between the two planes containing these two bottom ends, within the gate dielectric.

[0057] According to an example, the buried gate transistor comprises a barrier layer on the substrate configured to form a two-dimensional electron gas (2DEG) confined under said barrier layer, in the substrate.

[0058] According to an example, the 2DEG gas forms the conduction path, the first and second transistor contacts passing through said barrier layer.

[0059] According to an example, the substrate is GaN-based, and the buried layer is N doped GaN-based.

[0060] According to an alternative example, the substrate is silicon- or silicon carbide-based.

[0061] According to an example, the buried layer has a thickness e.sub.30 greater than or equal to 100 nm.

[0062] According to an example, the first and second transistor contacts are disposed symmetrically on either side of the gate.

[0063] According to an example, the first and second test contacts are disposed symmetrically on either side of the gate.

[0064] According to an example, the method further comprises: [0065] Positively polarising the first test contact vis-à-vis the second test contact, without polarising the first and second transistor contacts nor the gate, so as to determine a resistance value, typically 2.RCT+2.Rdop, of the layer buried between the first and second test contacts.

[0066] According to an example, the method further comprises: [0067] During the determination of the first resistance value RT1, negatively polarising the first gate of the first insulation structure, below a first threshold voltage Vth1, so as to block an electrical current flow between the first test contact and the first transistor contact, [0068] During the determination of the second resistance value RT2, negatively polarising the second gate of the second insulation structure, below a second threshold voltage Vth2, so as to block an electrical current flow between the second test contact and the second transistor contact.

[0069] Unless incompatible, technical features described in detail for a given embodiment can be combined with the technical features described in the context of other embodiments described as an example and in a non-limiting manner, so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0070] In the scope of the present invention, the power transistor architectures considered are typically buried gate in the substrate. Some of these architectures are more specifically based on a principle of conduction by two-dimensional electron gas (2DEG).

[0071] Such a transistor architecture includes the superposition of two semi-conductive layers having different band gaps which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional electron gas.

[0072] HEMT (High Electron Mobility Transistor)-type transistors, sometimes also called heterostructure field effect transistors, are examples of transistors based on this two-dimensional electron gas architecture.

[0073] For power (in particular, high voltage) and temperature holding reasons, the semi-conductive material of these transistors is preferably chosen so as to have a wide energy band gap. From among wide energy band gap HEMT transistors, gallium nitride-based transistors are generally preferred.

[0074] In the scope of the present invention, the flow of the current is typically controlled by a gate positively polarised with respect to the source.

[0075] This gate can be of the MOS or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type, or also more generally, MIS or MISFET (Metal Insulator Transistor) type. In this case, the metal gate is electrically insulated from the semi-conductive layers by a gate dielectric. Other gate compositions can be considered. A particularity of the transistor architectures according to the present invention is that the gate passes through the quantum well at which the two-dimensional electron gas is confined. The continuity of the two-dimensional electron gas is thus broken by a trench, wherein the MOS gate of the transistor is produced.

[0076] Generally, if the gate of the transistor is put at a voltage greater than a threshold voltage, the source and the drain are connected by the two-dimensional electron gas and the transistor is called on.

[0077] If the gate of the transistor is put at a voltage less than the threshold voltage, the source and the drain are no longer connected and the transistor is called off.

[0078] The buried gate HEMT transistors considered in the scope of the invention are preferably in the off state when the gate is not polarised. This type of transistor operation is commonly called “normally off”.

[0079] It is specified that, in the scope of the present invention, the terms “on”. “surmounts”, “covers”, “underlying”. “vis-à-vis” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition of a first layer on a second layer, does not compulsorily mean that the two layers are directly in contact with one another, but means that the first layer covers at least partially the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0080] For example, and in a manner known per se, in the field of GaN-based HEMT-type transistors, a thin AlN layer can be inserted between two GaN and AlGaN semi-conductive layers.

[0081] A layer can moreover be composed of several sub-layers of one same material or of different materials.

[0082] By a substrate, a stack, a layer, “based on” a material A or “A-based”, this means a substrate, a stack, a layer comprising this material A only or this material A and optionally other materials, for example alloy elements and/or doping elements.

[0083] The doping ranges associated with the different doping types indicated in the present application are as follows: [0084] p++ or n++ doping: greater than 1×10{circumflex over ( )}20 cm.sup.−3 [0085] p+ or n+ doping: 1×10{circumflex over ( )}18 cm.sup.−3 to 9×10{circumflex over ( )}19 cm.sup.−3 [0086] p or n doping: 1×10{circumflex over ( )}17 cm.sup.−3 to 1×10{circumflex over ( )}18 cm.sup.−3 [0087] intrinsic or unintentionally doped doping: 1.Math.10{circumflex over ( )}15 cm.sup.−3 to 1.Math.10{circumflex over ( )}17 cm.sup.−3

[0088] A preferably orthonormal marker, comprising the axes x, y, z is represented in the accompanying figures. When only one marker is represented in one same set of figures, this marker applies to all the figures of this set.

[0089] In the present patent application, the thickness of a layer is taken in a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms “on”, “surmounts”, “under”, “underlying” refer to positions taken in the direction z.

[0090] The terms “vertical”, “vertically” refer to a direction along z. The terms “horizontal”, “horizontally” refer to a direction in the plane xy.

[0091] An element located “in vertical alignment with” or “to the right of” another element means that these two elements are both located on one same line perpendicular to a plane wherein a lower or upper face of a substrate mainly extends, i.e. on one same line oriented vertically in the figures.

[0092] An example of a buried gate transistor 2 according to the present invention is illustrated in FIG. 1. The general architecture of this HEMT-type transistor 2 comprises a first contact, for example a source 21 and a second contact, for example a drain 22 formed on either side of a gate pattern or gate 23. The gate 23 extends partially through a stack of layers 32, 31, until the substrate 20. This transistor 2 is based on a principle of conduction by two-dimensional electron gas (2DEG). Other types of buried gate transistors can also be considered.

[0093] The substrate 20 can be a GaN-based substrate. Known GaN on sapphire or GaN on silicon substrates can typically be used. The support 10 can thus comprise, in a known manner, a silicon bulk part and one or more buffer layers inserted between the silicon part and the GaN-based substrate 20. The substrate 20 is typically unintentionally doped.

[0094] A barrier layer 31, typically AlGaN-based, is directly disposed on the surface 200 of the substrate 20. This barrier layer 31 has a thickness, for example, of between 20 nm and 100 nm.

[0095] In a known manner, a two-dimensional electron gas is formed under the AlGaN-based barrier layer 31, in the GaN-based substrate 20. The two-dimensional electron gas 2DEG is typically confined at the interface between the AlGaN-based barrier layer 31 and the GaN-based substrate 20. This two-dimensional electron gas 2DEG forms a conduction path (C) in the substrate 20.

[0096] A dielectric layer 32, for example silicon nitride SiN-based, is typically disposed on the barrier layer 31.

[0097] An encapsulation layer 33, for example silicon oxide SiO2-based, can be typically formed on the layer 32, between the contacts 21, 22 and the gate 23, so as to insulate the contacts and the gate together, and to flatten the structure.

[0098] In a known manner, the stack of layers 31, 32 at the surface 200 of the substrate 20 can comprise other layers, for example a thin AlN-based layer between the substrate 20 and the barrier layer 31.

[0099] The gate 23 is typically disposed on this stack of layers 31, 32, and comprises a part 24 passing through the stack and extending until the substrate 20, called buried part 24. The buried part 24 of the gate 23 has a lower end 240, and this lower end 240 is located at a depth d20 along z, in the substrate 20, with respect to the surface 200 of the substrate 20. The end 240 can be located at a depth d20 of between 20 nm and 100 nm. The buried part 24 of the gate 23 typically has a first side 241, for example substantially vertical, and a second side 242, for example substantially vertical, under the surface 200 of the substrate 20. The gate 23, 24 can be with the basis of a metal alloy, for example gold- and/or platinum- and/or titanium-based.

[0100] A gate dielectric 25 typically separates the gate 23, 24 from the stack of layers 31, 32 and from the substrate 20. This gate dielectric 25 is, for example, alumina Al2O3-based, and has a thickness of around a few nanometres to a few tens of nanometres, for example around 30 nm.

[0101] The buried part 24 of the gate 23 is configured to cut off the two-dimensional electron gas along the conduction path (C). Controlling the gate voltage Vg makes it possible to enable or block the flow of the electrons of the two-dimensional electron gas on either side of the gate 23. The gate voltage Vg making it possible to enable the flow of the electrons is, in this case, typically positive, for example of between 0V and 15V. According to an example, the gate voltage Vg making it possible to enable the flow of the electrons is of between 0V and 6V. In the absence of polarisation of the gate 23, this type of transistor 2 is configured such that the flow of the electrons is blocked. This type of transistor 2 is called “normally off”.

[0102] The source and drain contacts 21, 22 respectively have an end 210, 220 directly in contact with the substrate 20. The first transistor contact 21 is typically located on the side of the first side 241, and the second transistor contact 22 is typically located on the side of the second side 242.

[0103] The total resistance R.sub.on of the transistor 2 can be broken down along the different portions of the conduction path (C) from the source 21 up to the drain 22, as follows:

R.sub.on=R.sub.C1+R.sub.2DEG1+R.sub.T1+R.sub.Channel+R.sub.T2+R.sub.2DEG2+R.sub.C2

[0104] With R.sub.C1 the contact resistance at the first contact 21, R.sub.2DEG1 the resistance in the 2DEG gas between the first contract 21 and the buried part 24 of the gate 23, R.sub.T1 the resistance along the first side 241 of the buried part 24 of the gate 23, R.sub.Channel the resistance under the end 240 of the buried part 24 of the gate 23, R.sub.T2 the resistance along the second side 242 of the buried part 24 of the gate 23, R.sub.2DEG2 the resistance in the 2DEG gas between the buried part 24 of the gate 23 and the second contact 22, and R.sub.C2 the contact resistance at the second contact 22.

[0105] As illustrated in FIG. 2, a test structure 1 dedicated to measuring components R.sub.T1, R.sub.T2 of the transistor 2 is proposed.

[0106] The test structure 1 typically comprises first and second test contacts 11, 12, and a layer 30 buried in the substrate 20. The first and second test contacts 11, 12 typically flank the transistor 2. In particular, the test structure 1 is configured such that the gate 23, 24 and the transistor contacts 21, 22 are located between the first and second test contacts 11, 12.

[0107] In this configuration, the first transistor contact 21 is located between the first test contact 11 and the gate 23. The second transistor contact 22 is located between the second test contact 12 and the gate 23.

[0108] The first and second test contacts 11, 12 extend into the substrate 20 up to the buried layer 30. They each have an end 110, 120 located within the buried layer 30. The first and second test contacts 11, 12 are respectively electrically insulated vis-à-vis the first and second transistor contacts 21, 22, by insulation structures 41, 42.

[0109] The buried layer 30 is electrically conductive. It is typically with the basis of a highly doped semiconductor, typically having a doping greater than 10.sup.18 cm.sup.−3, for example of between 10.sup.19 and 10.sup.20 cm.sup.−3. Thus, for a GaN-based substrate 20, an n+ or n++ doped GaN-based buried layer 30 is advantageously chosen, in order to preserve the crystalline quality of the substrate 20. Such a layer 30 can be produced during the epitaxy of the substrate 20 by Metal Organic Chemical Vapour Deposition (MOCVD) growth, typically by incorporating silicon. Silicon is an n-type dopant (donor atoms) for GaN. The doping of GaN by silicon can be done during growth at 1050° C., without it being necessary to perform activation annealing. The buried layer 30 has a thickness e.sub.30 along z, preferably greater than 100 nm, for example of between 100 and 400 nanometres. The resistances R.sub.dop1, R.sub.dop2, linked to this layer 30 are lower than the doping is high, and lower than the thickness e.sub.30 is thick.

[0110] The buried layer 30 has an upper face 301 configured to make the end 240 tangent to the buried part 24 of the gate 23. According to a possibility, the face 301 passes within the dielectric 25 located under the end 240 of the gate. According to another possibility, the face 301 is tangent to the end 250 of the gate dielectric 25. The positioning of the face 301 of the layer 30 is chosen such that the layer 30 intercepts the conduction path of the transistor 2, at the lowest portion of the conduction path corresponding to R.sub.Channel. The tangential position of this face 301 vis-à-vis the end of the gate 24 or of the gate dielectric 25 makes it possible to preserve all or most of the portions of the conduction path corresponding to R.sub.T1, R.sub.T2 along the sides 241, 242 of the buried part 24 of the gate. This makes it possible to improve the precision on measuring the values R.sub.T1, R.sub.T2. The precision on the positioning in depth of the face 301 vis-à-vis of the ends 240, 250 is typically of around a few nanometres, for example less than 5 nm, and preferably less than 2 nm.

[0111] According to a possibility, the test structure 1 comprising the transistor 2 has a symmetry with respect to the gate 23. As illustrated in FIG. 2, the transistor contacts 21, 22 are preferably equidistant from the gate 23. In this case, R.sub.2DEG1≈R.sub.2DEG2. The test contacts 11, 12 are preferably equidistant from the gate 23. In this case, R.sub.dop1≈R.sub.dop2.

[0112] The insulation structures 41, 42 are configured to respectively electrically insulate the test contacts 11, 12 vis-à-vis the transistor contacts 21, 22. Several embodiments of these insulation structures 41, 42 are described below.

[0113] FIG. 3 illustrates an embodiment where the insulation structures 41, 42 are typically formed by argon implantation through the layers 31, 32, until the substrate 20. This implantation is configured to locally amorphise the zones 410, 420 extending through the layers 31, 32, and partially in the substrate 20 over a depth greater than the confinement thickness of the 2DEG. Thus, the two-dimensional electron gas is destroyed at the insulation zones 41, 42. There is therefore no conduction path between the first test contact 11 and the first transistor contact 21 on the one hand, and between the second test contact 12 and the second transistor contact 22 on the other hand. Such an implantation can be achieved via an implantation energy of several tens of keV, typically around 60 keV.

[0114] FIG. 4 illustrates another embodiment where the insulation structures 41, 42 are formed by insulation wells 411, 421. As above, these wells 411, 421 are configured to extend through the layers 31, 32, and partially into the substrate 20 over a depth greater than the confinement thickness of the 2DEG. This makes it possible to locally remove the 2DEG and the conduction path between the test contacts and the transistor contacts. The wells 411, 421 can be formed by chemical etching, then filled by a dielectric material, for example SiO2 or SiN.

[0115] FIG. 5 illustrates another embodiment where the insulation structures 41, 42 are formed by transistors 412, 422 disposed at the surface 200 of the substrate 20. In this embodiment, it is not necessary to structure the substrate 20 under the surface 200. Typically, the gates of the transistors 412, 422 are formed on the layer 32, respectively between the first test contact 11 and the first transistor contact 21, and between the second test contact 12 and the second transistor contact 22. The transistors 412, 422 thus formed are typically of the “normally on” type. It is therefore possible to block the conduction between the first test contact 11 and the first transistor contact 21, and between the second test contact 12 and the second transistor contact 22, by negatively polarising the gates of the transistors 412, 422 below the threshold voltages Vth of these transistors 412, 422. The threshold voltages Vth of these transistors 412, 422 are typically around −8V. Thus, by polarising the gates of the transistors 412, 422 for example at Vgs=−15V with respect to the transistor contacts 21, 22, depleted zones 51, 52 appear and block the conduction under the gates of the transistors 412, 422.

[0116] The test structure 1 can advantageously be implemented in order to separately measure R.sub.T1 and R.sub.T2.

[0117] As illustrated in FIGS. 3 and 6 for different embodiments of the insulation structures 41, 42, by positively polarising the first test contact 11 vis-à-vis the first transistor contact 21, for example according to Vss>0.5V, a current I1 is established along the conduction path (C1) corresponding to the resistance portions R.sub.CT1, R.sub.dop1, R.sub.T1, R.sub.2DEG1, R.sub.C1. It is thus possible to determine the resistance R.sub.T1 along the side 241 of the buried part 24 of the gate 23, according to:

[00003]$R_{T1}=\frac{V_{\mathrm{SS}}}{I_1}-R_{2\mathrm{DEG}1}-R_{C1}-R_{\mathrm{CT}1}-R_{\mathrm{dop}1}$

[0118] The resistances R.sub.2DEG1, R.sub.C1 can be determined, moreover, for example according to the known methods mentioned above.

[0119] The sum of the resistances R.sub.dop1+R.sub.CT1 can be advantageously determined via the same test structure 1, by modifying the connections and polarisations of the different contacts 11, 21, 23, 22, 12.

[0120] As illustrated in FIG. 4, by positively polarising the first test contact 11 vis-à-vis the second test contact 12, for example with V1>0.5V and V2=0V, without polarising the transistor contacts 21, 22 and the gate 23, a current I is established along the conduction path (C0) corresponding to the portions of resistances R.sub.CT1, R.sub.dop1, R.sub.dop2, R.sub.CT2. It is thus possible to determine the sum of the resistances R.sub.dop1+R.sub.CT1+R.sub.dop2+R.sub.CT2, which, in the case of a symmetrical test structure, is substantially equal to 2.R.sub.CT+2.R.sub.dop, according to:

[00004]$\frac{V1-V2}{I}=R_{\mathrm{CT}1}+R_{\mathrm{dop}1}+R_{\mathrm{CT}2}+R_{\mathrm{dop}2}$

[0121] In the case of a symmetrical test structure as illustrated in FIG. 4, R.sub.dop1≈R.sub.dop2≈R.sub.dop and R.sub.CT1≈R.sub.CT2≈R.sub.CT.

[0122] It is thus possible to extract R.sub.dop1+R.sub.CT1 according to:

[00005]$R_{\mathrm{CT}1}+R_{\mathrm{dop}1}=R_{\mathrm{CT}}+R_{\mathrm{dop}}=\frac{V1-V2}{2I}$

[0123] The test structure 1 thus makes it possible to individually determine R.sub.T1.

[0124] Similarly, the test structure 1 makes it possible to individually determine R.sub.T2, by positively polarising the second test contact 12 vis-à-vis the second transistor contact 22 (not illustrated).

[0125] The invention is not limited to the embodiments described above.