Capacitive sensor readout circuit

Abstract

A capacitive sensor device is provided. The capacitive sensor device may include a clock module configured to generate a clock signal, a sensor module configured to generate a reference signal and a sense signal, and sample a difference between the reference signal and the sense signal according to the clock signal, and a current supply module configured to selectively generate a bias current according to the clock signal, and charge each of the clock module and the sensor module based on the bias current and according to the clock signal.

Claims

1. A method of sensing a change in capacitance sensitive to capacitive sensor input, comprising: generating a clock signal based on a first capacitance, a reference signal based on a second capacitance, and a sense signal based on a third capacitance; generating a bias current according to the clock signal, wherein the bias current is copied and multiplied by a predefined factor, and each of the first capacitance, the second capacitance, and the third capacitance is charged using the copied and multiplied bias current; charging each of the first capacitance, the second capacitance, and the third capacitance based on the bias current and according to the clock signal; and sampling a difference between the reference signal and the sense signal according to the clock signal.

2. The method of claim 1, wherein each of the first capacitance and the second capacitance is sized to be significantly smaller than the third capacitance.

3. The method of claim 1, wherein the bias current is generated only when charging each of the first capacitance, the second capacitance, and the third capacitance.

4. The method of claim 1, wherein the third capacitance varies in response to capacitive sensor input.

5. The method of claim 4, wherein the difference between the reference signal and the sense signal corresponds to a magnitude of the capacitive sensor input.

6. The method of claim 4, wherein the difference between the reference signal and the sense signal corresponds to a magnitude of the capacitive sensor input.

7. The method of claim 1, further outputting a digitized value corresponding to the difference between the reference signal and the sense signal.

8. The method of claim 7, wherein the digitized value corresponds to a magnitude of the capacitive sensor input and is independent of changes in the bias current.

9. The method of claim 7, wherein the digitized value corresponds to a magnitude of the capacitive sensor input and is independent of changes in the bias current.

10. The method of claim 1, further outputting a digitized value corresponding to the difference between the reference signal and the sense signal.

11. A non-transient computer-readable medium having stored thereon computer-executable instructions for sensing a change in capacitance sensitive to capacitive sensor input, the computer-executable instructions comprising instructions for: generating a clock signal based on a first capacitance, a reference signal based on a second capacitance, and a sense signal based on a third capacitance; generating a bias current according to the clock signal, wherein the bias current is copied and multiplied by a predefined factor, and each of the first capacitance, the second capacitance, and the third capacitance is charged using the copied and multiplied bias current; charging each of the first capacitance, the second capacitance, and the third capacitance based on the bias current and according to the clock signal; and sampling a difference between the reference signal and the sense signal according to the clock signal.

12. The method of claim 11, wherein each of the first capacitance and the second capacitance is sized to be significantly smaller than the third capacitance.

13. The method of claim 11, wherein the bias current is generated only when charging each of the first capacitance, the second capacitance, and the third capacitance.

14. The method of claim 11, wherein the third capacitance varies in response to capacitive sensor input.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic view of one exemplary capacitive sensor device or circuitry of the present disclosure;

(2) FIG. 2 is a diagrammatic view of one timing diagram of the capacitive sensor device of the present disclosure;

(3) FIG. 3 is a schematic view of another clock circuit that may be implemented with the capacitive sensor device of the present disclosure;

(4) FIG. 4 is a diagrammatic view of another timing diagram of the capacitive sensor device of the present disclosure;

(5) FIG. 5 is a schematic view of another sense circuit that may be implemented with the capacitive sensor device of the present disclosure;

(6) FIG. 6 is a schematic view of another sense circuit that may be implemented with the capacitive sensor device of the present disclosure;

(7) FIG. 7 is a schematic view of yet another sense circuit that may be implemented with the capacitive sensor device of the present disclosure; and

(8) FIG. 8 is a flow diagram of one exemplary scheme or method of sensing a change in capacitance sensitive to capacitive sensor input.

(9) While the following detailed description is given with respect to certain illustrative embodiments, it is to be understood that such embodiments are not to be construed as limiting, but rather the present disclosure is entitled to a scope of protection consistent with all embodiments, modifications, alternative constructions, and equivalents thereto.

DETAILED DESCRIPTION

(10) Referring to FIG. 1, one exemplary embodiment of a capacitive sensor readout circuit or capacitive sensor device 100 is diagrammatically provided. In general, the capacitive sensor device 100 may be used to monitor for changes in capacitance responsive to capacitive sensor input, such as touch or proximity of a human finger, and provide a digital readout corresponding to the detected capacitive sensor input. Moreover, the capacitive sensor device 100 shown may be incorporated or implemented within mobile or battery-operated devices, or any other form of electronic devices configured to receive some form of capacitive sensor input from a user, and perform a preprogrammed task in response to the capacitive sensor input. As shown, the capacitive sensor device 100 may generally include a clock module 102, a sensor module 104, a current supply module 106, and any other supporting circuitry. Although only certain arrangements of the capacitive sensor device 100 are shown, it will be understood that other arrangements and variations are possible.

(11) As shown in FIG. 1, the clock module 102 may include a clock circuit 108 that is configured to receive a system clock CK, and ultimately generate a clock signal CLK, that is used to operate each of the sensor module 104 and the current supply module 106. The sensor module 104 may include a reference circuit 110 configured to generate a reference signal V.sub.REF, a sense circuit 112 configured to generate a sense signal V.sub.SENSE, and a sample circuit 114 configured to sample a difference between the reference signal V.sub.REF, and the sense signal V.sub.SENSE, according to the clock signal CLK. In particular, the sensor module 104 may employ an analog-to-digital convertor (ADC) 116 configured to sample for differences in capacitance exhibited by the reference signal V.sub.REF and the sense signal V.sub.SENSE, and generate or output a digitized value D.sub.OUT corresponding to the difference in capacitance and capacitive sensor input. The ADC 116 may be enabled based on the clock signal CLK, or clock sample signal CLK_SMP.

(12) Furthermore, the current supply module 106 of FIG. 1 may include a bias current circuit 118, and a multiplier circuit 120. The bias current circuit 118 may be configured to selectively generate a bias current I.sub.B according to the clock signal CLK. The multiplier circuit 120 may be configured to supply current to each of the clock circuit 108, the reference circuit 110, and the sensor circuit 112 based on the bias current I.sub.B and according to the clock signal CLK. More specifically, the multiplier circuit 120 may employ a current mirror or the like, which copies the bias current I.sub.B, and multiplies the bias current I.sub.B to generate three different current signals I.sub.CLK, I.sub.REF and I.sub.SENSE. The first copied current signal I.sub.CLK may be used to charge a clock capacitor 122 having a clock capacitance C.sub.CLK, the second copied current signal I.sub.REF may be used to charge a reference capacitor 124 having a reference capacitance C.sub.REF, and the third copied current signal I.sub.SENSE may be used to charge a sense capacitor 126 having a sense capacitance C.sub.SENSE.

(13) In the embodiment shown, each of the clock capacitor 122 and the reference capacitor 124 in FIG. 1 may be sized to be significantly smaller in capacitance than the sense capacitor 126, so as to improve sensitivity to capacitive sensor input while maintaining low power consumption. In some embodiments, an input capacitance of the ADC 116 may be used instead of the reference capacitance C.sub.REF. Additionally, the multiplier circuit 120 may be configured to copy and multiply the bias current I.sub.B by predefined factors N.sub.CLK, N.sub.REF and N.sub.SENSE to respectively charge each of the clock capacitor 122, the reference capacitor 124, and the sense capacitor 126. Furthermore, the bias current circuit 118 may be configured to generate the bias current I.sub.B only during charging of each of the clock capacitor 122, the reference capacitor 124, and the sense capacitor 126, as determined for instance by the clock signal CLK. In addition, the sense circuit 112 may be configured to vary the sense signal V.sub.SENSE in response to capacitive sensor input such that the difference between the reference signal V.sub.REF and the sense signal V.sub.SENSE corresponds to a magnitude of the capacitive sensor input.

(14) In accordance with the arrangement shown in FIG. 1, and with reference to the timing diagrams of FIG. 2, the clock capacitance C.sub.CLK may be charged by the first copied current signal I.sub.CLK, defined by I.sub.CLK=N.sub.CLKI.sub.B, such that

(15) $\begin{array}{cc}{V}_{\mathrm{CLK}}=\frac{I_{\mathrm{CLK}}{T}_{\mathrm{Charge}}}{C_{\mathrm{CLK}}}=\frac{N_{\mathrm{CLK}}{I}_B{T}_{\mathrm{Charge}}}{C_{\mathrm{CLK}}},& \left(1\right)\\ T_{\mathrm{Charge}}=\frac{V_{\mathrm{CLK}}{C}_{\mathrm{CLK}}}{N_{\mathrm{CLK}}{I}_B}=\frac{N_{\mathrm{CLK}}{I}_B{T}_{\mathrm{Charge}}}{C_{\mathrm{CLK}}},\mathrm{and}& \left(2\right)\\ V_{\mathrm{CLK}}=V_{\mathrm{SUPL}}-V_{\mathrm{CLK},\mathrm{THR}},& \left(3\right)\end{array}$
where T.sub.CHARGE is the period for charging capacitors C.sub.CLK, C.sub.REF and C.sub.SENSE, where V.sub.SUPL is the supply voltage, and where V.sub.CLK,THR is a threshold voltage that is significantly less than V.sub.SUPL. Correspondingly, charging the reference capacitance C.sub.REF with the second copied current signal I.sub.REF, and charging the sense capacitance C.sub.SENSE with the third copied current signal I.sub.SENSE, provides

(16) $\begin{array}{cc}{V}_{\mathrm{REF}}=\frac{N_{\mathrm{REF}}{I}_B{T}_{\mathrm{Charge}}}{C_{\mathrm{REF}}}=\frac{N_{\mathrm{REF}}}{C_{\mathrm{REF}}}.Math.\frac{C_{\mathrm{CLK}}}{N_{\mathrm{CLK}}}\left(V_{\mathrm{SUPL}}-V_{\mathrm{CLK},\mathrm{THR}}\right),& \left(4\right)\\ V_{\mathrm{SENSE}}=\frac{N_{\mathrm{SENSE}}{I}_B{T}_{\mathrm{Charge}}}{C_{\mathrm{SENSE}}}=\frac{N_{\mathrm{SENSE}}}{C_{\mathrm{SENSE}}}.Math.\frac{C_{\mathrm{CLK}}}{N_{\mathrm{CLK}}}\left(V_{\mathrm{SUPL}}-V_{\mathrm{CLK},\mathrm{THR}}\right),& \left(5\right)\end{array}$
where N.sub.CLK, N.sub.REF and N.sub.SENSE are discrete integers.

(17) As shown in FIG. 2, during operation, when the system clock CK changes from logical low to logical high, the clock signal CLK and the clock sample signal CLK_SMP become logical low, and thereby enables the bias current I.sub.B. Enabling the bias current I.sub.B further enables each of the copied current signals I.sub.CLK, I.sub.REF and I.sub.SENSE to begin respectively charging each of the clock capacitor 122, the reference capacitor 124 and the sense capacitor 126 for a duration of T.sub.CHARGE. When the voltage V.sub.CLK across the clock capacitor 122 reaches V.sub.CLK=V.sub.SUPLV.sub.CLK,THR, the clock sample signal CLK_SMP returns to logical high to engage the ADC 116 to sample the difference between voltage V.sub.REF and V.sub.SENSE respectively across the reference capacitor 124 and the sense capacitor 126. After sampling, the clock signal CLK returns to logical high, the bias current signal I.sub.B falls to 0 A, and each of the reference capacitance C.sub.REF and the sense capacitance C.sub.SENSE is discharged to 0 V.

(18) Correspondingly, the clock capacitance C.sub.CLK in FIG. 1 may be discharged to 0 V when the system clock signal CK becomes logical low, and the capacitive sensor device 100 may be completely shut down until the next rising edge of the system clock signal CK, or when the next sample of the sense capacitance C.sub.SENSE should be taken. Based on the foregoing, the digitized value D.sub.OUT output by the ADC 116 may be expressed by

(19) $\begin{array}{cc}{D}_{\mathrm{OUT}}=Q\left[\frac{V_{\mathrm{SENSE}}-V_{\mathrm{REF}}}{{\mathrm{KV}}_{\mathrm{SUPL}}}\right]=Q\left[\frac{V_{\mathrm{SUPL}}-V_{\mathrm{CLK},\mathrm{THR}}}{{\mathrm{KV}}_{\mathrm{SUPL}}}.Math.\frac{C_{\mathrm{TOP}}}{N_{\mathrm{TOP}}}\left(\frac{N_{\mathrm{SENSE}}}{C_{\mathrm{SENSE}}}-\frac{N_{\mathrm{REF}}}{C_{\mathrm{REF}}}\right)\right],& \left(6\right)\end{array}$
where Q denotes the quantization of the bracketed expression, and where KV.sub.SUPL denotes the reference voltage of the ADC 116. Notably, the expression for the digitized value D.sub.OUT illustrates that the readout is independent of the input or bias current I.sub.B, and thus, independent of changes in the bias current I.sub.B caused by variances in temperature, noise such as white noise, 1/f-noise and other noise sources, and manufacturing tolerances. Furthermore, the sensitivity to variances in the supply voltage is also low.

(20) Other variations or modifications to the capacitance sensor device 100 of FIG. 1 may be provided. In one modification, each of the predefined factors N.sub.CLK, N.sub.REF and N.sub.SENSE may be digitally set as a response to the digitized value D.sub.OUT output by the ADC 116. Moreover, the predefined factors may be set according to predetermined algorithms, or the like, configured to calibrate or recalibrate the capacitive sensor device 100 for the given conditions and to prevent the sensitivity of the capacitive sensor device 100 from drifting out of optimal range. For example, the individual values for the predefined factors N.sub.CLK, N.sub.REF and N.sub.SENSE may be calculated during a startup calibration algorithm and/or a calibration algorithm operating in the background while the capacitive sensor device 100 is reading the capacitance over one or more samples.

(21) In another modification, the clock circuit 108 of FIG. 1 may be replaced with the clock circuit 128 shown in FIG. 3, which may essentially include two clock circuits 130, 132, each similar to the clock circuit 108 of FIG. 1, coupled together in series. As further demonstrated by the timing diagrams in FIG. 4, the first clock circuit 130 may be charged via another copied current signal I.sub.CLK,PC which may serve as a pre-charge current. The second clock circuit 132 may be enabled by the first clock circuit 130 when the pre-charge voltage V.sub.CLK,PC is charged to the threshold voltage V.sub.SUPLV.sub.CLK,PC,THR, and the point at which the clock sample signal CLK_SMP becomes logical low and charging begins. The charging continues for the duration of the charge period T.sub.CHARGE and until V.sub.CLK is then reaches its threshold V.sub.SUPLV.sub.CLK,THR. At the end of the charge period T.sub.CHARGE, the clock sample signal CLK_SMP returns to logical high and sampling commences. As in FIG. 1, the clock signal CLK is a delayed version of clock sample signal CLK_SMP. When the clock signal CLK returns to logical high, charging ceases and the capacitances C.sub.REF and C.sub.SENSE are discharged. Both clock circuits 130, 132 are further reset when the system clock CK becomes logical low.

(22) In another modification, a voltage buffer may be applied to the sense signal V.sub.SENSE. For instance, a voltage buffer may be disposed between the sense capacitor 126 and the input of the ADC 116, to prevent the input of the ADC 116 to load and lower the sensitivity of the capacitive sensor device 100. This may be especially important when the sense capacitance C.sub.SENSE may not be much greater than an input capacitance of the ADC 116. Such a voltage buffer may require a bias current that is supplied only during the charge period T.sub.CHARGE, such that the buffer is on only while charging the reference capacitor 124 and the sense capacitor 126, according to the embodiment of FIG. 1 for example. In the embodiment shown in FIG. 3, however, the bias current for a voltage buffer may be enabled when the first clock circuit 130 begins to charge, and disabled when the clock signal CLK becomes logical high at the end of the charge period T.sub.CHARGE. This would enable the voltage buffer time to settle the internal bias currents before charging begins.

(23) In still another modification, and with reference to FIG. 5, the sense circuit 112 may provide, in addition to a default sensor plate 134, a sensor shield 136. For example, a voltage buffer may be added to copy the sense signal V.sub.SENSE to form a shield signal V.sub.SHIELD used to drive the sensor shield 136, which may enable the capacitive sensor device 100 to operate in a self-capacitance mode with increased sensitivity. In particular, self-capacitance modes may provide the sensitivity needed to detect small variations in capacitance caused by the proximity of an object rather than capacitive sensor input. The diagram in FIG. 5 compares the mutual capacitance mode of the embodiment of FIG. 1 to the self-capacitance mode of a shielded arrangement. As shown, the mutual capacitance mode exhibits a sense capacitance C.sub.SENSE, that is the sum of a fixed parasitic capacitance C.sub.SENSE,0 between the sensor plate 134 and ground, and the capacitance C.sub.SENSE,F between the sensor plate 134 and a finger or other object 138.

(24) According to the mutual capacitance example of FIG. 5, the relatively large fixed parasitic capacitance C.sub.SENSE,0 and the relatively large distance between the object 138 and the sensor plate 134 renders the capacitance C.sub.SENSE,F to be very small when used as a proximity sensor. Moreover, the digitized value D.sub.OUT output by the ADC 116 becomes too insensitive to the slight changes in capacitance induced by mere proximity. However, by using the self-capacitance mode of FIG. 5, and by substantially surrounding the sides and bottom surface of the sensor plate 134 with the sensor shield 136, the fixed capacitance C.sub.SENSE,0 can be made relatively very small. For example, using a voltage buffer to copy the sense signal V.sub.SENSE to the shield signal V.sub.SHIELD offsets the capacitance C.sub.2 formed between the sensor plate 134 and the sensor shield 136 improves overall sensitivity for proximity applications. In actual implementation, the sensor shield 136 may also surround a node extending between the sensor plate 134 and the capacitive sensor device 100. Furthermore, such a voltage buffer may be supplied with a bias current using any of the techniques described above.

(25) In yet another embodiment, the sense circuit 112 of FIG. 1 may be replaced with the modified sense circuit 140 show in FIGS. 6 and 7, for instance, to access and provide readouts for more than one sense capacitor 126 by incorporating an analog multiplexer (MUX) 142, or the like. As demonstrated in FIG. 6, for instance, one analog input of the MUX 142 may be coupled to the sense signal V.sub.SENSE of FIG. 1, and two or more analog outputs of the MUX 142 may be coupled to two or more additional sense capacitors 126. A digital input signal CTRL_MUX may be used to select the sense capacitors 126 to access at any given moment. Similarly, as shown in FIG. 7, a MUX 142 may also employ the shielded arrangement of FIG. 5. For instance, the MUX 142 may include two analog inputs, one coupled to the sense signal V.sub.SENSE and one coupled to the shield signal V.sub.SHIELD. The MUX 142 may also include two or more analog outputs, which can also be individually accessed using the digital input signal CTRL_MUX.

(26) In still further variations, the ADC 116 of FIG. 1 may be replaced with, or implemented with, a built-in trigger circuit configured with one or more trigger values against which an analog input can be compared. The trigger circuit outputs may be the result of the comparison between the analog input and the predefined trigger values. Further still, other modifications can be made to attenuate the effects of external disturbance, such as, but not limited to, stray currents inconsistently charging sense capacitors 126, variations in capacitance charge due to electromagnetic fields or related interference, and the like. For instance, the input bias current I.sub.B may be optimized such that the charge period T.sub.CHARGE may be adjusted to attenuate such interference and to optimize sensitivity to touch, proximity, or other capacitive sensor input. While only certain arrangements and embodiments are shown, it will be understood that other variations can be implemented to provide comparable results.

(27) Turning now to FIG. 8, one exemplary method 144 of sensing a change in capacitance or capacitive sensor input is provided. The method 144, or any one or more processes thereof, may be implemented in a variety of different ways, such as using one or more of algorithms, instructions, logic operations, and the like, and/or using digital circuitry, analog circuitry, or combinations thereof. As shown in FIG. 8, and in conjunction with the embodiments discussed in FIGS. 1-7 above, the method 144 in block 144-1 may initially generate a clock signal CLK based on a clock capacitance C.sub.CLK, a reference signal V.sub.REF based on a reference capacitance C.sub.REF, and a sense signal V.sub.SENSE based on a sense capacitance C.sub.SENSE. As discussed above, each of the clock capacitance C.sub.CLK and the reference capacitance C.sub.REF may be sized to be significantly smaller than the sense capacitance C.sub.SENSE. Furthermore, the sense capacitance C.sub.SENSE may be configured to vary in response to capacitive sensor input.

(28) Still referring to FIG. 8, the method 144 may be configured to generate a bias current I.sub.B according to the clock signal CLK in block 144-2, and charge each of the clock capacitance C.sub.CLK, the reference capacitance C.sub.REF, and the sense capacitance C.sub.SENSE based on the bias current I.sub.B and according to the clock signal CLK in block 144-3. More specifically, the method 144 may generate the bias current I.sub.B only when charging each of the clock capacitance C.sub.CLK, the reference capacitance C.sub.REF, and the sense capacitance C.sub.SENSE. Furthermore, the bias current I.sub.B may be copied and multiplied by predefined factors N.sub.CLK, N.sub.REF and N.sub.SENSE, and the copied current signals I.sub.CLK, I.sub.REF and I.sub.SENSE may be used to respectively charge each of the clock capacitance C.sub.CLK, the reference capacitance C.sub.REF, and the sense capacitance C.sub.SENSE. As discussed above, each of the predefined factors N.sub.CLK, N.sub.REF and N.sub.SENSE may also be digitally set as a response to the digitized value D.sub.OUT output by the ADC 116.

(29) The method 144 of FIG. 8 may further be configured to sample a difference between the reference signal V.sub.REF and the sense signal V.sub.SENSE according to the clock signal CLK in block 144-4. For example, the difference between the reference signal V.sub.REF and the sense signal V.sub.SENSE may correspond to a magnitude of the capacitive sensor input detected by the variable sense capacitance C.sub.SENSE. The method 144 in block 144-5 may further be configured to output a digitized value D.sub.OUT which corresponds to the difference between the reference signal V.sub.REF and the sense signal V.sub.SENSE. Moreover, the digitized value D.sub.OUT may be configured not only to correspond to a magnitude of the capacitive sensor input, but also to be substantially independent of variances in the bias current I.sub.B caused by variances in temperature, supply voltage, and/or interference due to noise, white noise, 1/f noise, and the like. Furthermore, any one or more processes of the method 144 shown in FIG. 8 may be reiterated per cycle of the system clock CK or some other desired frequency.

(30) From the foregoing, it will be appreciated that while only certain embodiments have been set forth for the purposes of illustration, alternatives and modifications will be apparent from the above description to those skilled in the art. These and other alternatives are considered equivalents and within the spirit and scope of this disclosure and the appended claims.