GATE STRUCTURE AND METHOD FOR PRODUCING SAME

Abstract

This invention concerns a gate structure and a process for manufacturing.

In particular, the present invention concerns the gate structuring of a field effect transistor with reduced thereto-mechanical stress and increased reliability (lower electromigration or diffusion of the gate metal).

The gate structure according to the invention comprises a substrate (10); an active layer (20) disposed on the substrate (10); an intermediate layer (40) disposed on the active layer (20), the intermediate layer (40) having a recess (45) extending through the entire intermediate layer (40) towards the active layer (20); and a contact element (50) which is arranged within the recess (45), the contact element (50) completely filling the recess (45) and extending to above the intermediate layer (40), the contact element (50) resting at least in sections directly on the intermediate layer (40); the contact element (50) being made of a Schottky metal (52) and the contact element (50) having an interior cavity (55) completely enclosed by the Schottky metal (52).

Claims

1. A gate structure comprising: a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, wherein the intermediate layer has a recess extending through the entire intermediate layer towards the active layer; and a contact element which is arranged inside the recess, wherein the contact element completely fills the recess and extends to above the intermediate layer, wherein the contact element rests directly on the intermediate layer at least in sections or the contact element is separated from the active layer and the intermediate layer by a dielectric cladding; the contact element is made of a Schottky metal; and the contact element has an interior cavity completely enclosed by the Schottky metal, wherein the recess has a width between 10 nm and 100 nm at the boundary with the underlying layer.

2. The gate structure of claim 1, wherein the contact element contacts the active layer directly.

3. (canceled)

4. The gate structure of claim 1, further comprising a dielectric layer disposed directly between the active layer and the intermediate layer, the contact element directly contacting the dielectric layer

5. The gate structure of claim 1, wherein the intermediate layer is a passivation layer.

6. The gate structure claim 1, wherein the intermediate layer comprises at least a first intermediate layer and a second intermediate layer.

7. The gate structure of claim 1, wherein the contact element above the intermediate layer is directly covered by a gate metal and the contact element with the gate metal above the intermediate layer is completely surrounded by a dielectric covering layer.

8. A method for producing a gate structure comprising: providing a substrate having an active layer disposed on the substrate and an intermediate layer disposed on the active layer; creating a recess in the intermediate layer, wherein the recess extends through the entire intermediate layer towards the active layer, wherein the recess has a width between 10 nm and 300 nm at the boundary with the underlying layer, wherein the recess has a width between 10 nm and 100 nm at the boundary with the underlying layer; filling and covering the recess by depositing a Schottky metal by sputtering, wherein the covering is continued at least until the Schottky metal completely covers the recess above the recess; structuring a contact element from the deposited Schottky metal, wherein the contact element rests at least in sections directly on the intermediate layer.

9. The method of claim 7, further comprising depositing a gate metal covering the Schottky metal above the intermediate layer.

10. The method of claim 7, wherein a dielectric cladding is deposited on the surface of the recess prior to filling and covering the recess.

11. The method of claim 8, wherein a dielectric cladding is deposited on the surface of the recess prior to filling and covering the recess.

12. The method of claim 9, wherein a dielectric cladding is deposited on the surface of the recess prior to filling and covering the recess.

13. The gate structure of claim 2, wherein the intermediate layer is a passivation layer.

14. The gate structure of claim 4, wherein the intermediate layer is a passivation layer.

15. The gate structure of claim 5, wherein the intermediate layer is a passivation layer.

17. The gate structure of claim 6, wherein the intermediate layer is a passivation layer.

18. The gate structure of claim 2, wherein the intermediate layer comprises at least a first intermediate layer and a second intermediate layer.

19. The gate structure of claim 2, wherein the contact element above the intermediate layer is directly covered by a gate metal and the contact element with the gate metal above the intermediate layer is completely surrounded by a dielectric covering layer.

20. A gate structure comprising: a substrate; an active layer disposed on the substrate; an intermediate layer disposed on the active layer, wherein the intermediate layer has a recess extending through the entire intermediate layer towards the active layer, the intermediate layer is a passivation layer, the intermediate layer comprises at least a first intermediate layer and a second intermediate layer; and a contact element which is arranged inside the recess, wherein the contact element completely fills the recess and extends to above the intermediate layer, wherein the contact element rests directly on the intermediate layer at least in sections or the contact element is separated from the active layer and the intermediate layer by a dielectric cladding, the contact element is made of a Schottky metal, the contact element has an interior cavity completely enclosed by the Schottky metal, the contact element contacts the active layer directly, the contact element above the intermediate layer is directly covered by a gate metal and the contact element with the gate metal above the intermediate layer is completely surrounded by a dielectric covering layer; and a dielectric layer disposed directly between the active layer and the intermediate layer, the contact element directly contacting the dielectric layer.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0040] The invention is explained in the following examples using the corresponding figures. It is shown:

[0041] FIG. 1 a schematic structure of a conventional gate structure according to the state of the art,

[0042] FIG. 2 a schematic structure of a first embodiment of the invention,

[0043] FIG. 3 a schematic structure of a second embodiment of the invention,

[0044] FIG. 4 a schematic structure of a third embodiment of the invention,

[0045] FIG. 5 a schematic structure of a fourth embodiment of the invention, and

[0046] FIG. 6 a schematic representation of the step filling and covering of the process according to the invention for producing a gate structure according to the invention.

DETAILED DESCRIPTION OF THE FIGURES

[0047] FIG. 1 shows a schematic structure of a conventional gate structure according to the state of the art. In particular, it is a T-gate as typically used in a HEMT or MeSFET. The figure shows a gate structure comprising a substrate 10; an active layer 20 disposed on the substrate 10; an intermediate layer 40 disposed on the active layer 20, the intermediate layer 40 having a recess 45 extending through the entire intermediate layer 40 towards the active layer 20; and a contact element 50 disposed within the recess 45, wherein the contact element 50 completely and homogeneously fills the recess 45 and extends up to above the intermediate layer 40, wherein the contact element 50 rests at least in sections directly on the intermediate layer 40. The contact element here consists of a gate metal 60. The gate metal 60, for example, can be Au. The contact element 50 is separated from the active layer 20 and the intermediate layer 40 by a Schottky 52 metal cladding. The Schottky metal may in particular be a thin layer of Ir or Pt. The contact element 50 is completely surrounded by a dielectric covering layer 70 above the intermediate layer 40.

[0048] FIG. 2 shows the schematic structure of a first embodiment of the invention. This may also be, in particular, a T-gate for a HEMT or MeSFET. The figure shows a gate structure according to the invention comprising a substrate 10; an active layer 20 disposed on the substrate 10; an intermediate layer 40 disposed on the active layer 20, wherein the intermediate layer 40 has a recess 45 extending through the entire intermediate layer 40 towards the active layer 20; and a contact element 50, which is arranged within the recess 45, wherein the contact element 50 completely and homogeneously fills the recess 45 and extends up to above the intermediate layer 40, wherein the contact element 50 at least in sections rests directly on the intermediate layer 40; wherein the contact element 50 is constructed from a Schottky metal 52 and the contact element 50 has an interior cavity 55 completely enclosed by the Schottky metal 52. The contact element 50 contacts the active layer 20 directly. Furthermore, the contact element 50 above the intermediate layer 40 is directly covered by a gate metal 60 and the contact element 50 with the gate metal 60 is completely surrounded by a dielectric covering layer 70 above the intermediate layer 40.

[0049] FIG. 3 shows a schematic structure of a second embodiment of the invention. In particular, this may be a T-gate of a MOSFET (variant 1). The representation shown corresponds as far as possible to the representation shown in FIG. 2, the reference signs and their assignment apply accordingly. However, unlike FIG. 2, the gate structure according to the invention comprises an additional dielectric layer 30 located directly between the active layer 20 and the intermediate layer 40, wherein the contact element 50 contacts the dielectric layer 30 directly.

[0050] FIG. 4 shows a schematic structure of a third embodiment of the invention. In particular, this may be a T-gate of a MOSFET (variant 1). The representation shown corresponds as far as possible to the representation shown in FIG. 2, the reference signs and their assignment apply accordingly. In contrast to FIG. 2, the gate structure according to the invention shows that the contact element 50 is separated from the active layer 20 and the intermediate layer 40 by a dielectric cladding 32.

[0051] FIG. 5 shows a schematic structure of a fourth embodiment of the invention. In particular, this may be a T-gate of a MOSFET (variant 2). The representation shown corresponds as far as possible to the representation shown in FIG. 4, the reference signs and their assignment apply accordingly. In contrast to FIG. 4, the intermediate layer 40 is formed from a first intermediate layer 42 and a second intermediate layer 44. Furthermore, a source metal 80 has been applied above the dielectric covering layer 70. In the vertical transistor shown, a drain contact 90 is also located on the back of substrate 10. Preferably, substrate 10 is an n+-GaN substrate, active layer 20 is an n-GaN drift layer, first intermediate layer 42 is a p-type GaN layer, and second intermediate layer 44 is an n+-GaN layer.

[0052] FIG. 6 shows a schematic representation of the step filling and covering of the method according to the invention for the production of a gate structure according to the invention, A substrate 10 having an active layer 20 disposed on the substrate 10 and an intermediate layer 40 disposed on the active layer 20 has been provided.

[0053] Further, a recess 45 has been formed in the intermediate layer 40, wherein the recess 45 extends through the entire intermediate layer 40 towards the active layer 20. The filling and covering of the recess 45 is then performed by sputtering a Schottky metal 52, wherein the covering is continued at least until the Schottky metal 52 above the recess 45 completely covers the recess 45.

[0054] During filling, the Schottky metal 52 coats both the sides of the recess 45 and the underlying active layer 20 (or an additional dielectric layer 30). The sputtering of Schottky metal 52 results in a reduced application of material to the bottom of recess 45 compared to the top of recess 45. As the filling increases, this results in increased material growth on the top, with further growth of the metal layer inside recess 45 increasingly suppressed. In particular, the structure sizes typical for T-gates lead to an overgrowth of the recess 45, wherein a cavity 55 is created inside the Schottky metallization of the recess 45 produced in this way. This cavity 55 is produced by a lower lateral growth rate of the Schottky metal 52 on the side walls of recess 45 by the coalescence of the Schottky metal 52 above recess 45. The process of forming the cavity 55 is self-aligning.

[0055] In the last illustration step, the structuring of a contact element 50 made of the deposited Schottky metal 52 is merely indicated by hatching, wherein the contact element 50 lies directly on the intermediate layer 40 at least in sections. The T-shaped shape of the gate within the gate structure according to the invention is clearly visible.

REFERENCE LIST

[0056] 10 substrate [0057] 20 active layer [0058] 30 dielectric layer [0059] 32 dielectric cladding [0060] 40 intermediate layer [0061] 42 first intermediate layer [0062] 44 second interlayer [0063] 45 recess [0064] 50 contact element [0065] 52 Schottky metal [0066] 55 cavity [0067] 60 gate metal [0068] 70 dielectric covering layer [0069] 80 source metal [0070] 90 drain contact