PROCESSING METHOD IN A WIRELESS TELECOMMUNICATIONS RECEIVER RECEIVING A DIGITALLY MODULATED SINGLE-CARRIER SIGNAL, ASSOCIATED WIRELESS TELECOMMUNICATIONS RECEIVER AND ASSOCIATED COMPUTER PROGRAM

Abstract

A processing method in a wireless telecommunications receiver receiving a digitally modulated single-carrier signal includes, between a matched filter, in the time domain, operating at a frequency drx×B and a frequency equalizer, operating at the frequency B, a decimation step comprising: i/extracting, from a filtered signal frame, a first sequence of samples for aiding the decimation and having the same power; and a second sequence of payload samples intended to be equalized; ii/estimating the variance in the power of each of the drx decimation phases of the first sequence and identifying the n.sup.th decimation phase associated with the minimum variance; iii/decimating the second sequence by selecting the n.sup.th decimation phase of the second sequence and supplying the decimation phase at the input of the frequency equalizer.

Claims

1. A processing method in a wireless telecommunications receiver receiving a digitally modulated single-carrier signal, said receiver comprising a processing chain comprising a matched filter designed to perform shaping filtering on the signal in the time domain and to operate at a frequency drx×B and a frequency equalizer designed to perform frequency equalization on the filtered signal and deduce the modulation symbols of the equalized signal and to operate at the frequency B, drx being strictly greater than 1; said method implemented in the receiver comprising, between the filtering and the equalization, a step of decimating the filtered signal by a factor drx, said method implemented in the receiver wherein said decimation of the filtered signal comprises the following steps: i/extracting, from a filtered signal frame: a first sequence of samples, said samples being samples for aiding the decimation and having the same power; and a second sequence of samples, said samples being the payload samples intended to be equalized; ii/estimating the variance in the power of each of the drx decimation phases of the first sequence of samples; comparing the estimated power variances with one another and identifying the decimation phase associated with the minimum variance, said identified phase being the n.sup.th phase, with n E {0, 1, . . . ; drx−1}; iii/decimating the second sequence of samples by a factor drx, the samples at the sampling frequency equal to B and delivered at the output of said decimation step being those of the n.sup.th decimation phase of the second sequence; iv/supplying, at the input of the frequency equalizer, said samples at the sampling frequency equal to B and delivered at the output of said decimation step.

2. The processing method in a wireless telecommunications receiver according to claim 1, wherein steps i, ii, iii and iv are implemented in relation to each filtered signal frame.

3. The processing method in a wireless telecommunications receiver according to claim 1, wherein the samples of the first sequence result from a digital modulation of a first type and the samples of the second sequence result from a digital modulation of a second type different from the first type.

4. The processing method in a wireless telecommunications receiver according to claim 1, wherein steps ii and iii are implemented in parallel in a decimation block, wherein: the first sequence of samples of the frame is supplied at the input of a first processing sub-chain computing the power of each of said samples, and then distributing the sequence of resulting powers into drx sequences each corresponding to a decimation phase, computing the variance of each sequence of powers and identifying the decimation phase, phase number n, having the lowest variance; in parallel, the second sequence of samples of the frame is supplied at the input of a second processing sub-chain distributing the second sequence into drx sequences each corresponding to a decimation phase and supplying said drx sequences at the input of a multiplexer selecting that one of said drx sequences, which will be supplied at the output of said decimation block to the equalizer, corresponding to decimation phase number n on the basis of the identifier, n, supplied to the multiplexer by the first processing sub-chain.

5. The processing method in a wireless telecommunications receiver according to claim 1, wherein the size of the first sequence of samples used in step i is selected prior to steps i to iv on the basis of the desired speed of the decimation step and of the desired quality of the equalization.

6. A computer program, intended to be stored in the memory of a wireless telecommunications receiver receiving a digitally modulated single-carrier signal, said receiver comprising a processing chain comprising a shaping filter for shaping the signal in the time domain, designed to perform shaping filtering on the signal and to operate at a frequency drx×B and a frequency equalizer designed to perform frequency equalization on the filtered signal and to operate at the frequency B, drx being strictly greater than 1, and furthermore comprising a microcomputer, said computer program comprising instructions that, when they are executed on the microcomputer, implement the steps of a method according to claim 1.

7. A wireless telecommunications receiver designed to receive a digitally modulated single-carrier signal, said receiver comprising a processing chain comprising a matched filter designed to perform shaping filtering on the signal in the time domain and to operate at a frequency drx×B and a frequency equalizer designed to perform frequency equalization on the filtered signal and deduce the modulation symbols of the equalized signal and to operate at the frequency B, drx being strictly greater than 1; the receiver comprising, between the matched filter and the equalizer, a decimation block designed to decimate the filtered signal by a factor drx, said receiver being wherein the decimation block is designed to perform the following operations: i/said decimation block is designed to extract, from a filtered signal frame: a first sequence of samples, said samples being samples for aiding the decimation and having the same power; and a second sequence of samples, said samples being the payload samples intended to be equalized; ii/said decimation block is designed to estimate the variance in the power of each of the drx decimation phases of the first sequence of samples; to compare the estimated power variances with one another and identify the decimation phase associated with the minimum variance, said identified phase being the n.sup.th phase, with nϵ{0, 1, . . . ; drx−1}; iii/said decimation block is designed to decimate the second sequence of samples by a factor drx, the samples at the sampling frequency equal to B and delivered at the output of said decimation step being those of the n.sup.th decimation phase of the second sequence; iv/said decimation block is designed to supply, at the input of the frequency equalizer, said samples at the sampling frequency equal to B and delivered at the output of said decimation step.

8. The wireless telecommunications receiver according to claim 7, wherein the decimation block is designed to perform the operations in relation to each filtered signal frame.

9. The wireless telecommunications receiver according to claim 7, wherein the samples of the first sequence result from a digital modulation of a first type and the samples of the second sequence result from a digital modulation of a second type different from the first type.

10. The wireless telecommunications receiver according to claim 7, wherein the decimation block comprises: a first processing sub-chain designed to receive, at input, the first sequence of samples of the frame, to compute the power of each of said samples, and then to distribute the sequence of resulting powers into drx sequences each corresponding to a decimation phase, to compute the variance of each sequence of powers and identify the decimation phase, phase number n, having the lowest variance; a second processing sub-chain designed to receive, at input, the second sequence of samples of the frame, to distribute the second sequence into drx sequences each corresponding to a decimation phase, said second chain comprising a multiplexer designed to receive, at input, said drx sequences, designed to receive an identifier, n, supplied by the first processing sub-chain, and designed to select that one of said drx sequences, which will be supplied at the output of said decimation block to the equalizer, corresponding to decimation phase number n equal to the identifier supplied by the first processing sub-chain; the first and second sequences being processed in parallel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The invention will be better understood and other features, details and advantages will become more clearly apparent on reading the following non-limiting description, and by virtue of the appended figures, which are given by way of example.

[0080] FIG. 1 shows a single-carrier transmission chain from the prior art;

[0081] FIG. 2 shows the receiver of the single-carrier transmission chain from FIG. 1 in more detail;

[0082] FIG. 3 shows the upsampling, decimation and equivalent tx-rx filtering operations implemented for example in a single-carrier transmission chain from the prior art as shown in FIG. 1;

[0083] FIG. 4 shows the frequency response of the equivalent tx-rx filter at reception from FIG. 3 before decimation;

[0084] FIG. 5 shows the frequency response of the equivalent tx-rx filter at reception from FIG. 3 after decimation;

[0085] FIG. 6 shows the graph of the eye of the power, after RRC Rx;

[0086] FIG. 7 shows a single-carrier transmission chain in one embodiment of the invention;

[0087] FIG. 8 shows the decimation block from FIG. 7 designed to select the decimation phase in one embodiment;

[0088] FIG. 9 shows a method in one embodiment of the invention.

[0089] Identical references may be used in various figures to designate identical or comparable elements.

DETAILED DESCRIPTION

[0090] FIG. 7 shows a single-carrier transmission chain in one embodiment of the invention, taking into account the various sampling frequency constraints explained above and designed to allow selection of the decimation phase at reception. This transmission chain, in one embodiment, comprises a single-carrier transmitter 5 comprising: [0091] a binary source 5_1, [0092] a coding block 5_2 for “mapping” M bits to an analogue value in the complex plane in accordance with a digital modulation (for example, but without limitation, QAM, AKQ, FSK, PSK) defining a constellation of symbols;

[00027]$T=\frac{1}{B}$ [0093] is used to denote the rate of these complex symbols, [0094] a shaping filter 5_3 for limiting the band of the signal and inter-symbol interference (ISI), [0095] a transmission antenna 5_4 transmitting the filtered signal on the carrier; and [0096] a preamble insertion block 5_5;
and a receiver 6 comprising, in the case under consideration, notably: [0097] a reception antenna 6_1, [0098] a filter 6_2, [0099] a decision member 6_3 for recovering the complex symbols, of FDE (frequency domain equalizer) type, the role of which is to estimate the parameters of the channel (notably frequency attenuations), to equalize the frequency of the frequency samples on the basis of the estimated channel parameters and to return to the time domain through an inverse Fourier transform operation. The use of an FDE equalizer 63 means having to frame the complex symbols, this grouping them into packets of N, the equalizer 63 operating on this packet size (cf. FIG. 2); [0100] an upsampling block 6_20 designed to upsample the received signal by a factor u.sub.rx such that the frequency of the upsampled signal that is supplied at the input of the filter 6_2 is strictly greater than B; [0101] a decimation block 6_40, designed to downsample the signal by a factor d.sub.rx, such that the frequency of the decimated signal supplied at the input of the FDE block 6_3 is equal to B, and designed to select the decimation phase by implementing a processing process in one mode of implementation of the invention.

[0102] The binary source 5_1, respectively the coding block 5_2, the shaping filter 5_3 and the transmission antenna 5_4 from FIG. 7 are similar to the source 51, respectively to the coding block 52, to the shaping filter 53 and to the transmission antenna 54 from FIG. 1.

[0103] The reception antenna 6_1, respectively the filter 6_2, and the decision member 6_3 from FIG. 7 are similar to the reception antenna 61, respectively the filter 62, and the decision member 63 from FIG. 1.

[0104] The preamble insertion block 5_5 in the transmitter 5 is designed to add, to each frame comprising the payload samples (i.e. obtained from the binary source), a preamble to the frame, the preamble comprising N.sub.p coded samples, for example coded using BPSK (i.e. {−1, +1}) or any other coding method with digital modulation delivering coded samples all of the same power, for example QPSK, 8-FSK, Zadof-Chu, etc. (the type of coding of the samples of the preamble is, in some embodiments of the invention, different from the coding of the binary source 5_1, the symbol frequency B however being common).

[0105] In the receiver 6, the decimation block 6_40 receives a signal resulting from the upsampling performed by the block 6_20 and from the filtering g(t) performed by the block 6_2 in the time domain. At the “RRC Rx” filter output, this signal contains d.sub.rx times more samples than required by the block FDE 6_3. The decimation block 6_40 is responsible for selecting the position of the sampling comb from among d.sub.rx positions and for supplying the corresponding downsampled signal at output.

[0106] FIG. 8 shows, in one embodiment of the invention, the architecture of the decimation block 6_40 for d.sub.rx=3. The decimation block 6_40 thus comprises two parallel processing chains.

[0107] The chain for processing the samples of the preamble of the same power comprises a power computation block 6_41, a block 6_44 for distributing the samples of the preamble into d.sub.rx=3 parallel flows each corresponding to a respective decimation phase, d.sub.rx=3 parallel variance computation blocks 6_45_1, 6_45_2, 6_45_3 and a block for determining a minimum 6_48.

[0108] The chain for processing the payload samples (resulting from the coding of the binary source) comprises a block 6_42 for distributing the payload samples into d.sub.rx=3 parallel flows each corresponding to a respective decimation phase and a multiplexer 6_43, controlled by a control signal from the block for determining a minimum 6_48.

[0109] The decimation block 6_40 is designed to implement the process 100 described below with reference to FIG. 9. In one embodiment, the decimation block 6_40 comprises a computer and a memory storing software instructions that, when they are implemented on the computer, implement the steps described below with reference to FIG. 9.

[0110] Thus, as shown in FIG. 9, for each frame received by the decimation block 6_40, in a step 101, the N.sub.p coded samples of the same power of the preamble, at the sampling frequency B×d.sub.rx, are extracted from the preamble of the frame by the decimation block 6_40 and are supplied at the input of the power computation block 6_41, whereas the payload samples of this frame, at the sampling frequency B×d.sub.rx, are extracted from the frame by the decimation block 6_40 and are supplied at the input of the distribution block 6_42.

[0111] In a step 102, the power computation block 6_41 computes the power of the samples (∥ ∥.sup.2) of the preamble and supplies the flow of power values to the distribution block 6_44.

[0112] In a step 103, the distribution block 6_44 distributes the flow of the powers of the samples of the preamble into d.sub.rx=3 parallel flows each corresponding to a respective decimation phase no. i of the power samples of the preamble and supplies each decimation phase no. i to a respective variance computation block 6_45_i, i=1 to d.sub.rx=3.

[0113] In steps 104_i, i=1, 2, 3, for example implemented in parallel, each variance computation block 6_45_i, i=1 to d.sub.rx=3, computes the variance in the received powers and delivers the variance value computed for phase no. i to the block for determining a minimum 6_48.

[0114] In a step 105, the block for determining a minimum 6_48 compares the d.sub.rx(=3) computed power variances with one another, selects the lowest one, identifies the phase corresponding to the lowest variance, called phase n here, and supplies the identifier “n” of the phase to the multiplexer 6_43.

[0115] In parallel with steps 102 to 105, in a step 106, the distribution block 6_42 distributes the flow of the payload samples into d.sub.rx=3 parallel flows each corresponding to a respective decimation phase no. i of the payload samples and supplies each decimation phase no. i to the multiplexer 6_43.

[0116] In a step 107, the multiplexer 6_43 selects decimation phase no. n from among the d.sub.rx decimation phases received on its inputs, and it is only this decimation phase, and not the other phases, that is delivered at output of the decimation block 6_40 and supplied to the equalization block 6_3 (the samples in the preamble are not supplied; they do not contain any payload information to be decoded and are used in the embodiment under consideration only to identify the best decimation phase).

[0117] It is thus not the amplitude of the samples of the preamble that is used, but the power of each sample. This makes it possible to overcome any phase rotation of the samples.

[0118] In one embodiment, the optimum decimation phase is selected frame by frame, on the basis of the preamble of each filtered frame presented at the input of the decimation block.

[0119] In one embodiment, the length of the estimation (ensuring the precision of the estimation) is performed on L.sub.var samples, L.sub.var being strictly less than or equal to the length of the preamble N.sub.p.; in one embodiment, the value of L.sub.var and/or N.sub.p. is selected before the method 100 is implemented on a frame, on the basis of the desired speed of the decimation step and of the desired quality of the equalization.

[0120] FIG. 6 proposes a “graph of the eye” of the samples of the preamble, with the rank of the sample modulo d.sub.rx on the abscissa and the power of the sample on the ordinate. The invention makes it possible to find the decimation phase of the samples corresponding to a node of this graph. The best phase, here for example with d.sub.rx=6, the one corresponding to the minimum variance, is phase #1 (the phases are numbered 0 to d.sub.rx−1 in FIG. 6), the one having values that are all equal (here the ideal case, without white noise), the preamble containing only values of the same power.

[0121] The probability of false detection (i.e. choosing the phase that is not expected) while implementing the invention was studied for various SNR values and for two values of L.sub.var. The probability is virtually zero for the SNRs of interest (for example >18 dB in the application).

[0122] The filter under consideration above is an RRC filter, but the invention remains applicable to any pair of matched filters.

[0123] The greater the number of coefficients of the filter, the more there will be a decimation phase that gives rise to a flat frequency response of the filter after decimation (as a function of the sampling frequency, of the band of the signal): a criterion with regard to the width of a flat area thus makes it possible, in one embodiment, to determine the number of coefficients of the filter.