MULTI-RATE DEM WITH MISMATCH NOISE CANCELLATION FOR DIGITALLY-CONTROLLED OSCILLATORS

Abstract

A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

Claims

1. A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC), comprising: a phase error to digital converter; a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator; a digitally controlled oscillator (DCO) with a multi-rate DEM encoder driving an integer bank of frequency control elements and a fractional bank of frequency control elements; and adaptive mismatch-noise cancellation logic operating to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero FCE static and dynamic mismatch error.

2. The digital fractional-N phase locked loop of claim 1, wherein the updating of the MNC coefficient values is conducted once for each time the phase error of the PLL is measured.

3. The digital fractional-N phase locked loop of claim 1, wherein the multi-rate DEM comprises: a slow DEM encoder that drives the integer bank of frequency control elements and a second order modulator; and a fractional path, wherein the fractional path includes the second-order digital modulator driving a fast DEM encoder that drives the fractional bank of frequency control elements, wherein the second-order digital modulator and fast DEM encoder are clocked at a higher frequency compared to that of the slow DEM encoder.

4. The digital fractional-N phase locked loop of claim 3, wherein the modulator's quantization noise is asymptotically independent of its input and dither sequences used in the modulator.

5. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic injects an MNC correction sequence, which is computed from the MNC coefficient values and the switching sequences generated inside the slow DEM encoder, into the fractional path.

6. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients with a least-mean-square (LMS)-like algorithm.

7. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients based on the statistical properties of switching sequences generated inside the slow DEM encoder.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG. 1 (Prior Art) is a schematic diagram of a frequency control technique for an LC-based DC);

[0045] FIG. 2 includes a set of example waveforms related to equations (15) and (16) to provide a visual representation of the effects of FCE mismatches on the DCO frequency;

[0046] FIG. 3 (Prior Art) is a block diagram of a mismatch-shaping segmented DEM encoder;

[0047] FIGS. 4A-4C (Prior Art) are block (4A & 4B) and schematic (4C) diagrams showing digital switching blocks of the FIG. 3 DEM encoder;

[0048] FIG. 5 is a block diagram of a preferred embodiment DCO with a multi-rate segmented DEM encoder that is a modification of the FIG. 3 encoder;

[0049] FIG. 6 is a block diagram of a preferred slow DEM encoder used in FIG. 5,

[0050] FIG. 7 is a functional diagram of a preferred embodiment second-order digital modulator used in FIG. 5;

[0051] FIG. 8 shows the fractional path of the multi-rate DEM encoder shown in FIG. 5 modified to accommodate MNC;

[0052] FIG. 9 (Prior Art) is a schematic diagram of a digital fractional-N PLL without MNC;

[0053] FIGS. 10A & 10B (Prior Art) respectively are a schematic diagram of a synchronization circuit used at DCO input in FIG. 9 and illustration of the clock signals within the DCO, p.sub.t, and n.sub.t=g(p.sub.t) for f.sub.fast=4. 5f.sub.ref,

[0054] FIGS. 11A-11C are block diagrams that illustrate a preferred digital fractional-N PLL with the multi-rate DEM encoder and MNC;

[0055] FIG. 12 shows example frequency transients used in a simulation of the FIGS. 11A-11C digital fractional-N PLL;

[0056] FIGS. 13A-13C respectively show simulated phase noise of the FIGS. 11A-11C digital fractional-N PLL; with the multi-rate DEM technique disabled, with the multi-rate DEM technique enabled for two cases, and with the multi-rate DEM technique enabled and with the MNC technique disabled and enabled;

[0057] FIGS. 14A & 14B show the evolution of the MNC coefficient errors over time from the simulation used to generate the curves in FIG. 13C;

[0058] FIGS. 15A & 15B show the evolution of the MNC coefficient errors over time for 7.Math.8.Math.10.sup.7 reference periods (3 seconds) for an example case in which K.sub.a and K.sub.b are initially set to 2.sup.1 and 2.sup.2, respectively, and then divided by two at the times indicated by the vertical dashed lines.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0059] Preferred embodiment methods and digital oscillators provide multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) that work together to address FCE mismatches. The DEM and the MNC run during normal PLL operation, and the MNC typically converges in a few seconds from a cold start. A preferred DEM has been simulated and succeeds in reducing noise from the FCE mismatches. The MNC cancels DCO phase error arising from FCE mismatch error. Ideal MNC coefficient values are estimated, during PLL normal operation, as part of the feedback loop in a digital fractional-N PLL that incorporates the DCO.

[0060] The center frequency of a conventional digitally-controlled oscillator (DCO) drifts over time due to flicker noise, voltage and temperature variations, and pulling from external interference. Given that the DCO frequency is a non-linear function of the DCO's input signal, this causes the digital PLL's phase noise to increase drastically from time to time because the DCO's input signal slowly drifts to counteract the DCO's center frequency drift. This issue is called spectral breathing because the phase noise spectrum, as viewed on laboratory measurement equipment, appears to swell up every now and then as if it is taking deep breaths of air, during which the PLL's performance is extremely degraded. Moreover, when the PLL is used to generate phase or frequency modulated signals there are no periods between breaths during which the phase noise performance is good. Spectral breathing can drastically degrade a digital PLL's phase noise. Preferred embodiments address spectral breathing by making the relation between the DCO frequency and its input signal linear, which is done at the expense of initially adding more noise to the system. However, this added noise has properties that can be exploited to cancel it, so that the digital PLL's performance is no longer degraded when the DCO's input signal changes. Overall, the price is only a slightly higher power consumption.

[0061] Preferred embodiments provide a new multi-rate DEM technique and an MNC technique that work together within a PLL to solve the problems that arise from FCE mismatches are presented. As in FIG. 1, the preferred embodiment uses integer and fractional FCE banks. In the preferred embodiment, both FCE banks are driven by a multi-rate DEM encoder, which ensures that the error arising from FCE mismatches is free of nonlinear distortion. In addition, the multi-rate DEM encoder avoids high power consumption because most of its digital logic is clocked at a rate of f.sub.in instead of f.sub.fast. Although the hardware of preferred embodiments is different from that of the solution in which d[n.sub.t] is oversampled and a DEM encoder clocked at a high rate is used to control the FCEs, a pessimistic power consumption analysis indicates that the preferred techniques are at least five times more power-efficient. Much of the additive error is not oversampled, so instead of relying on the DCO to suppress it, the MNC technique adaptively measures the error and cancels it in real time.

[0062] Preferred embodiments of the invention will now be discussed with respect to the drawings and experiments used to demonstrate the invention. The drawings may include schematic and/or block representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows.

[0063] FCEs with .sub.i>.sub.min are usually built by connecting nominally identical minimum-weight FCEs in parallel. Static mismatches among these FCEs are sources of error, but other non-idealities such as the non-instantaneous frequency transitions of realizable FCEs are also sources of error. Hence, a more comprehensive model than (11) for f.sub.i(t) is

f.sub.i(t)=(b.sub.i[m.sub.t]).sub.i+e.sub.i(t),(15)

where e.sub.i(t) is error that models both the static mismatch and the non-ideal frequency transitions of the ith FCE. b.sub.i[m] is the FCE's input bit value (either 0 or 1) over the mth clock interval, as defined above in (2). FCEs are designed such that frequency transitions caused by input bit changes settle within a clock period, so e.sub.i(t) only depends on b.sub.i[m.sub.t1] and b.sub.i[m.sub.t]. This can be modeled as

[00007]$\begin{array}{cc}{e}_i\left(t\right)=\{\begin{array}{cc}{e}_{11.Math.i},& \mathrm{if}.Math..Math.b_i\left[m_t-1\right]=1,b_i\left[m_t\right]=1,\\ e_{01.Math.i}\left(t\right),& \mathrm{if}.Math..Math.b_i\left[m_t-1\right]=0,b_i\left[m_t\right]=1,\\ e_{00.Math.i},& \mathrm{if}.Math..Math.b_i\left[m_t-1\right]=0,b_i\left[m_t\right]=0,\\ e_{10.Math.i}\left(t\right),& \mathrm{if}.Math..Math.b_i\left[m_t-1\right]=1,b_i\left[m_t\right]=0\end{array},& \left(16\right)\end{array}$

where e.sub.11i, e.sub.01i(t), e.sub.00i, and e.sub.10i(t) represent the error over each clock interval corresponding to the four different possibilities of the FCE's current and prior input bit values. The FCE model given by (15) and (16) is analogous to that of a non-return-to-zero (NRZ) 1-bit DAC. To prevent e.sub.i(t) from depending on b.sub.i[m.sub.t1], return-to-zero (RZ) FCEs could be implemented by setting the FCEs to a signal-independent state for a fraction of each clock period, but this is not practical for PLLs because it would periodically slew the DCO frequency and thereby introduce excessive phase noise.

[0064] FIG. 2 shows example waveforms associated with (15) and (16). A consequence of the frequency transitions settling within a clock period is that when an FCE's input bit does not change between clock periods, neither does its contribution to the DCO frequency, so e.sub.00i and e.sub.11i are constant. In contrast, e.sub.01i(t) and e.sub.10i(t) are not constant because they represent deviations from the FCE's ideal instantaneous frequency transitions when its input bit changes. As shown in FIG. 2, the shape of each of these frequency transitions depends only on whether the corresponding FCE input changed from 0 to 1 or 1 to 0, and both e.sub.01i(t) and e.sub.10i(t) are 1/f.sub.FCE-periodic.

[0065] Experimental results indicate, at least for the LC-based DCOs presented in [C. Venerus and I. Galton, A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer with a 2.8-3.5 GHz DCO, IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 450-463, February 2015] and [C. Weltin-Wu, E. Familier, and I. Galton, A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], that the frequency transition introduced by each FCE when its input bit changes from 0 to 1 and that when the input bit changes from 1 to 0 are antisymmetric to a high degree of accuracy, i.e., e.sub.11ie.sub.01i(t)=[e.sub.00ie.sub.10i(t)]. Therefore, substituting (16) into (15), applying this observation, collecting terms and omitting constant additive terms yields.

f.sub.i(t)=(b.sub.i[m.sub.t]).sub.i(t).sub.i+(b.sub.i[m.sub.t1]).sub.i(t),(17)

where

.sub.i(t)=1+(e.sub.01i(t)e.sub.00i)/.sub.iand .sub.i(t)=e.sub.11ie.sub.01i(t).(18)

[0066] Given that .sub.i(t) and .sub.i(t) are functions of e.sub.01i(t) and e.sub.10i(t), which are 1/f.sub.FCE-periodic, they are also 1/f.sub.FCE-periodic.

Multi-Rate DEM

[0067] Single-Rate Segmented DEM

[0068] Suppose the DCO's input sequence is given by (3), and for now suppose that quantization is not necessary because FCEs with small-enough step sizes are available, i.e., .sub.min=. Even in this case, FCE mismatches are a problem because they cause nonlinear distortion. A conventional single-rate segmented DEM encoder can be used to prevent this problem. For example, the mismatch-shaping segmented DEM encoder shown in FIG. 3 can be used with 34 FCEs. See, K. L. Chan, N. Rakuljic, and I. Galton, Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3383-3392, December 2008. The ith FCE has input b.sub.i[n.sub.t]=c.sub.i[n.sub.t] and frequency step size .sub.i=K.sub.i, where

K.sub.2i-1=K.sub.2i=2.sup.i1 for i=1,2, . . . ,13, and

K.sub.i=2.sup.13 for i=27,28, . . . ,34.(19)

[0069] The DEM encoder's input sequence, c[n.sub.t], is obtained from the DCO input sequence as

c[n.sub.t]=d[n.sub.t]/+2.sup.15+2.sup.131(20)

[0070] As shown in FIG. 3, the DEM encoder 300 consists of 33 digital switching blocks (SBs) 302, labeled S.sub.k,r for k=1, 2, . . . , 16, and r=1, 2, . . . , 17, configured in a tree structure. The 13 shaded SBs are called segmenting SBs, whereas the other 20 SBs are called non-segmenting SBs. The functional details of the SBs are shown in FIGS. 4A-4C. The top and bottom outputs of each segmenting SB are (c.sub.k,r[n.sub.t]1s.sub.k,1[n.sub.t]) and 1+s.sub.k,1[n.sub.t], respectively, where c.sub.k,1[n.sub.t] is the SB input sequence, and s.sub.k,1[n.sub.t], called a switching sequence, is 0 when c.sub.k,1[n.sub.t] is odd and 1 otherwise. Similarly, the top and bottom outputs of each non-segmenting SB are (c.sub.k,r[n.sub.t]s.sub.k,r[n.sub.t]) and (c.sub.k,r[n.sub.t]+s.sub.k,r[n.sub.t]), respectively, where c.sub.k,r[n.sub.t] is the SB input sequence and s.sub.k,r[n.sub.t] is 0 when c.sub.k,r[n.sub.t] is even and 1 otherwise.

[0071] Regardless of the SB type, each switching sequence is zero-mean and has a first-order highpass-shaped power spectral density (PSD) that peaks at f.sub.in/2. It is generated in two's complement format by the logic shown in FIG. 4C, wherein d.sub.k,r[n.sub.t] is generated within each SB and is well-modeled as a two-level white random sequence that takes on values of 0 and 1 with equal probability and is independent of the d.sub.k,r[n.sub.t] sequences in the other SBs.

[0072] Extension to Multi-Rate Segmented DEM

[0073] Now suppose that the smallest practical FCE frequency step size is .sub.min=2.sup.8. As the lower 16 FCEs in the example above all have frequency step sizes smaller than .sub.min, the bottom 16 outputs of the DEM encoder can no longer drive FCEs directly. The preferred multi-rate DEM architecture 500 in the DCO control logic 501 shown in FIG. 5 addresses this situation, where a bottom 4 FCEs make up a fractional FCE bank 502, the top 18 FCEs make up an integer FCE bank 504, and w.sub.t=p.sub.t1 is a T.sub.fast-delayed version of p.sub.t, where T.sub.fast=.sup.1/f.sub.fast. As in FIG. 1, n.sub.t=g(p.sub.t) changes synchronously with p.sub.t.

[0074] A slow DEM encoder 506 is a modified version of the DEM encoder in FIG. 3. Its outputs c.sub.17[n.sub.t], c.sub.18[n.sub.t], . . . , c.sub.34[n.sub.t] are identical to those in FIG. 3, and instead of outputs c.sub.1[n.sub.t], c.sub.2[n.sub.t], . . . , c.sub.16[n.sub.t] it has an output, x.sub.f[n.sub.t], supplied to a second order digital modulator 508, given by

[00008]$\begin{array}{cc}{x}_f\left[n_t\right]=.Math.\underset{i=1}{\overset{16}{.Math.}}.Math.K_i\left(c_i\left[n_t\right]-1/2\right).& \left(21\right)\end{array}$

[0075] Each c.sub.i[n.sub.t] takes on values of 0 and 1, so (19) and (21) imply that |x.sub.f[n.sub.t]|255 and x.sub.f[n.sub.t] is restricted to multiples of .

[0076] The slow DEM encoder could be implemented from the DEM encoder of FIG. 3 directly by combining c.sub.1[n.sub.t], c.sub.2[n.sub.t], . . . , c.sub.16[n.sub.t] as in (21), but the preferred structure of FIG. 6 provides a simpler and more elegant approach. As implied by FIG. 4B, the sum of the outputs of each non-segmenting SB is equal to the SB's input, so it follows from (21), FIG. 3 and FIG. 4A that x.sub.f[n.sub.t] can be computed directly from the bottom outputs of S.sub.16,1, S.sub.15,1, . . . , S.sub.9,1 as

[00009]$\begin{array}{cc}{x}_f\left[n_t\right]=.Math.\underset{k=9}{\overset{16}{.Math.}}.Math.2^{16-k}.Math.s_{k,1}\left[n_t\right].& \left(22\right)\end{array}$

[0077] Hence, as shown in FIG. 6, S.sub.1,1, S.sub.1,2, . . . , S.sub.1,8 are not necessary in the slow DEM encoder 506.

[0078] The scale factor shown in FIG. 6 is not an actual multiplier; it just denotes that the subsequent digital logic should interpret the LSB of x.sub.f[n.sub.t] to represent a DCO frequency step size of .

[0079] As shown in FIG. 5, x.sub.f[n.sub.t] is sampled at a rate of f.sub.fast by the second-order digital 4E modulator 508, whose functional diagram is shown in FIG. 7. The dither sequence, d.sub.[p.sub.t], is generated such that it can be well-modeled as a two-level white random sequence that is independent of d[n.sub.t] and x.sub.f[n.sub.t] and takes on values of 0 and A with equal probability. It ensures that the modulator's 508 quantization noise is asymptotically independent of x.sub.f[n.sub.t] and d.sub.[p.sub.t], and has a PSD equal to that of the output of a filter with transfer function (1z.sup.1).sup.2 driven by white noise with a variance of .sub.min.sup.2/12. See, S. Pamarti, J. Welz, and I. Galton, Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 3, pp. 492-503, March 2007. The modulator output is quantized to values in the set {2.sub.min, .sub.min, 0, .sub.min, 2.sub.min} and is given by

y.sub.[p.sub.t]=x.sub.f[n.sub.t]+e.sub.[p.sub.t],(23)

where e.sub.[p.sub.t] is second-order highpass-shaped quantization noise plus d.sub.[p.sub.t].

[0080] In FIG. 5, a fast DEM encoder 510 can be a conventional mismatch-shaping non-segmented DEM encoder with a clock rate of f.sub.fast. It is implemented as a tree of non-segmenting SBs, and it maps y.sub.[p.sub.t] to four 1-bit sequences, each of which drives an FCE with a frequency step size of .sub.min.

[0081] Each b.sub.i[w.sub.t] in FIG. 5, for i=1, 2, 3, 4, is clocked at a rate of f.sub.fast and toggles rapidly enough such that the FCE frequency transitions from the fractional FCE bank introduce high-frequency error components to the DCO phase error. Such components are lowpass filtered by the DCO, so f.sub.fast can be chosen so that they are not a problem in practice. Consequently, the frequency transitions of the FCEs from the fractional FCE bank 502 are modeled as ideal, so that f.sub.i(t) is given by (11) for i=1, 2, 3, 4.

[0082] It follows that

f.sub.F(t)=.sub.Fy.sub.[w.sub.t]+e.sub.F(t),(24)

where .sub.F is the average of .sub.i for i=1, 2, 3, 4 and e.sub.F(t) is a function of the errors introduced by the fractional FCE bank 502 and the switching sequences from the fast DEM encoder 510. The fast DEM encoder 510 ensures that e.sub.F(t) is free of nonlinear distortion, uncorrelated with y.sub.[w.sub.t], and has a first-order highpass-shaped PSD that peaks at f.sub.fast/2, so f.sub.fast can be chosen so that this term is not a problem in practice. Thus, substituting (23) into (24) and neglecting e.sub.F(t) gives

f.sub.F(t)=.sub.Fx.sub.f[g(w.sub.t)]+.sub.Fe.sub.[w.sub.t].(25)

[0083] As shown in FIG. 5, the c.sub.17[n.sub.t], c.sub.18[n.sub.t], . . . , c.sub.34[n.sub.t] outputs of the slow DEM encoder 506 drive the same FCEs as those of the DEM encoder of FIG. 3. This implies that f.sub.I(t) is given by

[00010]$\begin{array}{cc}{f}_I\left(t\right)={}_I\left(t\right).Math.d\left[g\left(w_t\right)\right]+{}_I\left(t\right).Math.d\left[g\left(w_t-1\right)\right]+e_I\left(t\right),& \left(26\right)\\ \mathrm{where}& \\ e_I\left(t\right)=.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{{}_{k,r}\left(t\right).Math.s_{k,r}\left[g\left(w_t\right)\right]+{}_{k,r}\left(t\right).Math.s_{k,r}\left[g\left(w_t-1\right)\right]\right\},& \left(27\right)\end{array}$

[0084] .sub.I(t), .sub.I(t), .sub.k,r(t) and .sub.k,r(t) (defined in Appendix A below) are T.sub.fast-periodic waveforms that depend on the errors introduced by the integer FCE bank 504, and the summation indices indicate the summation over all k and r values corresponding to the SBs within the slow DEM encoder 506.

[0085] The contribution to the DCO frequency from both FCE banks 502 and 504 is f.sub.tune(t)=f.sub.I(t)+f.sub.F(t), so (25) and (26) imply that

f.sub.tune(t)=.sub.I(t)d[g(w.sub.t)]+.sub.I(t)d[g(w.sub.t1)]+.sub.Fe.sub.[w.sub.t]+e.sub.M(t),(28)

where

e.sub.M(t)=e.sub.I(t)+.sub.Fx.sub.f[g(w.sub.t)](29)

is called FCE mismatch error. e.sub.M(t) is a linear combination of the switching sequences from the slow DEM encoder whose coefficients depend on the errors introduced by both FCE banks 502 and 504.

[0086] The .sub.I(t)d[g(w.sub.t1)] term in (28) is proportional to a T.sub.fast-delayed version of d[g(w.sub.t)], so it represents a linear filtering operation. This term tends to be much smaller than the desired signal component, .sub.I(t)d[g(w.sub.t)], so it is not a problem in practice. The .sub.Fe.sub.[w.sub.t] term is proportional to quantization noise plus dither so it is free of nonlinear distortion, is uncorrelated with the other terms in (28), and has a highpass-shaped PSD. The e.sub.M(t) term also has these properties because it is a linear combination of the switching sequences from the slow DEM encoder. The PSD of .sub.Fe.sub.[w.sub.t] peaks at f.sub.fast/2, whereas the PSD of e.sub.M(t) peaks at f.sub.in/2. Hence, f.sub.fast can be increased to make the DCO phase error introduced by .sub.Fe.sub.[w.sub.t] negligible, but this would not reduce the DCO phase error contribution from e.sub.M(t). Therefore, e.sub.M(t) is the only problematic term in (28).

[0087] Substituting (22) and (27) into (29) yields

[00011]$\begin{array}{cc}{e}_M\left(t\right)=.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{{}_{k,r}.Math.s_{k,r}\left[g\left(w_t\right)\right]+{}_{k,r}\left(t\right).Math.\left(s_{k,r}\left[g\left(w_t-1\right)\right]-s_{k,r}\left[g\left(w_t\right)\right]\right)\right\},& \left(30\right)\\ .Math.\mathrm{where}& \\ .Math.{}_{k,r}=\{\begin{array}{cc}{}_{k,r}\left(t\right)+{}_{k,r}\left(t\right)+{}_F.Math.2^{16-k},& \mathrm{if}.Math..Math.k9,r=1\\ {}_{k,r}\left(t\right)+{}_{k,r}\left(t\right),& \mathrm{otherwise}\end{array},& \left(31\right)\end{array}$

is constant for each k and r, even though neither .sub.k,r(t) nor .sub.k,r(t) are constant. The non-constant terms in each .sub.k,r(t) are equal in magnitude but opposite in sign to the corresponding terms in .sub.k,r(t), so .sub.k,r(t)+.sub.k,r(t), and hence .sub.k,r, are constant. Therefore, the terms proportional to .sub.k,r, in (30) represent the DCO frequency error contribution from FCE static gain errors, whereas the terms proportional to .sub.k,r(t) in (30) represent the DCO frequency error contribution from non-ideal FCE frequency transitions.

Adaptive FCE Mismatch Noise Cancellation

[0088] The purpose of the present MNC is to cancel most of the DCO phase error that would otherwise be caused by e.sub.M(t). To do this, the sequence

[00012]$\begin{array}{cc}{e}_{\mathrm{MNC}}\left[p_t\right]=.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{{}_{k,r}.Math.s_{k,r}\left[n_t\right]+b_{k,r}\left(s_{k,r}\left[g\left(w_t\right)\right]-s_{k,r}\left[n_t\right]\right)\right\},& \left(32\right)\end{array}$

where a.sub.k,r, and b.sub.k,r are called the MNC coefficients, is injected into the fractional path of the multi-rate DEM encoder. The ideal MNC coefficient values, i.e., the values of a.sub.k,r, and b.sub.k,r, for which the DCO phase error contribution of e.sub.M(t) is minimized, are estimated with a least-mean-square (LMS)-like algorithm. The algorithm is similar to a conventional LMS algorithm in the sense that it consists of a set of coefficients that are updated over time based on how strongly known signals are correlated to an error measurement.

[0089] We next explain how e.sub.MNC[p.sub.t] affects the DCO's phase error, how the FCE mismatch error is measured, and how the MNC coefficients are adaptively computed from the FCE mismatch error measurement.

[0090] MNC Sequence Application

[0091] FIG. 8 shows the fractional path of the multi-rate DEM encoder shown in FIG. 5 modified to accommodate MNC. The e.sub.MNC[p.sub.t] sequence (determined by FIGS. 11A-11C, discussed below) is subtracted from x.sub.f[n.sub.t] prior to the modulator, and the output range of the modulator 508, the range of the fast DEM encoder 510, and the number of FCEs of the FCE bank 502 driven by the fast DEM encoder 510 are all four times those of the original FIG. 5 system to accommodate the resulting dynamic range increase. Thus, f.sub.F(t) is still given by (24), but now .sub.[p.sub.t] is given by the right side of (23) minus e.sub.MNC[p.sub.t]. Despite having the same qualitative properties as before, .sub.F and e.sub.F(t) in (24) are slightly different in the modified system because of the additional FCEs.

[0092] An analysis shows that f.sub.time(t) is now given by

f.sub.tune(t)=.sub.I(t)a[g(w.sub.t)]+.sub.I(t)d[g(w.sub.t1)]+.sub.Fe.sub.[w.sub.t]+e.sub.R(t),(33)

where

e.sub.R(t)=e.sub.M(t).sub.Fe.sub.MNC[w.sub.t](34)

is the residual FCE mismatch error, i.e., what is left of e.sub.M(t) when e.sub.MNC[p.sub.t] is applied. It follows from (30), (32) and (34) that

[00013]$\begin{array}{cc}{e}_R\left(t\right)=.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{{}_{k,r-\mathrm{res}}.Math.s_{k,r}\left[g\left(w_t\right)\right]+{}_{k,r-\mathrm{res}}\left(t\right).Math.\left(s_{k,r}\left[g\left(w_t-1\right)\right]-s_{k,r}\left[g\left(w_t\right)\right]\right)\right\},& \left(35\right)\end{array}$

respectively.

[0093] Given that .sub.k,r is constant, there exists an a.sub.k,r that causes .sub.k,r-res=0. In contrast, there is no b.sub.k,r that causes .sub.k,r-res(t) to vanish completely, because .sub.k,r(t) is not constant. However, .sub.k,r(t) is T.sub.fast-periodic so there exists a b.sub.k,r that makes the DC component of .sub.k,r-res(t) zero, such that .sub.k,r-res(t) is a linear combination of sinusoids with frequencies that are non-zero multiples of f.sub.fast. Therefore, it follows from Error! Reference source not found. that if

[00014]$\begin{array}{cc}{a}_{k,r}=\frac{{}_{k,r}}{{}_F}.Math..Math.\mathrm{and}.Math..Math.b_{k,r}=\frac{1}{{}_F.Math.T_{\mathrm{fast}}}.Math.{}_0^{T_{\mathrm{fast}}}.Math.{}_{k,r}\left(\right).Math.d.Math..Math.,& \left(36\right)\end{array}$

for each k and r, then

.sub.k,r-res=0 and .sub.0.sup.T.sup.fast.sub.k,r-res()d=0.(37)

[0094] In the absence of FCE static mismatches, a.sub.k,r=0, and if the FCE frequency transitions are ideal, b.sub.k,r=0.

[0095] Phase error is the integral of frequency error, so the DCO phase error introduced by e.sub.R(t) is given by

.sub.R(t)=.sub.0.sup.te.sub.R()d.(38)

[0096] If (37) is satisfied, then (35) and (38) imply that

[00015]$\begin{array}{cc}{}_R\left(t\right)=.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left(s_{k,r}\left[g\left(w_t-1\right)\right]-s_{k,r}\left[g\left(w_t\right)\right]\right).Math.{}_0^{t-p_t.Math.T_{\mathrm{fast}}}.Math.{}_{k,r-\mathrm{res}}\left(u\right).Math.\mathrm{du},& \left(39\right)\end{array}$

where tp.sub.tT.sub.fast=tf.sub.fasttT.sub.fast<T.sub.fast. The term within the parenthesis in (39) equals zero when g(w.sub.t)g(w.sub.t1)=0 and s.sub.k,r[g(w.sub.t)1] s.sub.k,r[g(w.sub.t)] otherwise. Given that g(w.sub.t)g(w.sub.t1) can only take on values from the set {0, 1}, then

s.sub.k,r[g(w.sub.t1)]s.sub.k,r[g(w.sub.t)]=(g(w.sub.t)g(w.sub.t1))(s.sub.k,r[g(w.sub.t)1]s.sub.k,r[g(w.sub.t)]).(40)

[0097] Furthermore, g(w.sub.t) is a T.sub.fast-delayed version of n.sub.t, which increases by one unit every T.sub.in=1/f.sub.in, so g(w.sub.t)g(w.sub.t1) is T.sub.in-periodic and is given by

[00016]$\begin{array}{cc}g\left(w_t\right)=g\left(w_t-1\right)=\underset{k=-}{\overset{}{.Math.}}.Math.r\left(t-{\mathrm{kT}}_{i.Math..Math.n}\right),& \left(41\right)\end{array}$

where r(t)=1 for t[T.sub.fast, 2T.sub.fast) and 0 otherwise. It follows from (41) that the Fourier expansion of g(w.sub.t)g(w.sub.t1) is

[00017]$\begin{array}{cc}\frac{f_{i.Math..Math.n}}{f_{\mathrm{fast}}}+\underset{m=1}{\overset{}{.Math.}}.Math.\frac{2}{m.Math..Math.}.Math.\sin \left(m.Math..Math..Math.\frac{f_{i.Math..Math.n}}{f_{\mathrm{fast}}}\right).Math.\cos \left(2.Math..Math..Math.{\mathrm{mf}}_{i.Math..Math.n}\left[t-\frac{3}{2}.Math.T_{\mathrm{fast}}\right]\right).& \left(42\right)\end{array}$

[0098] Thus, if the conditions shown in (37) are satisfied, (39), (40) and (42) imply that .sub.R(t) would be given by second-order shaped noise multiplied by a T.sub.in-periodic waveform and a DC-free T.sub.fast-periodic waveform. Consequently, e.sub.R(t) would introduce components with frequencies around f.sub.n,m=nf.sub.fastmf.sub.in to the DCO's phase error, where n=1, 2, 3, . . . and m=0, 1, 2, . . . . It follows from (42) that the power of the components around frequencies f.sub.n,m with m near multiples of f.sub.fast/f.sub.in is very low. Therefore, .sub.R(t) would not be a problem if f.sub.fast is large enough because e.sub.R(t) would only introduce high-frequency components to the DCO's phase error that would be lowpass filtered by the DCO. Simulation results also suggest that .sub.R(t) is not a problem provided the conditions shown in (37) are satisfied and f.sub.fast is large enough.

[0099] FCE Mismatch Error Measurement

[0100] The ideal MNC coefficient values are estimated as part of a feedback loop in a digital fractional-N PLL that incorporates the DCO. This is done during the PLL's normal operation by adaptively adjusting a.sub.k,r, and b.sub.k,r, such that the conditions shown in (37) are satisfied for each k and r, thereby minimizing e.sub.R(t).

[0101] The purpose of a fractional-N PLL is to generate a periodic output signal, v.sub.PLL(t), with frequency f.sub.PLL=(N+)f.sub.ref, where N is a positive integer, is a fractional value and f.sub.ref is the frequency of a reference oscillator waveform, v.sub.ref(t). The general form of a digital fractional-N PLL without MNC is shown in FIG. 9. It consists of a phase-error-to-digital converter (PEDC) 902, a lowpass digital loop filter (DLF) 904, and a DCO 906. The PEDC's 902 output is an f.sub.ref-rate digital sequence of the form

p[n]=.sub.PLL[n]+e.sub.p[n],(43)

where .sub.PLL[n] is an estimate of the PLL's phase error and e.sub.p[n] is additive error that includes quantization error from the PEDC's 902 digitization process as well as error from circuit noise and other non-ideal circuit behavior in both the PEDC and reference oscillator.

[0102] A modified version of the DCO 906 contains the preferred multi-rate DEM structure of FIG. 5 with the MNC correction of FIG. 8 with f.sub.in=f.sub.ref. Typically, f.sub.fast-clk is a divided-down version of v.sub.PLL(t). Given that f.sub.PLL=(N+)f.sub.ref, f.sub.ref and f.sub.fast are incommensurate frequencies when 0, it is not possible for n.sub.t to change synchronously with p.sub.t=f.sub.fastt if n.sub.t=f.sub.reft. Therefore, as shown in FIGS. 10A & 10B, in practice the DCO input is synchronized to f.sub.fast-clk so (4) is satisfied, i.e., so n.sub.t only changes at times .sub.n, which are multiples of T.sub.fast, instead of times nT.sub.ref, where T.sub.ref=1/f.sub.ref is the reference period. It is common practice in digital PLLs to synchronize the DLF 904 output to the clock signal of the fractional path, so this is not a special requirement of the proposed system. A conventional circuit to avoid metastability issues is also needed as part of the synchronization circuit shown in FIG. 10A, but it has been omitted for simplicity.

[0103] A requirement of a PLL is to suppress low-frequency DCO error, which is achieved by subjecting additive frequency error introduced by the DCO to a highpass filter that has at least one zero at DC. In the following, the impulse response of this filter is denoted as h[n], and its running sum, i.e., h[0]+h[1]+ . . . +h[n], is denoted as l[n]. p[n] can be written as

p[n]=p.sub.ideal[n]+p.sub.R[n],(44)

[0104] where p.sub.ideal[n] represents the contribution to p[n] of all noise sources except FCE mismatches and p.sub.R[n] is the contribution to p[n] from e.sub.R(t). Specifically, p.sub.R[n] (with references to definitions in Appendix B) is given by

[00018]$\begin{array}{cc}{p}_R\left[n\right]={}_F.Math.T_{\mathrm{fast}}.Math.\underset{i=0}{\overset{n-1}{.Math.}}.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{y_{k,r-a}\left[i\right]+y_{k,r-b}\left[i\right]\right\}.Math.l\left[n-1-i\right],& \left(45\right)\end{array}$

where y.sub.k,r-a[t]+y.sub.k,r-b[i] is proportional to the PLL's frequency error introduced by the s.sub.k,r[n] sequences. If a.sub.k,r and b.sub.k,r in (32) are replaced by a.sub.k,r[n.sub.t] and b.sub.k,r[n.sub.t], respectively, then

y.sub.k,r-a[i]=(q.sub.i13)s.sub.k,r[i1]a.sub.k,r-error[i1]+3s.sub.k,r[i]a.sub.k,r-error[i](46)

and

a.sub.k,r-b[i]=(s.sub.k,r[i1]s.sub.k,r[i])b.sub.k,r-error[i],(47)

[0105] where q.sub.i1 is the number of T.sub.fast periods between times .sub.i1 and .sub.i, and

a.sub.k,r-error[n]=a.sub.k,r[n]a.sub.k,r and b.sub.k,r-error[n]=b.sub.k,r[n]b.sub.k,r (48)

are the MNC coefficient errors at sample time n.

[0106] The term proportional to s.sub.k,r[i] in (46) arises because the time at which the PEDC 902 samples the PLL's phase error, which is given by .sub.n+4T.sub.fast in the design example, is not equal to the time at which the integer FCE bank's inputs are updated, i.e., .sub.n+T.sub.fast. Accordingly, the integer FCE bank's inputs are updated three T.sub.fast before the PLL's phase error is sampled, which causes y.sub.k,r-a[i] to depend on s.sub.k,r[i1] and also on s.sub.k,r[i]. As implied by (44)-(47), the PEDC's 902 output has information regarding the MNC coefficient errors. The MNC coefficient estimation process described next is based on this result and on the properties of the switching sequences.

[0107] MNC Coefficients Estimation

[0108] A digital fractional-N PLL with the multi-rate DEM encoder and MNC technique is shown in FIG. 11A. The details of MNC logic 1102 are shown in FIG. 11B and FIG. 11C, wherein

[00019]$\begin{array}{cc}{t}_{k,r}\left[n\right]=\underset{i=0}{\overset{n}{.Math.}}.Math.s_{k,r}\left[i\right]& \left(49\right)\end{array}$

is the running sum of s.sub.k,r[n], and K.sub.a and K.sub.b are called the MNC gains. The MNC logic block consists of an adder and 25 s.sub.k,r[n.sub.t] residue estimators 1104.

[0109] It follows from FIG. 4 that each s.sub.k,r[n] sequence is a concatenation of sequences of the form 1, 0, . . . , 0, 1, 0, . . . , 0 or 1, 0, . . . , 0, 1, 0, . . . , 0, where each 0 is present only when the input of the s.sub.k,r[n] generator is zero. Thus, |s.sub.k,r[n]|1, |s.sub.k,r[n]|1 and |s.sub.k,r[n]s.sub.k,r[n1]|2 for all n, so the multipliers in FIG. 11(c) are simple in terms of hardware.

[0110] The s.sub.k,r[n.sub.t] residue estimators 1104 are responsible for the computation of the MNC coefficients. At each sample time, the MNC coefficient errors are measured and a.sub.k,r[n.sub.t] and b.sub.k,r[n.sub.t] are updated such that they approach the values shown in (36). The measurement of the MNC coefficient errors is based on the statistical properties of the switching sequences.

[0111] Although each s.sub.k,r[n] sequence depends on the input of its corresponding SB, when it is non-zero, its sign depends on d.sub.k,r[n]. Given that the d.sub.k,r[n] sequences are independent of the d.sub.k,r[n] sequences in the other SBs, this provides enough randomization for the s.sub.k,r[n] sequences to be uncorrelated with each other. Furthermore, as the d.sub.k,r[n] sequences are also independent of all electronic device noise sources in the PLL, each s.sub.k,r[n] sequence is uncorrelated with all such sources as well, and it is also uncorrelated with the PEDC's 902 quantization noise in PLLs where such noise source is uncorrelated with the PLL's phase error.

[0112] Hence, in such cases, the s.sub.k,r[n] sequences are uncorrelated with all PLL noise except the terms in p[n] arising from e.sub.R(t), i.e., p.sub.R[n].

[0113] The y.sub.k,r-a[i] and y.sub.k,r-b[i] terms in p[n] depend on the MNC coefficient errors, and such terms are proportional to functions of the s.sub.k,r[n] sequences. Specifically, it can be seen from (44)-(47) that p[n] has information about an accumulated version of

(q.sub.n23)s.sub.k,r[n2]a.sub.k,r-error[n2],(50)

and that p[n]p[n1] has information about

(s.sub.k,r[n2]s.sub.k,r[n1])b.sub.k,r-error[n1].(51)

[0114] Therefore, it follows that the accumulator inputs in FIG. 11C, i.e., p[n]t.sub.k,r[n2] and (p[n1]p[n])(s.sub.k,r[n2]s.sub.k,r[n1]), when non-zero, are noisy estimates of a.sub.k,r-error[n] and b.sub.k,r-error[n], respectively, so they can be used to adaptively compute the ideal MNC coefficients. In practice, the top and bottom branches within each s.sub.k,r[n.sub.t] residue estimator 1104 interfere with each other in a way that makes the accumulator inputs have information about both MNC coefficient errors. However, extensive simulations indicate that the MNC coefficient values converge to their ideal values regardless of such interferences provided the MNC gains are set properly to avoid instability in the feedback loops.

[0115] It would also be possible to correlate p[n1]p[n] by s.sub.k,r[n2] to get an estimate of a.sub.k,r-error[n]. However, as a.sub.k,r[n] is only updated when the accumulator input is non-zero, correlating p[n1]p[n] against s.sub.k,r[n2] instead of p[n] against t.sub.k,r[n2] would significantly decrease the convergence speed of a.sub.k,r[n] because normally s.sub.k,r[n2] is zero more often than t.sub.k,r[n2]. Although correlating p[n] against t.sub.k,r[n2] effectively increases the error variance of a.sub.k,r[n], as explained next, this problem can be mitigated by reducing K.sub.a.

[0116] As is common in most LMS-like algorithms, the choice of K.sub.a and K.sub.b represents a tradeoff. The larger the MNC gains, the faster the convergence, but the larger the error variance of a.sub.k,r[n] and b.sub.k,r[n]. Also, as the s.sub.k,r[n.sub.t] residue estimators comprise two LMS-like loops in parallel that interfere with each other, K.sub.a and K.sub.b each affect the convergence time and error variance of both a.sub.k,r[n] and b.sub.k,r[n]. Although it might be possible to develop closed-form expressions that quantify these tradeoffs, the authors currently use simulations to assist the design process and to choose the values of K.sub.a and K.sub.b.

Simulation Results

[0117] The multi-rate DEM and the MNC methods of the preferred embodiments described above were tested in an event-driven behavioral simulation of a modified version of the frequency-to-digital converter based fractional-N PLL presented in [C. Weltin-Wu, G. Zhao, and I. Galton, A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation, IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015; C. Weltin-Wu, G. Zhao, and I. Galton, A 3.5 GHz Digital Fractional-N Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion, IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2988-3002, December 2015]. As explained in [C. Weltin-Wu, E. Familier, and I. Galton, A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], p[n] is given by (43) where e.sub.p[n] is first-order shaped quantization noise that is uncorrelated with the PLL's phase error plus error from both the PEDC and reference oscillator.

[0118] The DLF consists of two single-pole IIR stages and a proportional-integral stage. Its transfer function is

[00020]$\begin{array}{cc}L\left(z\right)=K_M\left(K_P+\frac{K_I}{1-z^{-1}}\right).Math.\underset{i=0}{\overset{1}{.Math.}}.Math.\frac{{}_i}{1-\left(1-{}_i\right).Math.z^{-1}},& \left(52\right)\end{array}$

where K.sub.M, K.sub.P, K.sub.I, .sub.0 and .sub.1 are constant loop filter parameters. The DCO consists of an LC oscillator core with a power-of-two-weighted coarse capacitor bank, an integer FCE bank 502 and a fractional FCE bank 504 in accordance with FIG. 5. The latter two are driven by the multi-rate DEM encoder 500 shown in FIG. 5 and modified as shown in FIG. 8 with f.sub.fast=f.sub.PLL/8 and .sub.min=40 kHz (i.e., =156.25 Hz).

[0119] The static gain error of the ith FCE was modeled as an additive zero-mean Gaussian random variable with a standard deviation of 5% of .sub.i divided by the square root of .sub.i/.sub.min. The FCE frequency transitions were modeled as second-order transients that settle within one T.sub.fast period. The parameters of these transients, such as the damping factor and the natural frequency, are modelled as random variables with means and standard deviations determined from transistor-level simulation results. FIG. 12 shows example frequency transients used in the simulation.

[0120] The simulated noise parameters of the DCO and the reference oscillator, as well as the PEDC internal parameters were f.sub.ref=26 MHz, N=134 and =0.0003846153, so that f.sub.PLL=3.484 GHz and f.sub.fast=435.5 MHz. The DLF parameters used were K.sub.M=1.25, K.sub.P=2.sup.4, K.sub.I=2.sup.4, .sub.0=2.sup.3 and .sub.1=2.sup.2, and the MNC gains were set to K.sub.a=2.sup.3 and K.sub.b=2.sup.5. The simulated PLL has a bandwidth of 206 kHz and a phase margin of 63 degrees.

[0121] FIG. 13A shows the simulated PLL phase noise PSD with the multi-rate DEM technique disabled, i.e., with the flip-flops in both the slow and fast DEM encoders frozen. The two curves in FIG. 13A were obtained from two different simulations: one in which d.sub.I[n.sub.t] is constant and another one in which d.sub.I[n.sub.t] changes frequently. Although the DCO input sequence does not vary significantly in the short term once the PLL is locked, its moving average drifts over time such that d.sub.I[n.sub.t] eventually begins to change frequently, at which point it degrades the PLL's phase noise as shown in FIG. 13A. Once the multi-rate DEM technique is enabled, whether or not d.sub.I[n.sub.t] changes has no significant effect on the DCO's frequency, so spectral breathing no longer occurs.

[0122] FIG. 13B shows the simulated PLL phase noise PSD with the multi-rate DEM technique enabled for two cases: one case with just static gain errors, and the other case with just non-ideal frequency transitions. FIG. 13C shows the simulated PLL phase noise PSD considering both sources of error with the multi-rate DEM technique enabled and with the MNC technique disabled and enabled. The theoretical PLL phase noise PSD for ideal FCEs, which was computed using the linearized model presented in [C. Weltin-Wu, E. Familier, and I. Galton, A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], is also plotted as the dashed curves in FIGS. 13A-13C to provide a comparison baseline.

[0123] As shown in FIG. 13A, when the MNC technique is enabled the resulting phase noise PSD matches the theoretically-predicted phase noise PSD for ideal FCEs after 13.Math.10.sup.7 reference periods (5 seconds) from a cold start. This implies a phase noise improvement of more than 20 dB at an offset frequency around 10 MHz. As the FCE mismatches are mostly determined by circuit component mismatches, they are not expected to change significantly over time. Hence, once obtained, the MNC coefficients can be stored in memory and used subsequently by the PLL, thereby avoiding future convergence time delays.

[0124] FIG. 14 shows the evolution of the MNC coefficient errors over time from the simulation used to generate the curves in FIG. 13C. As shown in FIG. 14, some b.sub.k,r[n] coefficients initially move away from their ideal values. As explained above, this happens because the top and bottom branches of each s.sub.k,r[n.sub.t] residue estimator interfere with each other so that the error estimate at the input of each accumulator is biased by the MNC coefficient error of the opposite branch. If the MNC gains are set as in FIGS. 14A and 14B, this is not a problem because this effect becomes less significant as either one or both MNC coefficients approach their ideal values.

[0125] It follows from (46) and (47) that the terms proportional to a.sub.k,r-error[n] in p[n] are q.sub.n3 times larger than those proportional to b.sub.k,r-error[n] (e.g., q.sub.n16 in the design example), so for K.sub.a=K.sub.b, the error variance of each b.sub.k,r[n] is expected to be larger than that of a.sub.k,r[n]. Therefore, in order to make the error variance of the b.sub.k,r[n] coefficients comparable to that of the a.sub.k,r[n] coefficients, K.sub.b has to be smaller than K.sub.a. As shown in FIGS. 14A & 14B, this causes the b.sub.k,r[n] coefficients to converge to their ideal values at a slower rate than the a.sub.k,r[n] coefficients, so the convergence speed of the MNC technique is limited by K.sub.b. Nonetheless, it follows from FIGS. 14A & 14B that the a.sub.k,r[n] coefficients get close to their ideal values in less than 10.sup.7 reference periods (0.4 seconds). Hence, as the most significant sources of phase noise are the FCE static gain errors, the MNC method allows for a considerable phase noise improvement in less than half a second.

[0126] To reduce the cold-start convergence time of the MNC technique, large MNC gains can be used initially and decreased over time. See, W. Y. Chen and R. A. Haddad, A Variable Step Size LMS Algorithm, Proc. 33.sup.rd Midwest Symp. Circuits and Systems, pp. 423-426, August 1990. FIGS. 15A and 15B shows the evolution of the MNC coefficient errors over time for 7.8.10.sup.7 reference periods (3 seconds) for an example case in which K.sub.a and K.sub.b are initially set to 2.sup.1 and 2.sup.2, respectively, and then divided by two at the times indicated by the vertical dashed lines. In this case, the MNC coefficients reach the final values shown in FIGS. 14A & 14B in roughly 3 seconds, and the a.sub.k,r[n] coefficients get close to their ideal values in less than 2.Math.10.sup.6 reference periods (0.08 seconds), which is five times faster than in FIGS. 14A & 14B.

Appendix A

[0127] It follows from FIG. 5 and (17) that

[00021]$\begin{array}{cc}{f}_I\left(t\right)=\underset{i=5}{\overset{22}{.Math.}}.Math.\left[\left(b_i\left[w_t\right]-1/2\right).Math.{}_i\left(t\right).Math.{}_i+\left(b_i\left[w_t-1\right]-1/2\right).Math.{}_i\left(t\right)\right].& \left(53\right)\end{array}$

[0128] Expressions for each b.sub.i[w.sub.t]=c.sub.i+12[g(w.sub.t)] in terms of d[g(w.sub.t)] and the switching sequences can be found by tracing through the tree of FIG. 6 and applying (20) and the expressions shown in FIG. 4(a) and FIG. 4(b). This leads to

[00022]$\begin{array}{cc}{c}_i\left[g\left(w_t\right)\right]-1/2=m_i.Math.d\left[g\left(w_t\right)\right]/+\underset{k,r}{\overset{}{.Math.}}.Math.{}_{k,r,i}.Math.s_{k,r}\left[g\left(w_t\right)\right],& \left(54\right)\end{array}$

where

m.sub.i=0 for 17i26 and m.sub.i=2.sup.16 for 27i34,(55)

and each x.sub.k,r,i is one of 0, , , 2.sup.k or 2.sup.k. Combining (4)(19) and (53)-(55) yields (26) and (27), where .sub.I(t) and .sub.I(t) are the averages of .sub.i(t) and (2.sup.13/).sub.i(t) for i=15, 16, . . . , 22, respectively,

[00023]$\begin{array}{cc}{}_{k,r}\left(t\right)=\underset{i=5}{\overset{22}{.Math.}}.Math.{}_i\left(t\right).Math.K_{i+12}.Math.{}_{k,r,i+12}.Math..Math.\mathrm{and}.Math..Math.{}_{k,r}\left(t\right)=\underset{i=5}{\overset{22}{.Math.}}.Math.\frac{{}_i\left(t\right)}{}.Math.{}_{k,r,i+12}.& \left(56\right)\end{array}$

[0129] Each .sub.I(t), .sub.I(t), .sub.k,r(t) and .sub.k,r(t) is T.sub.fast-periodic, because it is a linear combination of .sub.I(t) and .sub.i(t), which are T.sub.fast-periodic.

Appendix B

[0130] The phase error of the digital PLL shown of FIG. 9 is given by

.sub.PLL(t)=.sub.0.sup.tv.sub.PLL(u)du,(57)

where .sub.PLL(t) is the PLL's frequency error at time t. The .sub.PLL[n] term in (43) is a sampled version of .sub.PLL(t) given by

.sub.PLL[n]=.sub.PLL(.sub.n),(58)

where .sub.n=nT.sub.ref+ and .sub.n is a small implementation-dependent deviation of .sub.n from its ideal value. It follows from (43), (57) and (58) that

[00024]$\begin{array}{cc}p\left[n\right]=p\left[0\right]-T_{\mathrm{ref}}.Math.\underset{i=1}{\overset{n}{.Math.}}.Math.{}_{\mathrm{PLL}}\left[i\right]+e_p\left[n\right],& \left(59\right)\end{array}$

where

[00025]$\begin{array}{cc}{}_{\mathrm{PLL}}\left[i\right]=\frac{1}{T_{\mathrm{ref}}}.Math.{}_{{}_{i-1}}^{{}_i}.Math.{}_{\mathrm{PLL}}\left(u\right).Math.\mathrm{du}& \left(60\right)\end{array}$

is the PLL's average frequency error over the time interval [.sub.i,1, .sub.i] and p[0] is the initial value of p[n]. FIG. 9 and (60) imply that e.sub.R(t) causes a term in .sub.PLL[i] given by

[00026]$\begin{array}{cc}\left\{e_R*h\right\}\left[i\right]=\underset{j=0}{\overset{}{.Math.}}.Math.h\left[j\right].Math.e_R\left[i-j\right],& \left(61\right)\\ \mathrm{where}& \\ e_R\left[i\right]=\frac{1}{T_{\mathrm{ref}}}.Math.{}_{{}_{i-1}}^{{}_i}.Math.e_R\left(u\right).Math.\mathrm{du}& \left(62\right)\end{array}$

and h[j] is the impulse response of the highpass filtering operation imposed by the PLL on the DCO's additive frequency error as discussed in the description above.

[0131] In the design example of the example embodiment .sub.n=4.2T.sub.fast+T.sub.fastv[n], where v[n] is an integer-valued sequence restricted to the set {6, 5, . . . , 5, 6}, so .sub.n=nT.sub.ref+4.2T.sub.fast+T.sub.fastv[n]. As the magnitude of T.sub.fastv[n] is at most T.sub.fast, its effect is negligible. Furthermore, for the sake of simplicity, .sub.n is assumed to be given by

.sub.n=.sub.n+4T.sub.fast,(63)

where .sub.n, as shown FIG. 10B, is a multiple of T.sub.fast. Given that 0<.sub.nnT.sub.refT.sub.fast for all n and that T.sub.fast is a small fraction of T.sub.ref, this approximation does not significantly affect the following results. Substituting Error! Reference source not found. with a.sub.k,r and b.sub.k,r replaced by a.sub.k,r[g(w.sub.t)] and b.sub.k,r[g(w.sub.t)], respectively, into (35), and the result of this operation and (63) into (62) yields

[00027]$\begin{array}{cc}{e}_R\left[i\right]=\frac{}{T_{\mathrm{ref}}}.Math.{}_{{}_{i-1}+4.Math.T_{\mathrm{fast}}}^{{}_i+4.Math.T_{\mathrm{fast}}}.Math.\left\{\left({}_{k,r}-{}_F.Math.a_{k,r}\left[g\left(w_t\right)\right]\right).Math.s_{k,r}\left[g\left(w_t\right)\right]+\left({}_{k,r}\left(t\right)-{}_F.Math.b_{k,r}\left[g\left(w_t\right)\right]\right).Math.\left(s_{k,r}\left[g\left(w_t-1\right)\right]-s_{k,r}\left[g\left(w_t\right)\right]\right)\right\}.Math.\mathrm{dt}.& \left(64\right)\end{array}$

[0132] Given that t[.sub.n, .sub.n+1) implies g(p.sub.t)=n1, it follows that g(w.sub.t)=i2 for t[.sub.i1+T.sub.fast, .sub.i+T.sub.fast) and g(w.sub.t)=i1 for t[.sub.i+T.sub.fast, .sub.i+T.sub.fast), so (64) can be written as

[00028]$\begin{array}{cc}{e}_R\left[i\right]=-.Math.\frac{{}_F.Math.T_{\mathrm{fast}}}{T_{\mathrm{ref}}}.Math.\underset{k,r}{\overset{}{.Math.}}.Math.\left\{{}_{k,r-a}\left[i-1\right]+y_{k,r-b}\left[i-1\right]\right\},& \left(65\right)\end{array}$

where y.sub.k,r-a[i] and y.sub.k,r-b[i] are given by (46) and (47), respectively, and it has been assumed that q.sub.i=(.sub.i+1.sub.i)/T.sub.fast is greater than 3 for all i (e.g., q.sub.i16 in the design example). Substituting (65) into (61) and the result into (59), rearranging terms and considering that s.sub.k,r[n]=0 for n<0 gives (44) and (45)

[0133] While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

[0134] Various features of the invention are set forth in the appended claims.