Circuit and method for driving a laser diode

Abstract

A driver circuit for driving a laser diode is described herein. In accordance with a first exemplary embodiment the driver circuit includes a first electronic switch connected to an output node that is configured to be operably connected to a laser diode. The electric connection between the first electronic switch and the output node has a first inductance. The driver circuit further includes a bypass circuit that is coupled to the output node and configured to take over, when activated, the current supplied to the output node via the first electronic switch, thus magnetizing the first inductance.

Claims

1. A driver circuit for driving a laser diode, the driver circuit comprising: a first electronic switch connected to an output node that is configured to be operably connected to the laser diode; the electric connection between the first electronic switch and the output node having a first inductance; and a bypass circuit coupled to the output node and configured to take over, when activated, the current supplied to the output node via the first electronic switch, thus magnetizing the first inductance.

2. The driver circuit of claim 1, wherein the electric connection between the output node and the bypass circuit has a second inductance, which is also magnetized when the bypass circuit is active.

3. The driver circuit of claim 1, further comprising a clamping circuit coupled to the first electronic switch configured to limit a voltage drop across the electronic switch in accordance with a clamping voltage.

4. The driver circuit of claim 1, further comprising a clamping circuit coupled to the first electronic switch; the clamping circuit being configured, during switch-off of the first electronic switch, to delay the switch-off in order to allow the first inductance to demagnetize.

5. The driver circuit of claim 1, further comprising a first driver coupled to a control electrode of the first electronic switch, the first driver being configured to generate a drive signal to switch the first electronic switch on an off in accordance with a first control signal.

6. The driver circuit of claim 5, further comprising a first delay circuit coupled to the first driver and configured to delay the first control signal by an adjustable delay time.

7. The driver circuit of claim 1, wherein the bypass circuit includes a second electronic switch connected to the output node; the electric connection between the second electronic switch and the output node having a second inductance.

8. The driver circuit of claim 7, wherein the bypass circuit further includes a clamping circuit coupled to the second electronic switch; the clamping circuit being configured to take over current passing through the second inductance, when the second electronic switch is switched off.

9. The driver circuit of claim 7, further comprising a second driver coupled to a control electrode of the second electronic switch, the second driver being configured to generate a drive signal to switch the second electronic switch on an off in accordance with a second control signal.

10. The driver circuit of claim 9, further comprising a second delay circuit coupled to the second driver and configured to delay the second control signal by an adjustable delay time.

11. The driver circuit of claim 1, further comprising a capacitor coupled between the first electronic switch and the output node, to decouple DC current passing from the first electronic switch to the output node.

12. The driver circuit of claim 11, further comprising a third electronic switch coupled in operably parallel to the laser diode.

13. The driver circuit of claim 1, further comprising a half-bridge including a third electronic switch and a fourth electronic switch coupled between a supply node and a ground node, the middle tap of the half-bridge forming a further output node configured to be operably coupled to the laser diode, so that the laser diode is coupled between the output node and the further output node.

14. The driver circuit of claim 13, wherein the electric connection between the third electronic switch and the further output node having a third inductance; and wherein the electric connection between the fourth electronic switch and the further output node having a fourth inductance.

15. The driver circuit of claim 14, further comprising: a clamping circuit coupled to the third electronic switch; the clamping circuit being configured to take over current passing through the third inductance, when the third electronic switch is switched off; and a further clamping circuit coupled to the fourth electronic switch; the further clamping circuit being configured to take over current passing through the fourth inductance, when the fourth electronic switch is switched off.

16. A driver circuit for driving a laser diode, the driver circuit comprising: a first and a second transistor half-bridge forming a H-bridge that has a first output node and a second output node configured to operably couple the laser diode in between, each transistor half-bridge being composed of a high-side transistor and a low-side transistor; and control circuitry configured to: switch on, in a pre-charging phase, the high-side and the low-side transistors of the first and the second transistor half-bridges to magnetize any inductances coupled in series to the high-side and the low-side transistors; and switch off, in a ramp-up phase, the low-side transistor of the first transistor half-bridge and the high-side transistor of the second transistor half-bridge, thus directing current, which passes through the high-side transistor of the first transistor half-bridge and the low-side transistor of the second transistor half-bridge and through inductances coupled in series thereto, through the laser diode via the first and the second output node.

17. A method for driving a laser diode, the method comprising: directing a first current, via a first electronic switch to an output node operably coupled to the laser diode thus magnetizing a first inductance effective between the first electronic switch and the output node; draining the first current, by activating a bypass circuit, from the output node thud bypassing the laser diode; and directing the first current to the laser diode via the output node by deactivating the bypass circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention can be better understood with reference to the following description and drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:

(2) FIG. 1A is a circuit diagram of a laser diode and an electronic switch for switching the laser diode and FIG. 1B is a schematic drawing of a corresponding chip package.

(3) FIG. 2 illustrates an electric equivalent circuit of the laser diode package including parasitic inductances.

(4) FIG. 3 is a circuit diagram illustrating a first example of a driver circuit for driving a laser diode.

(5) FIG. 4 is a graph of timing diagrams (diagrams 4a, 4b, and 4c) illustrating the function of the circuit of FIG. 3.

(6) FIG. 5 is a circuit diagram illustrating a second example of a driver circuit for driving a laser diode.

(7) FIG. 6 includes timing diagrams illustrating the function of the circuit of FIG. 5.

(8) FIG. 7 is a circuit diagram illustrating a third example of a driver circuit for driving a laser diode.

(9) FIG. 8 includes timing diagrams illustrating the function of the circuit of FIG. 7.

(10) FIG. 9 is a circuit diagram illustrating a fourth example of a driver circuit for driving a laser diode.

(11) FIG. 10 is a flow chart illustrating one exemplary method for driving a laser diode.

DETAILED DESCRIPTION

(12) FIGS. 1A and 1B illustrate a laser diode and a portion of a driver circuit used to drive the laser diode. FIG. 1A is a circuit diagram of a laser diode D.sub.L and an electronic switch T.sub.HS for switching the laser diode D.sub.L on and off. Accordingly, a series circuit of laser diode DL and electronic switch T.sub.HS is coupled between ground terminal GND and supply terminal, at which a supply voltage V.sub.S is applied. At least one capacitor (in the present example a parallel circuit of capacitors C.sub.1 and C.sub.2) is connected in parallel to the series circuit of laser diode DL and electronic switch T.sub.HS in order to buffer the supply voltage V.sub.S and provide load current to the laser diode D.sub.L. The electronic switch T.sub.HS may be a MOSFET or any other suitable transistor type (e.g. BJT). The control (gate or base) terminal of the electronic switch T.sub.HS is labelled ON in the present example. Generally the buffer capacitance provided by capacitors C.sub.1 and C.sub.2 is needed to allow fast transients of the load current.

(13) FIG. 1B is a schematic drawing of a laser diode module 1 with a chip package 10 including the circuit of FIG. 1A. Accordingly, the chip package includes a first semiconductor die including the electronic switch T.sub.HS, a second semiconductor die including the laser diode D.sub.L, and at least a third semiconductor die providing the buffer capacitance. Corresponding to diagram (a) of FIG. 1, to separate capacitors are used in the present example. A lead frame 11 provides three pins corresponding to the supply terminal (voltage V.sub.S), the ground terminal GND and the control terminal ON, wherein the middle terminal is the supply terminal. The semiconductor dies including the buffer capacitors C.sub.1 and C.sub.2 are directly (i.e. without using a bond wire) bonded (e.g. soldered) to the lead frame 11 and provide a buffer capacitance between the pins representing ground and supply terminal. The bottom metallization of the semiconductor die including the MOSFET T.sub.HS represents the drain electrode of the MOSFET and is directly bonded to the pin representing the supply terminal. The gate electrode in the top metallization layer of MOSFET T.sub.HS is connected to the pin representing the control terminal ON via a bond wire. Similarly, the source electrode in the top metallization layer of MOSFET T.sub.HS is connected to the anode electrode on the top surface of laser diode D.sub.L via bond wires 12. The cathode electrode at the bottom surface of the laser diode D.sub.L is directly bonded to the lead frame 11.

(14) FIG. 2 illustrates a simplified electrical equivalent circuit of the laser diode module 1 of FIG. 1. Additionally, the circuit of FIG. 2 includes a gate driver circuit 41 coupled to the control electrode of the MOSFET T.sub.HS and configured to generate drive signals suitable to switch the MOSFET T.sub.HS on and off in accordance with a logic signal S.sub.ON. Apart from the gate driver 41, the circuit of FIG. 2 is substantially the same as in FIG. 1A except the inductors L.sub.1, L.sub.C and L.sub.G that represent parasitic inductances of the bond wires 12 (corresponds to inductance L.sub.1), the electric connections between the capacitors C.sub.1 and C.sub.2 and the laser diode D.sub.L (corresponds to inductance L.sub.C), and the electric connection (e.g., bond wire) between the control terminal ON and the actual control electrode of the MOSFET T.sub.HS (corresponds to inductance L.sub.G). Together, the gate driver 41 and the electronic switch T.sub.HS may be regarded as driver circuit 4 for driving the laser diode D.sub.L.

(15) In LIDAR systems the measurement range depends on the radiant power of the laser pulse. However, to limit the pulse energy (to protect the eyes of persons in the environment of the LIDAR system) the laser pulses need to be rather short. The voltage drop V.sub.LEFF across the effective parasitic inductance L.sub.EFF (L.sub.EFF=L.sub.C+L.sub.1) is given by
V.sub.LEFF=L.sub.EFF.Math.i.sub.L/t.sub.rise and V.sub.LEFF=L.sub.EFF.Math.i.sub.L/t.sub.fall
wherein i.sub.L is change of the load current (e.g. from 0 A to 40 A or from 40 A to 0 A), t.sub.rise is the respective rise time and t.sub.fall respective fall time. Assuming an effective inductance of 5 nH and a rise time of 2 ns yields a voltage drop of 100V. Accordingly, the system including the capacitors would have to be designed for a voltage of more than 110V (assuming 10V voltage drop across the laser diode and the MOSFET) in order to achieve the desired peak current within the desired rise time. It is noted, that a rise time of 2 ns may be too long for some applications. With the integration approach as illustrated in FIG. 1B, the inductance L.sub.EFF may be significantly reduced (e.g. below 2 nH or even below 1 nH). The remaining inductance is predominantly caused by the bond wires 12 used to connect the MOSFET TL and the laser diode D.sub.L. For example, the voltage drop V.sub.LEFF is still 80V when reducing the inductance L.sub.EFF to 1 nH when the load current is to be ramped up to 40 A within a rise time of 0.5 ns.

(16) One insight from the above analysis is that relatively high voltages (as compared to the forward voltage of the laser diode) are needed to generate the fast current transients (steep current ramps with very short rise or fall times) of the load current passing through the laser diode. Higher voltages entail an increased complexity and costs of the driver circuit. For example, e.g. transistors and buffer capacitors with comparably breakdown voltage are needed; charge-pumps may be needed for charging the buffer capacitors to the desired voltage. The driver circuits described herein are designed to generate steep current ramps for driving the laser diode with a comparably low supply voltage.

(17) FIG. 3 is a circuit diagram illustrating a first example of a driver circuit 4 for driving a laser diode D.sub.L. As in the example of FIG. 2, the parasitic inductances, which are relevant for the generation of the current ramps for the laser diode D.sub.L, are shown in FIG. 3. Accordingly, the driver circuit includes a transistor half-bridge composed of a high-side transistor T.sub.HS and a low side transistor T.sub.LS. These transistors T.sub.HS and T.sub.LS are coupled in series between a supply node SUP, at which supply voltage V.sub.S is applied, and a ground node GND, which is at reference potential V.sub.GND (e.g. 0V). The circuit node that forms the middle tap of the transistor half-bridge is denoted as OUT. The electrical lines connecting the circuit node OUT and the transistors T.sub.HS and T.sub.LS are represented by the inductors L.sub.1 and L.sub.2. As mentioned bond wires or any other electric lines contacting the transistors' electrodes may give rise to significant inductances as discussed above. As can be seen in FIG. 3, the laser diode D.sub.L is connected between the circuit node OUT and ground GND. Furthermore, one or more buffer capacitors, collectively represented by capacitor C) are connected between the supply node SUP and ground GND. As in the example in FIG. 2, an inductor L.sub.C connected in series to capacitor C represents the parasitic inductance resulting from the electrical lines contacting the capacitor(s). In the present example, the transistors T.sub.HS and T.sub.LS are n-channel MOSFETs. However, any other transistor types (e.g. bipolar junction transistors) may be used in other implementations. When using MOSFETs, the high-side transistor T.sub.HS may also be implemented as a p-channel MOS transistor.

(18) Clamping circuits CL1 and CL2 are coupled to the transistors T.sub.HS and T.sub.LS, respectively. Clamping circuit CL1 is configured to take over the inductor current i.sub.1 passing through inductor L.sub.1, when the transistor T.sub.HS is switched off. Accordingly, the gate of transistor T.sub.HS is (re-) activated for a short time period (or deactivation is delayed for a short time period) thus allowing the inductor L.sub.1 to discharge (demagnetize). Similarly, clamping circuit CL2 is configured to take over the inductor current is passing through inductor L.sub.2, when the transistor T.sub.LS is switched off. Similarly, the gate of transistor T.sub.LS is (re-) activated for a short time period (or deactivation is delayed for a short time period) thus allowing the inductor L.sub.2 to discharge (demagnetize). The mentioned re-activation (or delay of deactivation) of the transistors T.sub.HS and T.sub.LS during clamping is triggered by the drain-source voltage across the transistors T.sub.HS and T.sub.LS exceeding a clamping voltage defined by Zener diodes included in the clamping circuits. Besides current commutation, clamping circuits CL1 and CL2 may limit the voltage across the gate dielectric in order to protect the transistors T.sub.HS and, respectively, T.sub.LS. (in case of a MOS transistor).

(19) In the present example, the clamping circuit CL1 is connected between the source electrode of transistor THS and the supply node SUP, and includes a series circuit of Zener diodes DZ1A, DZ1B and normal diode D1. While commutating the inductor current i1, diode D1 is forward biased and Zener diodes DZ1A and DZ1B are operated in the Zener or avalanche breakdown and are thus reverse conducting. The Zener diode DZ1A is connected between source and gate of transistor THS to limit the gate-source voltage and protect the gate dielectric of transistor THS. Diode D1 and Zener diode DZ1B are connected between gate of transistor THS and supply node SUP. Clamping circuit CL2 includes a series circuit of Zener diode DZ2B and normal diode D2 coupled between drain and gate of transistor TLS, and a further Zener diode DZ2A coupled between gate and source of the transistor TLS. While commutating the inductor current i2, diode D2 is forward biased and Zener diode DZ2B is operated in the Zener or avalanche breakdown and is thus reverse conducting. The diodes D2 and DZ2B, which are connected between drain and gate of transistor TLS, thus can pull up the gate potential of transistor TLS (when the drain voltage rises to the mentioned clamping voltage of, e.g., 40V) to a level high enough to delay a complete switch-off of transistor for a short time-interval, during which the inductor L2 can demagnetize. Clamping circuit CL1 operates substantially in the same way.

(20) It is noted that the clamping circuits CL1 and CL2 are merely one exemplary implementation suitable for n-channel MOS transistors T.sub.HS and T.sub.LS. Other implementations of clamping circuits may be used dependent on the actual application. Diodes D.sub.1 and D.sub.2 blocks the current path through the Zener diodes D.sub.Z1B and D.sub.Z2B between gate and drain of transistors T.sub.HS and, respectively, T.sub.LS, when switching the transistors T.sub.HS and T.sub.LS on. As mentioned, the main purpose of the clamping circuits CL1 and CL2 is clamping, i.e. to take over the inductor currents when the respective transistor is switched off in order to delay the actual switch-off of the respective transistor and allow demagnetization of the respective inductor. It is noted that gate drivers (see FIG. 2, gate driver 10) have been omitted in the example of FIG. 3 in order to keep the illustrations simple. Suitable gate driver circuits are as such known and are thus not explained in more details.

(21) The function of the driver circuit of FIG. 3 is now explained with reference to the timing diagrams shown in FIG. 4. In particular, FIG. 4 includes diagram 4a, 4b and 4c. In LIDAR systems a sequence of consecutive current (and light) pulses is usually generated to obtain a sequence of corresponding range measurement values. The timing diagrams illustrates the inductor currents i.sub.1 and i.sub.2 as well as the load current i.sub.D passing through the laser diode D.sub.L (diode current) throughout one pulse period (i.e. time instant t.sub.0 to time instant t.sub.4). According to the present example, the inductors i.sub.1 and i.sub.2 are pre-charged with a magnetic flux (i.e. magnetized) before the diode current i.sub.D is actually switched on. Diagram (4a) of FIG. 4 illustrates one exemplary waveform of the inductor current i.sub.1, diagram (4b) of FIG. 4 illustrates one exemplary waveform of the inductor current i.sub.2, and diagram (4c) of FIG. 4 illustrates one exemplary waveform of the diode current i.sub.D.

(22) According to the example of FIG. 4 a pulse period may be segmented into five phases. During the first phase (before time instant t.sub.0 and between time instants t.sub.3 and t.sub.4) both transistors T.sub.HS and T.sub.LS are switched off and the inductor currents i.sub.1 and i.sub.2 as well as the diode current i.sub.D are zero (off phase). The second phase is the pre-charging phase starting at time instant t.sub.0 (or t.sub.4 in the subsequent pulse period), during which both transistors T.sub.HS and T.sub.LS are conductive (switched on). The inductances L.sub.1 and L.sub.2 (and their intrinsic series resistances) form a voltage divider and are designed such that the voltage VD at the middle tap OUT of the transistor half-bridge (which is also the middle-tap of the voltage divider) does not exceed the forward voltage of the laser diode D.sub.L (e.g. 2.2V). Therefore, the diode current i.sub.D remains substantially zero during the pre-charging phase while the inductor currents i.sub.1 and i.sub.2 (i.sub.1=i.sub.2, i.sub.D=0) ramp up as shown in diagrams (4a) and (4b) of FIG. 4. Thereby, the slope k.sub.1 of the inductor currents i.sub.1 and i.sub.2 is k.sub.1=(V.sub.1+V.sub.2)/(L.sub.1+L.sub.2), wherein V.sub.1 and V.sub.2 denote the voltage drop across the inductors L.sub.1 and L.sub.2, respectively. At time instant t.sub.1 the energies E.sub.1 and E.sub.2 stored in the inductors L.sub.1 and L.sub.2, respectively, are E.sub.1=(L.sub.1.Math.i.sub.1.sup.2)/2 and E.sub.1=(L.sub.2.Math.i.sub.2.sup.2)/2. The voltage V.sub.1+V.sub.2 across the inductors is comparably low, e.g. 2V to 5V. It is noted that the low-side transistor T.sub.LS may be regarded as a bypass circuit configured to take over, when activated, the inductor current i.sub.1 (note, i.sub.1=i.sub.2 during the pre-charging phase) provided via the high-side transistor T.sub.HS, and the diode current i.sub.D remains substantially zero during this phase.

(23) The third phase is the ramp-up phase starting at time instant t.sub.1, during which transistor T.sub.HS remains on, whereas transistor T.sub.LS is switched off at time instant t.sub.1. As the current path through transistor T.sub.LS is no longer available, the inductor current i.sub.1 is drained via the laser diode and the diode current i.sub.D ramps up very steeply within a very short rise time, while the inductor current i.sub.2 is commutated by the clamping circuit CL2 comparably fast. During this phase the voltage V.sub.2 across the inductor L.sub.2 may drop down to approximately 40V. The forth phase is referred to as on-phase and starts at time instant t.sub.2, at which inductor current i.sub.2 reaches zero and inductor L.sub.2 is completely demagnetized. The on-phase continues until time instant t.sub.2. The fifth phase is the ramp-down phase starting at time instant t.sub.2, during which transistor T.sub.LS remains off, wherein transistor T.sub.HS is also switched off at time instant t.sub.2. As the current path through transistor T.sub.HS is no longer available, the inductor current i.sub.1 is commutated by the clamping circuit CL1 comparably fast. As mentioned, Zener diode D.sub.Z1A ensured that the gate-source voltage of transistor T.sub.HS does not become too high and thus protects the gate dielectric. During this phase the voltage V.sub.1 across the inductor L.sub.1 may drop down to approximately 40V. At time instant t.sub.3 the inductor current i.sub.1 has dropped to zero amperes (i.e. inductor L.sub.1 is completely demagnetized), the ramp-down phase ends and the mentioned off phase begins until a new pre-charge phase is initiated at time t.sub.4.

(24) FIG. 5 is a circuit diagram illustrating another implementation of a driver circuit 4 for driving a laser diode D.sub.L. In the present example, the driver circuit includes four transistors which are connected to two transistor half-bridges and thus form a transistor H-bridge. Accordingly, a first half-bridge is formed by high-side transistor T.sub.1 and low-side transistor T.sub.11. Circuit node OUT1 is the middle tap of the first half-bridge. Similarly, a second half-bridge is formed by high-side transistor T.sub.22 and low-side transistor T.sub.2. Circuit node OUT2 is the middle tap of the second half-bridge. Both half-bridges are connected between supply node SUP, at which supply voltage V.sub.S is applied, and ground node GND. The laser diode D.sub.L is connected between circuit nodes OUT1 and OUT2. The inductances of the electric lines between the circuit node OUT1 and the transistors T.sub.1 and T.sub.11 are represented by inductors L.sub.1 and L.sub.11, respectively. Similarly, the inductances of the electric lines between the circuit node OUT2 and the transistors T.sub.2 and T.sub.22 are represented by inductors L.sub.2 and L.sub.22, respectively. Each transistor T.sub.1, T.sub.2, T.sub.11, T.sub.22 is coupled by a respective clamping circuit which is represented by the Zener diodes D.sub.Z1, D.sub.Z2, D.sub.Z11, D.sub.Z22, respectively. It is noted that the clamping circuit are simplified in the present example and may be more complex (e.g. like in FIG. 3) in other examples.

(25) The function of the driver circuit of FIG. 5 is explained now with reference to the timing diagram of FIG. 6. It is noted, however, that the operation principle of the present example is similar to the operation principle of the previous example shown in FIG. 3. Accordingly, the inductors L.sub.1 and L.sub.11 as well as L.sub.2 and L.sub.22 are pre-charged during a pre-charging phase, in which all transistors T.sub.1, T.sub.11, T.sub.2, T.sub.22 are conductive (switched on). This phase is illustrated in the timing diagrams of FIG. 6, between time instants t.sub.0 and t.sub.1. The first four diagrams (from the top) in FIG. 6 show exemplary waveforms of the gate signals applied to transistors T.sub.1, T.sub.11, T.sub.2, T.sub.22. The bottom diagram of FIG. 6 shows exemplary waveforms of the inductor current i.sub.1 and the diode current i.sub.D. One can see, the inductor current i.sub.1=i.sub.11 ramps up between time instant t.sub.0 (at which all transistors are switched on) and time instant t.sub.1. In a symmetric set-up the voltage at circuit nodes OUT1 and OUT2 is the same during the pre-charging phase, and thus the voltage V.sub.DL across the laser diode D.sub.L is zero; the inductor currents are identical, i.e. i.sub.1=i.sub.2=i.sub.11=i.sub.22. As in the previous example of FIG. 3, transistors T.sub.11 (and also transistor T.sub.22) can be regarded as bypass circuit configured to provide, when activated during the pre-charging phase, a current path for the inductor currents in order to bypass the laser diode D.sub.L. When deactivated (at the beginning of the subsequent ramp-up phase) this bypass is closed and the current is forced to pass the laser diode.

(26) At time instant t.sub.1 the ramp-up phase is initiated by triggering a switch-off of transistors T.sub.11 and T.sub.22. As a result, the inductor currents i.sub.1 and i.sub.2 are taken over by the laser diode D.sub.L and, thus, the diode current i.sub.D ramps up within a very short rise time t.sub.rise=t.sub.2t.sub.1, while the inductor currents i.sub.11 and i.sub.22 are taken over by the Zener diodes D.sub.Z11 and D.sub.Z22 (clamping circuits CL11 and CL22). In addition to the example of FIG. 3, the transistors T.sub.1 and T.sub.2 remain on between time instants t.sub.2 and t.sub.2, i.e. during the on phase before, at time instant t.sub.2, a switch-off of transistors T.sub.1 and T.sub.2 is triggered at the beginning of the ramp-down phase. During the ramp-down phase (between time instants t.sub.2 and t.sub.3) the inductor currents i.sub.1 and i.sub.2 are taken over by the Zener diodes D.sub.Z1 and D.sub.Z2 (clamping circuits CL1 and CL2) and the current falls down to zero (see FIG. 6, time instant t.sub.3). The subsequent phase is the off phase that lasts until a new pre-charge phase is triggered.

(27) FIG. 7 is a circuit diagram illustrating another implementation of a driver circuit 4 for driving a laser diode D.sub.L. The example of FIG. 7 is a modification of the previous example of FIG. 3 with an additional safety feature. As discussed above, the maximum radiant power of the laser diode is rather high (up to e.g. 40 W and more) in order to achieve a significant measurement range in LIDAR systems. However, the duration of the pulses (pulse width) must be sufficiently short in order to limit the pulse energy (radiant power times pulse width) to values that are harmless for the human eye (for a given pulse repetition frequency). When using a driver circuit as illustrated in FIG. 3 a dangerous situation may occur when the high-side switch T.sub.HS fails to switch-off the diode current i.sub.D (for whatever reason). In such a situation the laser diode would be operated as a continuous wave (CW) laser with a radiant power of several watts (which would correspond to a class 3B or class 4 laser).

(28) The example of FIG. 7 is essentially the same as the example of FIG. 3 with an additional capacitor C.sub.0 inserted between circuit node OUT (middle tap of the half-bridge formed by transistors T.sub.HS and T.sub.LS) and the laser diode D.sub.L. The parasitic inductance caused by the electric line between the high-side transistor T# and the circuit node OUT is represented by inductor L.sub.1. The parasitic inductance caused by the electric line between the circuit node OUT and the capacitor C.sub.0 is represented by inductor L.sub.2. Capacitor C.sub.0 decouples the high-side transistor T.sub.HS (und thus the supply node providing supply voltage V.sub.S) from the laser diode for DC currents. Thus, even if the high-side transistor would cause a short-circuit between the circuit node OUT and the supply node (voltage V.sub.S) a CW operation of the laser diode D.sub.L is prevented by capacitor C.sub.0, which blocks DC current from the laser diode D.sub.L. To safely switch-off the laser diode D.sub.L a further low-side switch T.sub.LS may be coupled in parallel to the laser diode D.sub.L. The parasitic inductance caused by the electric line between the laser diode D.sub.L and transistor T.sub.LS is represented by inductor L.sub.3, which may have a comparably low inductance.

(29) The function of the driver circuit of FIG. 7 is explained now with reference to the timing diagrams of FIG. 8. Accordingly, in a first phase (pre-charging phase) between time instants to and t.sub.1 the high-side transistor T.sub.HS and the additional low-side transistor T.sub.LS are conductive, while low-side transistor T.sub.LS is off. Thus, the inductor current i.sub.1 passing through inductors L.sub.1, L.sub.2, and L.sub.3 as well as capacitor C.sub.0 ramps up as in the example of FIG. 3. The energy E.sub.123 stored in inductance L.sub.1+L.sub.2+L.sub.3 is E.sub.123=((L.sub.1+L.sub.2+L.sub.3).Math.i.sub.1.sup.2)/2. During the second phase (energy transfer phase) the Energy E.sub.123 stored in the inductance is transferred to capacitor C.sub.0 resulting in a transient current passing through the capacitor C.sub.0, and this transient current is drained vie the laser diode D.sub.L as transistor T.sub.LS is switched off at time instant t.sub.1 (see second timing diagram in FIG. 8). A corresponding radiant power output is generated by the laser diode. The capacitor C.sub.0 may be discharged in a third phase starting at time instant t.sub.3, at which the both low-side transistors T.sub.LS and T.sub.LS is switched on. Transistor T.sub.LS may remain on until time instant t.sub.4, when a new pulse period is triggered. In other words, transistor T.sub.LS is activated at the end of the generated (current and corresponding light) pulse to completely discharge capacitor C.sub.0 thus ensuring that the pulse is generated with the same defined initial conditions (capacitor C.sub.0 discharged).

(30) As can be seen in the timing diagrams shown in FIGS. 4, 6, and 8, the timing of the switching time instants of the individual transistors determines the pulse width of the radiant power output generated by the laser diode. The example of FIG. 9 is the same as the previous example of FIG. 3. However, the present example additionally shows gate driver circuits 41a and 41b used to generate the gate voltages V.sub.GHS and V.sub.GLS for the transistors T.sub.LS and T.sub.LS, respectively. The gate drivers 41a and 41b are configured to generate the gate voltages V.sub.GHS and V.sub.GLS in accordance with the (binary) logic signals ON.sub.HS and ON.sub.LS, respectively. According to the present example, programmable delay circuits 42a, 42b may be coupled to the inputs of the gate drivers 41a and 41b, respectively. The delay circuits 42a, 42b are configured to delay the logic signals ON.sub.HS and ON.sub.LS by a defined (adjustable) delay time. Using the delay circuits 42a, 42b the timing of the logic signals ON.sub.HS and ON.sub.LS (and thus of the gate voltages V.sub.GHS and V.sub.GLS) can be fine-tuned. In some applications, such a fine-tuning may be necessary, for example, to compensate for variations of the parasitic inductances and may be conducted at the end of production during a production test using, e.g. automatic testing equipment. The delay may be stored in a one-time programmable (OTP) memory, an EPROM or the like. The logic signals ON.sub.HS and ON.sub.LS may be generated by a controller circuit CTRL and the generation of these signal may be triggered by an input signal IN (logic signal). It is understood that the controller circuit CTRL may be any suitable logic circuit and may be, for example, be implemented using a programmable logic circuit, a microcontroller executing software instructions or the like. It is understood that, in any example described herein, the gate voltages supplied to the high-side and low-side transistors may be generated in a similar manner as in the present example of FIG. 9.

(31) FIG. 10 is a flow chart illustrating one exemplary method for driving a laser diode. This method may be realized using any of the driver circuits described herein. First, during a pre-charging phase (FIG. 10, step 81), a current (see, e.g. FIGS. 3, 5, and 7, inductor current is directed, via a first electronic switch (see FIGS. 3 and 7, high-side transistor T.sub.HS; and FIG. 5, transistor T.sub.11), to an output node (node OUT or OUT1), to which the laser diode is coupled. Thus, a first inductance effective between the first electronic switch and the output node is magnetized. Further during the pre-charging phase (FIG. 10, step 82), the current i.sub.1 is drained via the active bypass circuit (see FIGS. 3, 5, and 7, low-side transistors T.sub.LS, T.sub.11, and T.sub.LS, respectively switched on) from the output node. Thus, the laser diode is bypassed and the diode current substantially zero while the inductors are magnetizes (pre-charged) In the subsequent ramp-up phase (FIG. 10, step 83), the current i.sub.1 is directed to the laser diode via the output node by deactivating the bypass circuit (see FIGS. 3, 5, and 7, low-side transistors T.sub.LS, T.sub.11, and T.sub.LS, respectively switched off). As the inductance effective in the current path is already magnetized, the diode current can ramp up very steeply resulting in a comparably short rise time.

(32) Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (units, assemblies, devices, circuits, systems, etc.), the terms (including a reference to a means) used to describe such components are intended to correspondunless otherwise indicatedto any component or structure, which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary implementations of the invention.

(33) In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms including, includes, having, has, with, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term comprising.

EXAMPLES

Example 1

(34) A driver circuit for driving a laser diode comprising a first electronic switch connected to an output node that is configured to be operably connected to a laser diode, the electric connection between the first electronic switch and the output node having a first inductance; and a bypass circuit coupled to the output node and configured to take over, when activated, the current supplied to the output node via the first electronic switch, thus magnetizing the first inductance.

Example 2

(35) The driver circuit of example 1, wherein the electric connection between the output node and the bypass circuit has a second inductance, which is also magnetized when the bypass circuit is active.

Example 3

(36) The driver circuit of example 1 or 2, further comprising a clamping circuit coupled to the first electronic switch configured to limit a voltage drop across the electronic switch in accordance with a clamping voltage.

Example 4

(37) The driver circuit of any of examples 1 to 3, further comprising a clamping circuit coupled to the first electronic switch; the clamping circuit being configured, during switch-off of the first electronic switch, to delay the switch-off in order to allow the first inductance to demagnetize.

Example 5

(38) The driver circuit of any of examples 1 to 4, further comprising a first driver coupled to a control electrode of the first electronic switch, the first driver being configured to generate a drive signal to switch the first electronic switch on an off in accordance with a first control signal.

Example 6

(39) The driver circuit of example 5, further comprising a first delay circuit coupled to the first driver and configured to delay the first control signal by an adjustable delay time.

Example 7

(40) The driver circuit of any of examples 1 to 6, wherein the bypass circuit includes a second electronic switch connected to the output node; the electric connection between the first electronic switch and the output node having a second inductance.

Example 8

(41) The driver circuit of example 7, wherein the bypass circuit further includes a clamping circuit coupled to the second electronic switch; the clamping circuit being configured to take over current passing through the second inductance, when the second electronic switch is switched off.

Example 9

(42) The driver circuit of example 7 or 8, further comprising a second driver coupled to a control electrode of the second electronic switch, the second driver being configured to generate a drive signal to switch the second electronic switch on an off in accordance with a second control signal.

Example 10

(43) The driver circuit of example 9, further comprising a second delay circuit coupled to the second driver and configured to delay the second control signal by an adjustable delay time.

Example 11

(44) The driver circuit of any of examples 1 to 10, further comprising a capacitor coupled between the first electronic switch and the output node, to decouple DC current passing from the first electronic switch to the output node.

Example 12

(45) The driver circuit of example 11, further comprising a third electronic switch coupled in operably parallel to the laser diode.

Example 13

(46) The driver circuit of any of examples 1 to 12, further comprising a half-bridge including a third electronic switch and a fourth electronic switch coupled between a supply node and a ground node, the middle tap of the half-bridge forming a further output node configured to be operably coupled to the laser diode, so that the laser diode is coupled between the output node and the further output node.

Example 14

(47) The driver circuit of example 13, wherein the electric connection between the third electronic switch and the further output node having a third inductance; and wherein the electric connection between the fourth electronic switch and the further output node having a fourth inductance; and

Example 15

(48) The driver circuit of example 14, further comprising a clamping circuit coupled to the third electronic switch; the clamping circuit being configured to take over current passing through the third inductance, when the third electronic switch is switched off; and a further clamping circuit coupled to the fourth electronic switch; the further clamping circuit being configured to take over current passing through the fourth inductance, when the fourth electronic switch is switched off.

Example 16

(49) A driver circuit for driving a laser diode comprising a first and a second transistor half-bridge forming a H-bridge that has a first output node and a second output node configured to operably couple a laser diode in between, each transistor half-bridge being composed of a high-side transistor and a low-side transistor; and control circuitry configured to: switch on, in a pre-charging phase, the high-side and the low-side transistors of the first and the second transistor half-bridges to magnetize any inductances coupled in series to the high-side and the low-side transistors; and switch off, in a ramp-up phase, the low-side transistor of the first transistor half-bridge and the high-side transistor of the second transistor half-bridge, thus directing current, which passes through the high-side transistor of the first transistor half-bridge and the low-side transistor of the second transistor half-bridge and through inductances coupled in series thereto, through the laser diode via the first and the second output node.

Example 17

(50) A method for driving a laser diode comprising: directing a first current, via a first electronic switch to an output node operably coupled to the laser diode thus magnetizing a first inductance effective between the first electronic switch and the output node; draining the first current, by activating a bypass circuit, from the output node thud bypassing the laser diode; and directing the first current to the laser diode via the output node by deactivating the bypass circuit.