High dynamic range CTIA pixel

Abstract

A HDR CTIA pixel which provides automatic gain selection, and spatial and temporal coherence. The pixel comprises an input node for connection to a photocurrent, and an output node. The pixel includes a CTIA which comprises a high gain integration capacitor and a first reset switch connected between the input and output nodes, a low gain integration capacitor connected between the input node and a first node, a second reset switch connected between the first node and the output node, and a first FET connected across the second reset switch. In operation, the first FET is off during the reset phase, and is conditionally turned on during or after the integration phase. The CTIA also includes an amplifier having an inverting input connected to the input node and an output connected to the output node. The pixel can be operated in static low-gain control and dynamic low-gain control modes.

Claims

1. A pixel having an associated pixel frame period comprising a reset phase followed by an integration phase, comprising: an input node for connection to the photocurrent output I.sub.ph of a photodiode; an output node, the voltage at said output node being V.sub.out; a capacitive transimpedance amplifier (CTIA) which comprises: a first integration capacitor connected between said input node and said output node; and a first reset switch connected between said input node and said output node; a second integration capacitor connected between said input node and a first node, the voltage at said first node being V.sub.lg; a second reset switch connected between said first node and said output node; and a first FET connected across said second reset switch, said first FET being off during said reset phase and conditionally turning on during or after said integration phase, said first and second reset switches being implemented as FETs of a first polarity and said first FET being implemented as a FET of a second polarity opposite of said first polarity.

2. The pixel of claim 1, wherein said CTIA comprises: an amplifier having at least an inverting input port and an output port, the inverting input port of said amplifier connected to said input node and the output port of said amplifier connected to said output node; said first integration capacitor; and said first reset switch.

3. The pixel of claim 1, wherein said pixel has an associated pixel saturation level, said pixel frame period arranged such that: said first and second reset switches are closed during said reset phase; said first and second reset switches are opened during said integration phase; said first FET is driven with a DC gate voltage V.sub.clamp such that: said first FET is off during said reset phase; and said first FET conditionally turns on during said integration phase; and V.sub.out is sampled just before the end of said integration phase.

4. The pixel of claim 3, wherein said pixel saturation level is the voltage at said output node at which the magnitude of the open-loop gain of the feedback loop of said CTIA during said integration phase becomes less than one.

5. The pixel of claim 3, wherein said first FET is an NMOS FET, V.sub.t is the NMOS threshold voltage, and 0<V<V.sub.t, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and decreases with time during said integration phase while V.sub.out>V.sub.clampV; said first FET is off during said integration phase while V.sub.out>V.sub.clampV; and said first FET is on during said integration phase while V.sub.out<V.sub.clampV; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

6. The pixel of claim 5, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a PMOS threshold voltage below the supply voltage Vdd.

7. The pixel of claim 5, wherein said first FET is on during said integration phase and V.sub.out is constant with time and is independent of the value of said first and second integration capacitors and decreases logarithmically with I.sub.ph while V.sub.out<V.sub.lg V.sub.out decreases with time and is proportional to I.sub.ph and inversely proportional to the sum of said first and second integration capacitors while V.sub.out=V.sub.lg and V.sub.out is higher than said pixel saturation level.

8. The pixel of claim 3, wherein said first FET is a PMOS FET, V.sub.t is the PMOS threshold voltage, and 0<V<|V.sub.t|, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and increases with time during said integration phase while V.sub.out<V.sub.clamp+V; said first FET is off during said integration phase while V.sub.out<V.sub.clamp+V; and said first FET is on during said integration phase while V.sub.out>V.sub.clamp+V; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

9. The pixel of claim 8, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a NMOS threshold voltage above ground.

10. The pixel of claim 8, wherein said first FET is on during said integration phase and V.sub.out is constant with time and is independent of the value of said first and second integration capacitors and increases logarithmically with I.sub.ph while V.sub.out>V.sub.lg V.sub.out increases with time and is proportional to I.sub.ph and inversely proportional to the sum of said first and second integration capacitors while V.sub.out=V.sub.lg and V.sub.out is lower than said pixel saturation level.

11. The pixel of claim 1, wherein said pixel has an associated pixel saturation level, said pixel frame period further comprising a charge redistribution phase following said integration phase, said pixel frame period arranged such that: said first and second reset switches are closed during said reset phase; said first and second reset switches are opened during said integration phase; said second reset switch is closed during said charge redistribution phase; said first FET is driven with a gate voltage V.sub.clamp during said reset and integration phases such that: said first FET is off during said reset phase; and said first FET conditionally turns on during said integration phase; and said first FET is driven with a full-rail gate voltage during said charge redistribution phase such that said first FET turns on in strong inversion and acts as a switch that is closed, thereby forcing V.sub.lg and V.sub.out to become equal; V.sub.out is sampled a first time just before the end of the integration phase, this sampling constituting the high-gain CTIA output; and V.sub.out is sampled a second time just before the end of the charge redistribution phase, this sampling constituting the low-gain CTIA output.

12. The pixel of claim 11, wherein said pixel saturation level is the voltage at said output node at which the magnitude of the open-loop gain of the feedback loop of said CTIA during said integration or charge redistribution phases becomes less than one.

13. The pixel of claim 11, wherein said first FET is an NMOS FET, V.sub.t is the NMOS threshold voltage, and 0<V<V.sub.t, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and V.sub.out decreases with time during said integration phase while V.sub.out>V.sub.clampV; said first FET is off during said integration phase while V.sub.out>V.sub.clampV; said first FET is on during said integration phase while V.sub.out<V.sub.clampV; and the gate voltage applied to said first FET during said charge redistribution phase is equal to the supply voltage Vdd; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

14. The pixel of claim 13, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a PMOS threshold voltage below the supply voltage Vdd.

15. The pixel of claim 11, wherein said first FET is a PMOS FET, V.sub.t is the PMOS threshold voltage, and 0<V<|V.sub.t|, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and V.sub.out increases with time during said integration phase while V.sub.out<V.sub.clamp+V; said first FET is off during said integration phase while V.sub.out<V.sub.clamp+V; said first FET is on during said integration phase while V.sub.out>V.sub.clamp+V; and the gate voltage applied to said first FET during said charge redistribution phase is equal to ground; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

16. The pixel of claim 15, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a NMOS threshold voltage above ground.

17. A pixel having an associated pixel frame period comprising a reset phase followed by an integration phase, comprising: an input node for connection to the photocurrent output I.sub.ph of a photodiode; an output node, the voltage at said output node being V.sub.out; a capacitive transimpedance amplifier (CTIA), comprising: an amplifier having at least an inverting input port and an output port, the inverting input port of said amplifier connected to said input node and the output port of said amplifier connected to said output node; a first integration capacitor connected between said input node and said output node; and a first reset switch connected between said input node and said output node; a second integration capacitor connected between said input node and a first node, the voltage at said first node being V.sub.lg; a second reset switch connected between said first node and said output node; and a first FET connected across said second reset switch and driven with a DC voltage V.sub.clamp; wherein said pixel has an associated pixel saturation level, said pixel frame period arranged such that: said first and second reset switches are closed during said reset phase; said first and second reset switches are opened during said integration phase; said first FET is driven with a DC gate voltage V.sub.clamp such that: said first FET is off during said reset phase; and said first FET conditionally turns on during said integration phase; and V.sub.out is sampled just before the end of said integration phase.

18. The pixel of claim 17, wherein said pixel saturation level is the voltage at said output node at which the magnitude of the open-loop gain of the feedback loop of said CTIA during said integration phase becomes less than one.

19. The pixel of claim 17, wherein said first FET is an NMOS FET, V.sub.t is the NMOS threshold voltage, and 0<V<V.sub.t, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and decreases with time during said integration phase while V.sub.out>V.sub.clampV; said first FET is off during said integration phase while V.sub.out>V.sub.clampV; and said first FET is on during said integration phase while V.sub.out<V.sub.clampV; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

20. The pixel of claim 19, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a PMOS threshold voltage below the supply voltage Vdd.

21. The pixel of claim 17, wherein said first FET is a PMOS FET, V.sub.t is the PMOS threshold voltage, and 0<V<|V.sub.t|, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and increases with time during said integration phase while V.sub.out<V.sub.clamp+V; said first FET is off during said integration phase while V.sub.out<V.sub.clamp+V; and said first FET is on during said integration phase while V.sub.out>V.sub.clamp+V; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

22. The pixel of claim 21, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a NMOS threshold voltage above ground.

23. The pixel of claim 19, wherein V.sub.out at the end of integration is given by: $V_{\mathrm{out}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}}$ when I.sub.ph is less than a first value; $V_{\mathrm{out}}=V_{\mathrm{clamp}}-V=V_{\mathrm{clamp}}-\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0}$ when I.sub.ph is between said first value and a second value; and $V_{\mathrm{out}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}+C_{\lg }}$ when I.sub.ph is greater than said second value and V.sub.out is higher than said pixel saturation level where k is Boltzmann's constant, T is absolute temperature, q is the charge of the electron, n is a non-ideality factor, I.sub.0 is current proportional to W/L of said first FET, C.sub.hg is the capacitance of said first integration capacitor, C.sub.lg is the capacitance of said second integration capacitor, and T.sub.int is the duration of said integration phase.

24. The pixel of claim 21, wherein V.sub.out at the end of integration is given by: $V_{\mathrm{out}}=V_{\mathrm{rst}}+\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}}$ when I.sub.ph is less than a first value; $V_{\mathrm{out}}=V_{\mathrm{clamp}}+V=V_{\mathrm{clamp}}+\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0}$ when I.sub.ph is between said first value and a second value; and $V_{\mathrm{out}}=V_{\mathrm{rst}}+\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}+C_{\lg }}$ when I.sub.ph is greater than said second value and V.sub.out is lower than said pixel saturation level where k is Boltzmann's constant, T is absolute temperature, q is the charge of the electron, n is a non-ideality factor, I.sub.0 is current proportional to W/L of said first FET, C.sub.hg is the capacitance of said first integration capacitor, C.sub.lg is the capacitance of said second integration capacitor, and T.sub.int is the duration of said integration phase.

25. A pixel having an associated pixel frame period comprising a reset phase followed by an integration phase and a charge redistribution phase, comprising: an input node for connection to the photocurrent output I.sub.ph of a photodiode; an output node, the voltage at said output node being V.sub.out; a capacitive transimpedance amplifier (CTIA), comprising: an amplifier having at least an inverting input port and an output port, the inverting input port of said amplifier connected to said input node and the output port of said amplifier connected to said output node; a first integration capacitor connected between said input node and said output node; and a first reset switch connected between said input node and said output node; a second integration capacitor connected between said input node and a first node, the voltage at said first node being V.sub.lg; a second reset switch connected between said first node and said output node; and a first FET connected across said second reset switch and driven with a drive voltage V.sub.en_lg; wherein said pixel has an associated pixel saturation level, said pixel frame period arranged such that: said first and second reset switches are closed during said reset phase; said first and second reset switches are opened during said integration phase; said second reset switch is closed during said charge redistribution phase; said first FET is driven with a gate voltage V.sub.clamp during said reset and integration phases such that: said first FET is off during said reset phase; and said first FET conditionally turns on during said integration phase; and said first FET is driven with a full-rail gate voltage during said charge redistribution phase such that said first FET turns on in strong inversion and acts as a switch that is closed, thereby forcing V.sub.lg and V.sub.out to become equal; V.sub.out is sampled a first time just before the end of the integration phase, this sampling constituting the high-gain CTIA output; and V.sub.out is sampled a second time just before the end of the charge redistribution phase, this sampling constituting the low-gain CTIA output.

26. The pixel of claim 25, wherein said pixel saturation level is the voltage at said output node at which the magnitude of the open-loop gain of the feedback loop of said CTIA during said integration phase becomes less than one.

27. The pixel of claim 25, wherein said first FET is an NMOS FET, V.sub.t is the NMOS threshold voltage, and 0<V<V.sub.t, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and decreases with time during said integration phase while V.sub.out>V.sub.clampV; said first FET is off during said integration phase while V.sub.out>V.sub.clampV; and said first FET is on during said integration phase while V.sub.out<V.sub.clampV; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

28. The pixel of claim 27, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a PMOS threshold voltage below the supply voltage Vdd.

29. The pixel of claim 25, wherein said first FET is a PMOS FET, V.sub.t is the PMOS threshold voltage, and 0<V<|V.sub.t|, said pixel frame period further arranged such that: V.sub.out is reset to a predetermined voltage V.sub.rst during said reset phase and increases with time during said integration phase while V.sub.out<V.sub.clamp+V; said first FET is off during said integration phase while V.sub.out<V.sub.clamp+V; and said first FET is on during said integration phase while V.sub.out>V.sub.clamp+V; wherein V is equal to the gate-to-source voltage of said first FET when operating in weak inversion.

30. The pixel of claim 29, wherein, when said CTIA is differential, said predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of said CTIA amplifier, and when said CTIA is single-ended, said predetermined voltage is approximately a NMOS threshold voltage above ground.

31. The pixel of claim 27, wherein said high-gain CTIA output is given by: $V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}}$ when I.sub.ph is less than a first value $V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{clamp}}-V=V_{\mathrm{clamp}}-\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0}$ when I.sub.ph is greater than said first value; and said low-gain CTIA output is given by: $V_{\mathrm{out},\lg }=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}\left(t_{\mathrm{int}}+t\right)}{C_{\mathrm{hg}}+C_{\lg }}$ when V.sub.out,lg is higher than said pixel saturation level; where k is Boltzmann's constant, T is absolute temperature, q is the charge of the electron, n is a non-ideality factor, I.sub.0 is current proportional to W/L of said first FET, C.sub.hg is the capacitance of said first integration capacitor, C.sub.lg is the capacitance of said second integration capacitor, T.sub.int is the duration of said integration phase, and t is the duration of said redistribution phase.

32. The pixel of claim 29, wherein said high-gain CTIA output is given by: $V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{rst}}+\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}}$ when I.sub.ph is less than a first value $V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{clamp}}+V=V_{\mathrm{clamp}}+\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0}$ when I.sub.ph is greater than said first value; and said low-gain CTIA output is given by: $V_{\mathrm{out},\lg }=V_{\mathrm{rst}}+\frac{I_{\mathrm{ph}}\left(t_{\mathrm{int}}+t\right)}{C_{\mathrm{hg}}+C_{\lg }}$ when V.sub.out,lg is lower than said pixel saturation level where k is Boltzmann's constant, T is absolute temperature, q is the charge of the electron, n is a non-ideality factor, I.sub.0 is current proportional to W/L of said first FET, C.sub.hg is the capacitance of said first integration capacitor, C.sub.lg is the capacitance of said second integration capacitor, T.sub.int is the duration of said integration phase, and t is the duration of said redistribution phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1a is a schematic diagram of one possible embodiment of a HDR CTIA pixel as described herein.

(2) FIG. 1b is a timing diagram which illustrates the operation of the HDR CTIA pixel of FIG. 1a.

(3) FIG. 2 is a plot of the CTIA output voltage at the end of integration vs. photocurrent which further illustrates the operation of the HDR CTIA pixel of FIG. 1a.

(4) FIG. 3a is a schematic diagram of another possible embodiment of a HDR CTIA pixel as described herein.

(5) FIG. 3b is a timing diagram which illustrates the operation of the HDR CTIA pixel of FIG. 3a.

(6) FIG. 4 is a plot of the HG and LG CTIA output voltages vs. photocurrent which further illustrates the operation of the HDR CTIA pixel of FIG. 3a.

(7) FIG. 5a is a schematic diagram which illustrates coupling a HDR CTIA pixel of FIG. 1a with additional circuitry to provide global shutter, correlated double sampling (CDS), and integrate-while-read (IWR) functionality.

(8) FIG. 5b is a timing diagram which illustrates the operation of the circuitry shown in FIG. 5a.

(9) FIG. 6a is a schematic diagram which illustrates coupling a HDR CTIA pixel of FIG. 3a with additional circuitry to provide global shutter, correlated double sampling (CDS), and integrate-while-read (IWR) functionality.

(10) FIG. 6b is a timing diagram which illustrates the operation of the circuitry shown in FIG. 6a.

DETAILED DESCRIPTION OF THE INVENTION

(11) One possible embodiment of the present HDR CTIA pixel is shown in FIG. 1a. The pixel has an associated pixel frame period, comprising a reset phase followed by an integration phase. The pixel 10 comprises an input node 12 for connection to the photocurrent output I.sub.ph of a photodiode 14, and an output node 16, the voltage at the output node being V.sub.out The pixel also includes a CTIA which comprises a first integration capacitor C.sub.hg connected between input node 12 and output node 16, and a first reset switch 18 connected across C.sub.hg. A second integration capacitor C.sub.lg is connected between input node 12 and a first node 20, the voltage at first node 20 being V.sub.lg, and a second reset switch 22 is preferably connected between first node 20 and output node 16. Reset switches 18 and 22 are shown implemented with PMOS FETs M.sub.rst and M.sub.lgp, respectively, though other device types could also be used. The CTIA preferably also comprises an amplifier 24 having at least an inverting input port and an output port, the inverting input port of the amplifier connected to input node 12 and the output port connected to output node 16. Amplifier 24 is a differential amplifier in the exemplary embodiment shown in FIG. 1a, though a single-ended amplifier could also be used.

(12) The present pixel also includes a first FET M.sub.lgn connected across second reset switch 22. In operation, first FET M.sub.lgn is off during the reset phase, and conditionally turns on during or after the integration phase. First and second reset switches 18, 22 are preferably implemented as FETs of a first polarity, and first FET M.sub.lgn is preferably implemented as a FET of a second polarity opposite that of the first polarity. For example, as shown in FIG. 1a, first and second reset switches 18, 22 are implemented as PMOS FETs, and FET M.sub.lgn is implemented as a NMOS FET.

(13) The circuit configuration described above can be operated in several different modes. A static low-gain control mode is illustrated in FIG. 1a, with an accompanying timing diagram shown in FIG. 1b. The pixel operation during the frame period 30 proceeds as follows: first and second reset switches 18, 22 are closed during the reset phase 32 (control signal rstb is at a logic low), and are opened during the integration phase 34 (control signal rstb is at a logic high); first FET M.sub.lgn is driven with a DC gate voltage V.sub.clamp such that: M.sub.lgn is off during reset phase 32; and M.sub.lgn conditionally turns on during the integration phase 34; and V.sub.out is sampled just before the end of the integration phase.

(14) The following analysis assumes that I.sub.ph flows into node 12, M.sub.lgn is an NMOS FET and 0<V<V.sub.t, where V.sub.t is the NMOS threshold voltage:

(15) During the reset phase 32, M.sub.rst and M.sub.lgp are on and V.sub.out and V.sub.lg are reset to a predetermined voltage. In a region 36, M.sub.lgn is off and photocurrent I.sub.ph is integrated only on C.sub.hg. As a result, V.sub.out decreases with time with a slope I.sub.ph/C.sub.hg. When V.sub.out=V.sub.clampV, M.sub.lgn turns on in weak inversion and operates in saturation. Now V.sub.out is constant and clamped to V.sub.clampV, no current flows through C.sub.hg, and I.sub.ph is integrated entirely on C.sub.lg. Consequently, in this region 40, V.sub.lg decreases with time with a slope I.sub.ph/C.sub.lg. Then, when V.sub.lg=V.sub.out=V.sub.clampV, M.sub.lgn begins to operate in the linear region as a switch that is closed and V.sub.out is unclamped. In this region 42, I.sub.ph is integrated on both C.sub.hg and C.sub.lg and V.sub.out=V.sub.lg and decreases with time with a slope I.sub.ph/(C.sub.hg+C.sub.lg).

(16) Note that the CTIA can be single-ended or differential (as shown in FIG. 1a). If differential, the predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of CTIA amplifier 24. When the CTIA is single-ended and I.sub.ph flows into node 12, the predetermined voltage is preferably set approximately a PMOS threshold voltage below the supply voltage Vdd. When the CTIA is single-ended and I.sub.ph flows out of node 12, the predetermined voltage is preferably set approximately a NMOS threshold voltage above ground.

(17) If I.sub.ph flows out of node 12, M.sub.lgn is a PMOS FET and 0<V<|V.sub.t|, where V.sub.t is the PMOS threshold voltage, the pixel operation is similar to the one described above except that: V.sub.out is reset to a predetermined voltage during the reset phase 32 and increases with time during the integration phase 34; M.sub.lgn is off during integration phase 34 while V.sub.out<V.sub.clamp+V and M.sub.lgn is on during integration phase 34 while V.sub.out>V.sub.clamp+V.

(18) A plot of the sampled value of V.sub.out at the end of integration phase 34 versus I.sub.ph for the static low-gain control mode is shown in FIG. 2. In this plot it is assumed that I.sub.ph flows into node 12 and M.sub.lgn is an NMOS FET. There are three distinct regions, with the behavior of V.sub.out depending on the magnitude of I.sub.ph In HG linear region 50, V.sub.out decreases linearly with photocurrent I.sub.ph and is inversely proportional to C.sub.hg:

(19) $V_{\mathrm{out}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}},$
where t.sub.int is the integration time.

(20) V.sub.out is in logarithmic region 52 when I.sub.ph is greater than

(21) $I_{\mathrm{ph},1}=\frac{C_{\mathrm{hg}}{V}_{\mathrm{out}}}{t_{\mathrm{int}}}$
but less than

(22) $I_{\mathrm{ph},2}=\frac{\left(C_{\mathrm{hg}}+C_{\lg }\right)V_{\mathrm{out}}}{t_{\mathrm{int}}},$
where V.sub.out=V.sub.rstV.sub.clamp+V. In logarithmic region 52 V.sub.out is essentially independent of the values of C.sub.hg and C.sub.lg, and decreases logarithmically with I.sub.ph:

(23) $V_{\mathrm{out}}=V_{\mathrm{clamp}}-V=V_{\mathrm{clamp}}-\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0},$
where k is Boltzmann's constant, T is absolute temperature, q is the charge of the electron, n is a non-ideality factor, and I.sub.0 is current proportional to W/L of M.sub.lgn.

(24) When I.sub.ph is greater than I.sub.ph,2, V.sub.out is in LG linear region 54, in which V.sub.out decreases linearly with photocurrent and is inversely proportional to the sum of C.sub.hg and C.sub.lg:

(25) $V_{\mathrm{out}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}+C_{\lg }}$
As I.sub.ph increases further, V.sub.out (I.sub.ph) approaches zero and the CTIA pixel saturates. This occurs for approximately 400 pA in FIG. 2.

(26) For reference, the following parameters were used in creating the plot shown in FIG. 2:

(27) C.sub.hg=16 fF

(28) C.sub.lg=64 fF

(29) V.sub.clamp=0.9 V

(30) t.sub.rst=30 s

(31) t.sub.frame=500 s

(32) t.sub.int=470 s

(33) If I.sub.ph flows out of node 12 and M.sub.lgn is a PMOS FET, the behavior of V.sub.out as a function of photocurrent I.sub.ph and the associated equations are similar, except that V.sub.out increases with I.sub.ph during first linear region 50, logarithmic region 52 and second linear region 54.

(34) Another possible operating mode, referred to herein as dynamic low-gain control, is illustrated in FIG. 3a, with an accompanying timing diagram shown in FIG. 3b. The pixel 60 has the same circuit elements as did pixel 10. However, rather than first FET M.sub.lgn being driven with a constant voltage V.sub.clamp, it is instead controlled with a signal en_lg which toggles between V.sub.clamp and a full-rail voltage (Vdd if M.sub.lgn is an NMOS FET) as shown in FIG. 3b. In addition, second reset switch 22 (PMOS FET M.sub.lgp) is controlled with a control signal enb_lg, rather than reset signal rstb.

(35) Pixel frame period 62 further comprises a charge redistribution phase 64 following the reset phase 66 and integration phase 68. The pixel frame period 62 is arranged such that: first and second reset switches 18, 22 are closed during reset phase 66; first and second reset switches 18, 22 are opened during integration phase 68; first reset switch 18 remains open while second reset switch 22 is closed during charge redistribution phase 64 with duration t; M.sub.lgn is driven with a gate voltage V.sub.clamp during the reset and integration phases (66, 68) such that: M.sub.lgn is off during reset phase 66; and M.sub.lgn conditionally turns on during integration phase 68; and M.sub.lgn is driven with a full-rail gate voltage (Vdd if M.sub.lgn is an NMOS FET) during charge redistribution phase 64 such that M.sub.lgn turns on in strong inversion and operates in the linear region as a switch that is closed, thereby forcing V.sub.lg and V.sub.out to become equal; V.sub.out is sampled a first time just before the end of integration phase 68, this sampling constituting the high-gain (HG) CTIA output; and V.sub.out is sampled a second time just before the end of charge redistribution phase 64, this sampling constituting the low-gain (LG) CTIA output.

(36) The pixel operation during the reset and integration phases (66, 68) in dynamic low-gain control mode is essentially identical to the one in static low-gain control mode. The following analysis assumes that I.sub.ph flows into node 12, M.sub.lgn is an NMOS FET and 0<V<V.sub.t, where V.sub.t is the NMOS threshold voltage. During reset phase 66, M.sub.rst and M.sub.lgp are on and V.sub.out and V.sub.lg are reset to a predetermined voltage. t the onset of integration phase 68, M.sub.lgn is off and photocurrent I.sub.ph is integrated only on C.sub.hg. As a result, V.sub.out decreases with time with a slope I.sub.ph/C.sub.hg. When V.sub.out=V.sub.clampV, M.sub.lgn turns on in weak inversion and clamps V.sub.out to V.sub.clampV. The HG CTIA output is the value of V.sub.out sampled just before the end of integration phase 68. During the charge redistribution phase 64, M.sub.lgn is driven with a full-rail gate voltage (Vdd), so that it turns on in strong inversion and operates as a switch that is closed. Consequently, V.sub.lg and V.sub.out become equal and the integrated charge on C.sub.hg and C.sub.lg is redistributed. For the duration t of the charge redistribution phase, V.sub.out=V.sub.lg and decreases with time with a slope I.sub.ph/(C.sub.hg+C.sub.lg). The value of V.sub.out just before the end of the charge redistribution phase 64 is sampled as the LG CTIA output.

(37) When the CTIA is differential (as shown in FIG. 3a), the predetermined voltage is equal to a voltage V.sub.rst applied to the non-inverting input of CTIA amplifier 24, and when the CTIA is single-ended and I.sub.ph flows into node 12, the predetermined voltage is approximately a PMOS threshold voltage below supply voltage Vdd. When the CTIA is single-ended and I.sub.ph flows out of node 12, the predetermined voltage is preferably set approximately a NMOS threshold voltage above ground.

(38) If I.sub.ph flows out of node 12, M.sub.lgn is a PMOS FET and 0<V<|V.sub.t|, where V.sub.t is the PMOS threshold voltage, the pixel operation is similar to the one described above except that: V.sub.out is reset to a predetermined voltage during reset phase 66 and V.sub.out increases with time during integration phase 68; M.sub.lgn is off during integration phase 68 while V.sub.out<V.sub.clamp+V; M.sub.lgn is on during integration phase 68 while V.sub.out>V.sub.clamp+V; and the gate voltage applied to M.sub.lgn during charge redistribution phase 64 is equal to ground.

(39) A plot of V.sub.out,hg (the HG CTIA output) and V.sub.out,lg (the LG CTIA output) versus I.sub.ph in dynamic low-gain control mode is shown in FIG. 4. V.sub.out,hg is given by:

(40) $V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}{t}_{\mathrm{int}}}{C_{\mathrm{hg}}}\mathrm{for}{I}_{\mathrm{ph}}<I_{\mathrm{ph}1}\mathrm{and}$$V_{\mathrm{out},\mathrm{hg}}=V_{\mathrm{clamp}}-V=V_{\mathrm{clamp}}-\frac{\mathrm{nkT}}{q}\ln \frac{I_{\mathrm{ph}}}{I_0}\mathrm{for}{I}_{\mathrm{ph}}{I}_{\mathrm{ph}1}.$
Here

(41) $I_{\mathrm{ph},1}=\frac{C_{\mathrm{hg}}{V}_{\mathrm{out}}}{t_{\mathrm{int}}},$
where V.sub.out=V.sub.rstV.sub.clamp+V. Signal V.sub.out,lg is given by:

(42) $V_{\mathrm{out},\lg }=V_{\mathrm{rst}}-\frac{I_{\mathrm{ph}}\left(t_{\mathrm{int}}+t\right)}{C_{\mathrm{hg}}+C_{\lg }}.$
As I.sub.ph increases further, V.sub.out,lg approaches ground and the CTIA pixel saturates. This occurs for approximately 400 pA in FIG. 4. It should be noted that when using dynamic low-gain control it is advantageous to set V.sub.clampV close to the CTIA saturation level (ground in FIG. 4) in order to maximize the HG CTIA output swing. While V.sub.out,hg decreases logarithmically with I.sub.ph for I.sub.phI.sub.ph1, this region is normally excluded in favor of V.sub.out,lg when constructing the HDR signal. It should also be noted that while the V.sub.out,lg exposure time (t.sub.int+t) is slightly longer than the V.sub.out,hg exposure time (t.sub.int), this difference is inconsequential as long as t<<t.sub.int and therefore the HDR signal constructed from V.sub.out,hg and V.sub.out,lg is essentially temporally coherent.

(43) For reference, the following parameters were used in creating the plot shown in FIG. 4:

(44) C.sub.hg=16 fF

(45) C.sub.lg=64 fF

(46) V.sub.clamp=0.5 V

(47) t.sub.rst=30 s

(48) t=30 s

(49) t.sub.frame=500 s

(50) t.sub.int=440 s

(51) The pixels described herein would typically be coupled to additional circuitry to provide a desired functionality. One possible example is shown in FIG. 5a, with a corresponding timing diagram shown in FIG. 5b. Here, a HDR CTIA pixel 70 as described herein is used in static low-gain control mode, and coupled to additional circuitry 72 to provide global shutter, correlated double sampling (CDS), and integrate-while-read (IWR) functionality. Similarly, in FIGS. 6a and 6b, a HDR CTIA pixel 80 as described herein is used in dynamic low-gain control mode, and coupled to additional circuitry 82 to provide global shutter, CDS and IWR functionality. While FIGS. 5b and 6b illustrate the readout of three pixel rows (by providing consecutive row select signals rowsel<0>, rowsel<1>, and rowsel<2>), an arbitrary number n rows can be read out by providing consecutive row select signals rowsel<0>, rowsel<1>, . . . rowsel<n1>. The last signal rowsel<n1> must be issued before the arrival of the respective sampling pulse (sample in FIG. 5a, sample1 in FIG. 6a).

(52) The relative advantages and disadvantages of static and dynamic low-gain control will be discussed next. The primary advantage of static low-gain control is that there is a single pixel output (the sampled value of V.sub.out at the end of integration) which is an HDR signal containing three different regions (as shown in FIG. 2): a HG linear region, a logarithmic region and a LG linear region. When operated with static low-gain control, the pixel has automatic gain selection; i.e. the pixel output automatically switches between these three regions as the photocurrent increases. Having a single pixel output is advantageous because it simplifies the implementation of additional pixel features such as CDS, global shutter, and IWR functionality. The disadvantage of the static low-gain control is the presence of a logarithmic region, which makes it more difficult to reconstruct a linear transfer function (pixel output vs. photocurrent). Dynamic low-gain control avoids the logarithmic region. Instead, the pixel has two linear outputs: HG and LG as shown in FIG. 4. The absence of a logarithmic region facilitates the reconstruction of a linear transfer function, which represents the main advantage of dynamic low-gain control. The disadvantage is the presence of two pixel outputs, which somewhat complicates the implementation of additional pixel features (CDS, global shutter, IWR, etc.) as can be seen by comparing the schematics in FIGS. 5a and 6a. Another disadvantage is that a pixel operated with dynamic low-gain control by itself does not have automatic gain selection: a separate circuit or block is needed to combine the HG and LG outputs from each pixel into a single HDR output. As an example, the HG output may be compared against a reference to determine whether it is saturated or not. If the HG output is not saturated then the HDR signal equals the HG output; otherwise, the HDR signal equals the LG output. Finally, for the same values of C.sub.hg, C.sub.lg and CTIA output voltage swing, a pixel using dynamic or static low-gain control will have approximately the same dynamic range.

(53) A HDR CTIA pixel as described herein selectively enables an overflow capacitor (C.sub.lg in FIGS. 1a and 3a), thereby expanding the pixel's charge capacity and dynamic range. The static low-gain control mode further provides automatic gain selection with a single-transistor implementation, which provides minimum layout penalty and no power penalty. The HDR CTIA pixel as described herein preserves spatial coherence because the HDR signal is produced by a single photodiode. It also preserves temporal coherence because the HDR signal is produced by integrating the photocurrent over a single exposure. Both spatial and temporal coherence are particularly beneficial for hyperspectral imaging.

(54) In contrast with a visible monolithic pixel, for the present pixel the photodiode can be on a separate layer and can be made of different semiconductor materials (e.g., Si, HgCdTe, InGaAs). With a suitable selection of photodiode material, the HDR CTIA pixel can work over various spectral bands of interest from UV to long-wave IR. An HDR CTIA pixel with a Si photodiode achieves higher optical fill factor and quantum efficiency (QE) than a visible monolithic pixel, especially in the near-IR spectrum. Pixel crosstalk is also lower, because the CTIA amplifier maintains the CTIA input at a virtual ground and therefore the interpixel capacitance does not matter.

(55) The pixel implementations depicted in FIGS. 1a and 3a are merely exemplary. Numerous ways in which a pixel in accordance with the present invention could be implemented are envisioned, including opposite polarity embodiments and embodiments using devices other than FETs. Similarly, the additional circuitry to which pixels per the present invention might be coupled could be implemented in myriad ways other than those shown in FIGS. 5a and 6a. The present pixel is useful in any number of possible applications, including hyperspectral imaging as mentioned above, or any application needing a HDR CTIA-type input cell.

(56) The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.