Inspection circuit, semiconductor storage element, semiconductor device, and connection inspection method

Abstract

An inspection circuit for inspecting a connection state between a semiconductor storage element including a storage section, and a semiconductor element connected to the semiconductor storage element, the inspection circuit includes: an input terminal that is input with a test signal to be sent to a first controller; an input/output terminal that is input and output with data to be written to or read from the storage section; a first inspection section that is input with an inspection signal; a second inspection section, disposed between the input terminal and the first controller, that converts the test signal to a control signal at a predetermined logic level under control of the first inspection section; and a third inspection section, disposed between the input/output terminal and a second controller, that sends the test signal to the second controller under control of the first inspection section.

Claims

1. An inspection circuit that executes an inspection of a connection state between a semiconductor storage element including a storage section that stores data, and a semiconductor element connected to the semiconductor storage element, the inspection circuit comprising: an input terminal that is input with a test signal to be sent to a first controller; an input/output terminal that is input with data to be written to the storage section and that outputs data read from the storage section; a first inspection section that is input with an inspection signal; a second inspection section, disposed between the input terminal and the first controller, that converts the test signal to a control signal at a predetermined logic level under control of the first inspection section; and a third inspection section, disposed between the input/output terminal and a second controller, that sends the test signal to the second controller under control of the first inspection section.

2. The inspection circuit of claim 1, wherein inspection of the connection state is executed by writing the test signal to the storage section, reading the test signal from the storage section, and comparing the written data with the read data.

3. The inspection circuit of claim 1, wherein inspection of the connection state is executed by inspecting whether or not a short circuit to the predetermined logic level has occurred between the input terminal and a terminal of the semiconductor element connected to the input terminal.

4. The inspection circuit of claim 1, wherein: the test signal is set to an opposite logic level to the predetermined logic level at a timing for writing to the storage section; and the second inspection section converts the test signal to the control signal at the predetermined logic level at a timing for writing to the storage section.

5. The inspection circuit of claim 1, wherein the third inspection section sends the test signal, received from the input terminal via the second inspection section and the first inspection section, to the second controller.

6. The inspection circuit of claim 1, wherein the first controller is a controller that executes a chip selection function and the control signal is a chip selection signal, or the first controller is a controller that executes a clock enable function and the control signal is a clock enable signal.

7. A semiconductor storage element comprising: a storage section; a first controller, the first controller being configured to execute a given function accompanying storage in the storage section when a control signal is at a predetermined logic level; a second controller, the second controller being configured to control writing of data to the storage section and reading of data from the storage section; and an inspection circuit that executes an inspection of a connection state between the semiconductor storage element, and a semiconductor element connected to the semiconductor storage element, the inspection circuit comprising an input terminal that is input with a test signal to be sent to the first controller, an input/output terminal that is input with the data to be written to the storage section and that outputs the data read from the storage section, a first inspection section that is input with an inspection signal, a second inspection section, disposed between the input terminal and the first controller, that converts the test signal to the control signal at the predetermined logic level under control of the first inspection section, and a third inspection section, disposed between the input/output terminal and the second controller, that sends the test signal to the second controller under control of the first inspection section.

8. A semiconductor device comprising: a semiconductor element; and a semiconductor storage element comprising a storage section, a first controller, the first controller being configured to execute a given function accompanying storage in the storage section when a control signal is at a predetermined logic level, a second controller, the second controller being configured to control writing of data to the storage section and reading of data from the storage section, and an inspection circuit that executes an inspection of a connection state between the semiconductor storage element and the semiconductor element, the inspection circuit comprising an input terminal that is input with a test signal to be sent to the first controller, an input/output terminal that is input with the data to be written to the storage section and that outputs the data read from the storage section, a first inspection section that is input with an inspection signal, a second inspection section, disposed between the input terminal and the first controller, that converts the test signal to the control signal at the predetermined logic level under control of the first inspection section, and a third inspection section, disposed between the input/output terminal and the second controller, that sends the test signal to the second controller under control of the first inspection section.

9. The semiconductor device of claim 8, wherein the semiconductor element is a microcontroller including: a first output terminal that sends the test signal to the input terminal; a second output terminal that sends the inspection signal to the first inspection section; and a data input terminal that is input with data from the input/output terminal, wherein, execution of the inspection by the inspection circuit is controlled by the inspection signal.

10. The semiconductor device of claim 8, wherein the semiconductor storage element and the semiconductor element are mounted in a microchip package.

11. A connection inspection method that uses an inspection circuit included in a semiconductor storage element, the semiconductor storage element including a storage section that stores data and a controller that executes a given function accompanying storage in the storage section in a case in which a control signal is at a predetermined logic level, the connection inspection method comprising: inputting a test signal through an input terminal that is input with a signal sent to the controller; at a timing for writing to the storage section, converting the test signal to a control signal of the predetermined logic level, and inputting the converted signal to the controller; writing, at the timing for writing to the storage section, the test signal to the storage section; reading the test signal stored in the storage section; and inspecting a connection state between an input terminal of the semiconductor storage element and a terminal corresponding to the input terminal on a semiconductor element connected to the semiconductor storage element by comparing the test signal written to the storage section to the test signal read from the storage section.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Exemplary embodiments will be described in detail based on the following figures, wherein:

(2) FIG. 1 is a block diagram illustrating a configuration of a semiconductor device according to an exemplary embodiment;

(3) FIG. 2 is a block diagram illustrating a configuration of an inspection circuit according to a first exemplary embodiment;

(4) FIG. 3 is a timing chart illustrating correct operation of an inspection circuit according to the first exemplary embodiment;

(5) FIG. 4 is a timing chart illustrating abnormal operation of an inspection circuit according to the first exemplary embodiment;

(6) FIG. 5 is a block diagram illustrating a configuration of an inspection circuit according to a second exemplary embodiment;

(7) FIG. 6 is a timing chart illustrating correct operation of an inspection circuit according to the second exemplary embodiment; and

(8) FIG. 7 is a timing chart illustrating abnormal operation of an inspection circuit according to the second exemplary embodiment.

DETAILED DESCRIPTION

(9) Detailed explanation follows regarding exemplary embodiments of the present disclosure, with reference to the drawings.

First Exemplary Embodiment

(10) Explanation follows regarding an inspection circuit, a semiconductor storage element, a semiconductor device, and a connection inspection method according to the present exemplary embodiment, with reference to FIG. 1 to FIG. 4. In the present exemplary embodiment, configuration is made so as to detect a short abnormality (short circuit) affecting a CS terminal of DRAM.

(11) As illustrated in FIG. 1, a semiconductor device 10 according to the present exemplary embodiment is configured including DRAM 12 and a controller IC 18. The DRAM 12 and the controller IC 18 are mounted in a package. The package configuration is not particularly limited, but the semiconductor device 10 according to the present exemplary embodiment employs MCP. The semiconductor device 10 includes external terminals 20 for connecting to external components and the like.

(12) The DRAM 12 is a semiconductor storage element according to the present exemplary embodiment, and is configured including an inspection circuit 14, which is an inspection circuit according to the present exemplary embodiment, and a storage section 15 that stores data therein. As illustrated in FIG. 1, the inspection circuit 14 includes a chip select (CS) terminal, a TEST terminal, a clock enable (CKE) terminal, and a DQ terminal. These terminals configure a portion of the terminals 16 used for external connections to the DRAM 12. Note that, in the present exemplary embodiment, configuration is made to detect short abnormalities (short circuit) at the CS terminal of the DRAM 12, and therefore explanation follows using the example of an inspection circuit 14 including a CS terminal, a TEST terminal, and a DQ terminal.

(13) The controller IC 18 is a semiconductor element that is primarily used to control the DRAM 12. The controller IC 18 includes a C_CS terminal, a C_TEST terminal, a C_CKE terminal, and a C_DQ terminal, which configure a portion of the terminals 22 of the controller IC 18. The C_CS terminal, the C_TEST terminal, the C_CKE terminal, and the C_DQ terminal are respectively connected to the CS terminal, the TEST terminal, the CKE terminal, and the DQ terminal of the DRAM 12, and configure output terminals that output control signals to control the CS terminal, the TEST terminal, the CKE terminal, and the DQ terminal of the DRAM 12, or configure input terminals that receive signals from the DRAM 12.

(14) Next, detailed explanation follows regarding the inspection circuit 14 according to the present exemplary embodiment, with reference to FIG. 2. As illustrated in FIG. 2, the inspection circuit 14 is configured including the CS terminal, the TEST terminal, and the DQ terminal, as well as short detection circuits 24-1, 24-2, 24-3 (these are also referred to collectively as short detection circuits 24 hereafter). Note that the CS control circuit 26 and the DQ control circuit 28 in FIG. 2 configure part of the DRAM 12.

(15) The CS terminal is a device selection signal input terminal. Input through other signal lines is enabled while this signal is being asserted. The CS control circuit 26 is a circuit that executes operations in response to a signal input to the CS terminal. The CS terminal is connected to the C_CS terminal of the controller IC 18. The controller IC 18 controls a chip selection function by sending a CS signal from the C_CS terminal to the CS terminal of the DRAM 12. Note that although the CS terminal according to the present exemplary embodiment is activated at the L level (is enabled at the L level, namely, is active low), obviously the opposite logic may also be employed.

(16) The DQ terminal is an input/output terminal for data signals. The DQ control circuit 28 writes data to memory (for example, 1-bit memory) in the DRAM 12 in response to a signal input to the DQ terminal, and reads, from the DQ terminal, data that has been written from the memory in the DRAM 12 in response to a control signal from the DQ terminal. The DQ terminal is connected to the C_DQ terminal of the controller IC 18. The controller IC 18 sends data signals from the C_DQ terminal to the DQ terminal, and also accepts data signals output from the DQ terminal through the C_DQ terminal.

(17) The TEST terminal is an input terminal for a control signal to control the inspection circuit 14. The TEST terminal is connected to the short detection circuit 24-1. The short detection circuits 24-2 and 24-3 are each connected to the short detection circuit 24-1, and are controlled via the short detection circuit 24-1. The TEST terminal is connected to the C_TEST terminal of the controller IC 18. The controller IC 18 controls the inspection circuit 14 by sending a control signal (inspection signal) used to control inspection from the C_TEST terminal to the inspection circuit 14.

(18) As illustrated in FIG. 2, bonding wires, printed board patterns, bumps (in the case of flip chip mounting), or the like are used to make connections between the C_CS terminal and the CS terminal, between the C_DQ terminal and the DQ terminal, and between the TEST terminal and the C_TEST terminal. In the present exemplary embodiment, these connections are configured by bonding wires W. The short detection circuits 24 are circuits that detect short abnormalities (short circuit) in these connections. Namely, the inspection circuit 14 according to the present exemplary embodiment is a circuit that detects short abnormalities in the connections between the DRAM 12 and the controller IC 18.

(19) As illustrated in FIG. 2, the short detection circuit 24-2 is disposed between the CS terminal and the CS control circuit 26, and controls input to the CS control circuit 26. The short detection circuit 24-3 is disposed between the DQ terminal and the DQ control circuit 28, and controls input and output of the DQ control circuit 28. The short detection circuit 24-1 is connected to the TEST terminal as well as the short detection circuit 24-2 and the short detection circuit 24-3, and controls the short detection circuits 24-2, 24-3 in response to an inspection signal input via the TEST terminal.

(20) Next, explanation follows regarding operation of the inspection circuit 14. The inspection circuit 14 has a normal mode, this being operation in a normal state, and an inspection mode, this being operation during inspection. As illustrated by the dashed arrow labeled <1>, in the normal mode, signals sent from the C_CS terminal to the CS terminal are input to the CS control circuit 26 so as to control the CS control circuit 26. Similarly, as illustrated by the dashed arrow labeled <1>, data signals sent from the C_DQ terminal to the DQ terminal are input to the DQ control circuit 28. Further, as illustrated by the dashed arrow labeled <4>, data signals read from the DRAM 12 are sent from the DQ control circuit 28 to the C_DQ terminal of the controller IC 18 via the DQ terminal. Note that the reference numbers depicted by <X> in the following explanation indicate corresponding locations in the drawings.

(21) In the inspection mode, the controller IC 18 sends a TEST signal from the C_TEST terminal to the TEST terminal of the DRAM 12 to activate (actuate) the short detection circuits 24-1, 24-2, 24-3. When this is performed, the CS terminal is isolated from the CS control circuit 26 at the short detection circuit 24-2. Namely, the CS control circuit 26 is applied with an L level signal from the short detection circuit 24-2 via the route labeled <3> in FIG. 2, placing the interior of the DRAM 12 in a WRT command state. As described above, the CS terminal according to the present exemplary embodiment is active low.

(22) At the same time, the DQ terminal is isolated from the DQ control circuit 28 at the short detection circuit 24-3, and a signal (test signal) that is input to the DQ control circuit 28 through the CS terminal, via the route labeled <2> in FIG. 2, is written to the DRAM 12. The data written to the DRAM 12 is read by the controller IC 18 through the DQ terminal via the route labeled <4> in FIG. 2. The above operation enables inspection as to whether or not a short abnormality has arisen between the C_CS terminal and the CS terminal. Namely, in the inspection mode, a signal via the route labeled by the dashed arrow <3> is an input signal for the CS control circuit 26, and a signal indicated by the dashed arrow <2> is an input (write) data signal for the DQ control circuit 28.

(23) More detailed explanation follows regarding operation of the inspection circuit 14, with reference to FIG. 3 and FIG. 4. FIG. 3 is a timing chart illustrating operation of the inspection circuit 14 in a case in which a short abnormality has not occurred between the C_CS terminal and the CS terminal. FIG. 3 illustrates commands sent from the controller IC 18 to the DRAM 12 and the waveforms at respective sections. FIG. 4 is a timing chart illustrating operation of the inspection circuit 14 in a case in which a short abnormality has occurred between the C_CS terminal and the CS terminal. FIG. 4 illustrates commands sent from the controller IC 18 to the DRAM 12 and the waveforms at respective sections.

(24) As illustrated at <1> in FIG. 3, in the present operation example, writing and reading are performed in this sequence. In a write operation, an ACT (active) command, a WRT (write) command, and a PRE (pre-charge) command are sent as commands from the controller IC 18 to the DRAM 12 in this sequence, and one bit of data is written to a memory cell in the DRAM 12. In the present exemplary embodiment, for example, memory cells are configured by one-bit cells. A TEST IN command between the ACT command and the WRT command, and a TEST OUT command between the WRT command and the PRE command configure inspection operation commands in the present exemplary embodiment. Namely, the inspection circuit 14 is controlled using the TEST IN command and the TEST OUT command. The TEST IN command is a command to activate (start operation of) the inspection circuit 14, and the TEST OUT command is a command to de-activate (stop operation of) the inspection circuit 14. In a read operation, an ACT (active) command, a RED (read) command, and a PRE (pre-charge) command are set from the controller IC 18 to the DRAM 12 in this sequence, and one bit of data is read from a one-bit cell of the DRAM 12.

(25) The waveforms of a clock signal CLK (CK) and a test signal TEST are also illustrated at <1> in FIG. 3. The test signal TEST is a signal input to the TEST terminal of the DRAM 12 from the C_TEST terminal of the controller IC 18 during the inspection operation. Setting this TEST signal to the H level causes the inspection circuit 14 to transition to the inspection mode (activate the inspection circuit 14) and causes the short detection circuits 24 to operate.

(26) Explanation follows regarding operation when an H level is input to the CS terminal of the DRAM 12 from the C_CS terminal of the controller IC 18 in cases in which a short abnormality has not occurred between the C_CS terminal and the CS terminal, with reference to <2> in FIG. 3. In this operation, an H level is written from the C_CS terminal of the controller IC 18 via the CS terminal of the DRAM 12, and this H level is read from the DRAM 12.

(27) To begin, a signal input to the CS terminal has the waveform as illustrated at <3> in FIG. 3. Namely, since the signal input to the CS terminal is active low, and the CS control circuit 26 operates when the input signal is set to L level at timings corresponding to commands. An H level is input to the CS terminal at the WRT command timing in order to write an H level to the DRAM 12. However, in order to achieve normal operation of the CS control circuit 26, as illustrated at <4> in FIG. 3, the input of the CS control circuit 26 is converted to L level by the short detection circuit 24-2 at the WRT command timing.

(28) As illustrated at <5> in FIG. 3, the signal input to the DQ control circuit 28 at the WRT command timing is H level due to an H level CS signal being input via the short detection circuits 24-2, 24-1, 24-3. Namely, an H level is written to the DRAM 12. Accordingly, in a read operation, as illustrated at <6> in FIG. 3, an H level is read via the DQ terminal, with the logic of the write data and the logic of the read data of the DRAM 12 matching each other at the H level. The controller IC 18 therefore determines the connection between the C_CS terminal and the CS terminal to be correct.

(29) Next, explanation follows regarding operation when an L level is input to the CS terminal of the DRAM 12 from the C_CS terminal of the controller IC 18 in cases in which a short abnormality has not occurred between the C_CS terminal and the CS terminal, with reference to <7> in FIG. 3. In this operation, an L level is written from the C_CS terminal of the controller IC 18 via the CS terminal of the DRAM 12, and this L level is read from the DRAM 12.

(30) To begin, a signal input to the CS terminal has the waveform as illustrated at <8> in FIG. 3. Namely, an L level is input to the CS terminal at a WRT command timing in order to write an L level to the DRAM 12. Since the CS control circuit 26 normally operates at the L level, as illustrated at <9> in FIG. 3, the short detection circuit 24-2 inputs an L level signal to the CS control circuit 26 at the WRT command timing.

(31) As illustrated at <10> in FIG. 3, the signal input to the DQ control circuit 28 at the WRT command timing is at the L level due to an L level CS signal being input via the short detection circuits 24-2, 24-1, 24-3. Namely, an L level is written to the DRAM 12. Accordingly, in a read operation, as illustrated at <11> in FIG. 3, an L level is read via the DQ terminal, the logic of the write data and the logic of the read data matches with each other at the L level. The controller IC 18 therefore determines the connection between the C_CS terminal and the CS terminal to be correct.

(32) Next, explanation follows regarding operation of the inspection circuit 14 in cases in which a short abnormality has occurred between the C_CS terminal and the CS terminal, with reference to FIG. 4. This example assumes a short abnormality to the L level, for example a short circuit to a power source VSS, has occurred between the C_CS terminal and CS terminal. The commands, the CLK (CK) signal, and the TEST signal illustrated at <1> in FIG. 4 are similar to those illustrated at <1> in FIG. 3, and so detailed explanation thereof is omitted.

(33) As illustrated at <2> in FIG. 4, in this example, at a WRT command timing, the controller IC 18 sends an H level from the C_CS terminal as an input signal (test signal) to inspect the CS terminal of the DRAM 12. However, since a short to the L level has occurred between the C_CS terminal and the CS terminal, as illustrated at <3> in FIG. 4, the CS terminal input remains at the L level. In order to achieve normal operation of the CS control circuit 26, as illustrated at <4> in FIG. 3, the short detection circuit 24-2 sends an L level to the CS control circuit 26.

(34) However, in this example, when attempting to write an H level to the 1-bit memory in the DRAM 12, since the signal input to the CS terminal remains at the L level, as illustrated at <5> in FIG. 4, the short detection circuit 24-3 sends an L level to the DQ control circuit 28. As illustrated at <6> in FIG. 4, the controller IC 18 therefore reads an L level from the DRAM 12 via the DQ terminal. Even if an H level has been written, the level read from the DRAM 12 will always be L level. Since the write data and the read data do not match, the controller IC 18 determines that a short abnormality to the L level has occurred in the connection between the C_CS terminal and the CS terminal.

(35) As described above, the inspection circuit, the semiconductor storage element, the semiconductor device, and the connection inspection method according to the present exemplary embodiment may easily detect a short abnormality (short circuit), in cases in which the short abnormality has occurred in the connection between the C_CS terminal of the controller IC 18 and the CS terminal of the DRAM 12.

Second Exemplary Embodiment

(36) Explanation follows regarding an inspection circuit, a semiconductor storage element, a semiconductor device, and a connection inspection method according to an exemplary embodiment, with reference to FIG. 5 to FIG. 7. In the present exemplary embodiment, configuration is made so as to detect a short abnormality (short circuit) affecting a CKE terminal of DRAM.

(37) As illustrated in FIG. 5, an inspection circuit 14a according to the present exemplary embodiment is configured including a CKE terminal, a TEST terminal, a DQ terminal, and short detection circuits 24-4, 24-5, 24-6 (these are also referred to collectively as short detection circuits 24 hereafter). The CKE control circuit 30 and the DQ control circuit 28 in FIG. 5 configure part of the DRAM 12. Note that as the present exemplary embodiment is configured to detect short abnormalities (short circuit) affecting the CKE terminal of the DRAM 12, the terminals of the inspection circuit 14a include the CKE terminal, the TEST terminal, and the DQ terminal.

(38) The CKE terminal is an input terminal for a clock enable signal. Input of a clock is enabled while this signal is being asserted. The CKE control circuit 30 is a circuit that executes operations in response to a signal input to the CKE terminal. The CKE terminal is connected to the C_CKE terminal of the controller IC 18. The controller IC 18 controls a clock enable function by sending a CKE signal from the C_CKE terminal to the CKE terminal of the DRAM 12. Note that, although the CKE terminal according to the present exemplary embodiment is activated at the H level (is enabled at an H level, namely, is active high), obviously the opposite logic may also be employed. The DQ terminal and the DQ control circuit 28 are both similar to those illustrated in FIG. 2, and so detailed explanation thereof is omitted.

(39) The TEST terminal is an input terminal for a control signal to control the inspection circuit 14a, and is connected to the short detection circuit 24-4. The TEST terminal is connected to the C_TEST terminal of the controller IC 18. The controller IC 18 controls the inspection circuit 14a by sending a control signal from the C_TEST terminal of the controller IC 18 to the inspection circuit 14a.

(40) In FIG. 5, bonding wires, printed board patterns, or the like are used make connections between the C_CKE terminal and the CKE terminal, between the C_DQ terminal and the DQ terminal, and between the TEST terminal and the C_TEST terminal. In the present exemplary embodiment, these connections are configured by bonding wires W. The short detection circuits 24 are circuits that detect short abnormalities (short circuit) in these connections. Namely, the inspection circuit 14a according to the present exemplary embodiment is a circuit that detects short abnormalities in the connections between the DRAM 12 and the controller IC 18.

(41) As illustrated in FIG. 5, the short detection circuit 24-5 is disposed between the CKE terminal and the CKE control circuit 30, and controls input to the CKE control circuit 30. The short detection circuit 24-6 is disposed between the DQ terminal and the DQ control circuit 28, and controls input and output of the DQ control circuit 28. The short detection circuit 24-4 is connected to the TEST terminal as well as the short detection circuits 24-5, 24-6, and controls the short detection circuits 24-5, 24-6 in response to input signals (inspection signals) input from the TEST terminal.

(42) Next, explanation follows regarding operation of the inspection circuit 14a. The inspection circuit 14a has a normal mode and an inspection mode, similarly to the inspection circuit 14. As illustrated by the dashed arrow labeled <5>, in the normal mode, signals sent from the C_CKE terminal to the CKE terminal are input to the CKE control circuit 30 so as to control the CKE control circuit 30. Similarly, as illustrated by the dashed arrow labeled <5>, data signals sent from the C_DQ terminal to the DQ terminal are input to the DQ control circuit 28 to write to the DRAM 12. Further, as illustrated by the dashed arrow labeled <8>, read signals from the DRAM 12 are sent from the DQ control circuit 28 to the C_DQ terminal of the controller IC 18 via the DQ terminal.

(43) In the inspection mode, a TEST signal is sent from the C_TEST terminal of the controller IC 18 to the TEST terminal of the DRAM 12 in order to activate the short detection circuits 24-4, 24-5, 24-6. When this is performed, the CKE terminal is isolated from the CKE control circuit 30 at the short detection circuit 24-5. Namely, the CKE control circuit 30 is applied with an H level signal from the short detection circuit 24-5 via the route labeled <7> in FIG. 5, placing the interior of the DRAM 12 in a WRT command state. Note that although the CKE terminal according to the present exemplary embodiment is active high, as described above, obviously the opposite logic may also be employed.

(44) At the same time, the DQ terminal is isolated from the DQ control circuit 28 at the short detection circuit 24-6, and a signal input to the CKE terminal is sent to the DQ control circuit 28 via the route labeled <6> in FIG. 5 and is written to the DRAM 12. The data written to the DRAM 12 is read by the controller IC 18 through the DQ terminal via the route <8> in FIG. 5. The above operation enables inspection as to whether or not a short abnormality has arisen between the C_CKE terminal and the CKE terminal. Namely, in the inspection mode, a signal via the route labeled by the dashed arrow <7> is an input signal for the CKE control circuit 30, and the signal labeled by the dashed arrow <6> is an input (write) data signal for the DQ control circuit 28.

(45) More detailed explanation follows regarding operation of the inspection circuit 14a, with reference to FIG. 6 and FIG. 7. FIG. 6 is a timing chart illustrating operation of the inspection circuit 14a in a case in which a short abnormality has not occurred between the C_CKE terminal and the CKE terminal. FIG. 6 illustrates commands sent from the controller IC 18 to the DRAM 12 and the waveforms at respective sections. FIG. 7 is a timing chart illustrating operation of the inspection circuit 14a in a case in which a short abnormality has occurred between the C_CKE terminal and the CKE terminal. FIG. 7 illustrates commands sent from the controller IC 18 to the DRAM 12 and the waveforms at respective sections.

(46) The commands, the clock signal CLK (CK), and the TEST signal illustrated at <1> in FIG. 6 are similar to those at <1> in FIG. 3, and so detailed explanation thereof is omitted.

(47) Explanation follows regarding operation when an H level is input to the CKE terminal of the DRAM 12 from the C_CKE terminal of the controller IC 18 in cases in which a short abnormality has not occurred between the C_CKE terminal and the CKE terminal, with reference to <2> in FIG. 6. In this operation, an H level is written from the C_CKE terminal of the controller IC 18 via the CKE terminal of the DRAM 12, and this H level is read from the DRAM 12.

(48) To begin, a signal input to the CKE terminal has the waveform illustrated at <3> in FIG. 6. Namely, the signal input to the CKE terminal is H level at the WRT command timing in order to write an H level to the DRAM 12. When this is performed, as illustrated at <4> in FIG. 6, since the input signal of the CKE terminal is active high, the input of the CKE control circuit 30 is set to H level by the short detection circuit 24-5. The CKE control circuit 30 operates accordingly. As illustrated at <5> in FIG. 6, at the WRT command timing, the H level input to the CKE terminal is input to the DQ control circuit 28 by the short detection circuit 24-6. Namely, an H level is written to the DRAM 12.

(49) Accordingly, in a read operation, as illustrated at <6> in FIG. 6, an H level is read via the DQ terminal, with the logic of the write data and the logic of the read data of the DRAM 12 matching each other at the H level. The controller IC 18 therefore determines the connection between the C_CKE terminal and the CKE terminal to be correct.

(50) Next, explanation follows regarding operation when an L level is input to the CKE terminal of the DRAM 12 from the C_CKE terminal of the controller IC 18 in cases in which a short abnormality has not occurred between the C_CKE terminal and the CKE terminal, with reference to <7> in FIG. 6. In this operation, an L level is written from the C_CKE terminal of the controller IC 18 via the CKE terminal of the DRAM 12, and this L level is read from the DRAM 12.

(51) To begin, a signal input to the CKE terminal has the waveform as illustrated at <8> in FIG. 6. Namely, the controller IC 18 inputs an L level to the CKE terminal at the WRT command timing. Since the CKE control circuit 30 normally operates at the H level, as illustrated at <9> in FIG. 6, the short detection circuit 24-5 converts the L level signal input to the CKE terminal to H level at the WRT command timing and inputs the converted H level signal to the CKE control circuit 30.

(52) As illustrated at <10> in FIG. 6, the signal input to the DQ control circuit 28 at the WRT command timing is at the L level due to an L level CKE signal being input via the short detection circuits 24-5, 24-4, 24-6. Namely, an L level is written to the DRAM 12. Accordingly, in a read operation, as illustrated at <11> in FIG. 6, an L level is read via the DQ terminal, with the logic of the write data and the logic of the read data matching each other at the L level. The controller IC 18 therefore determines the connection between the C_CKE terminal and the CKE terminal to be correct.

(53) Next, explanation follows regarding operation of the inspection circuit 14a in cases in which a short abnormality has occurred between the C_CKE terminal and the CKE terminal, with reference to FIG. 7. This example assumes a short abnormality to the H level, for example a short circuit to a power source VDD, has occurred between the C_CKE terminal and the CKE terminal. The commands, the CLK (CK) signal, and the TEST signal illustrated at <1> in FIG. 7 are similar to those illustrated at <1> in FIG. 3, and so detailed explanation thereof is omitted.

(54) As illustrated at <2> in FIG. 7, in this example, the controller IC 18 sends an L level from the C_CKE terminal to the CKE terminal of the DRAM 12 as an input signal (test signal) to inspect the CKE terminal of the DRAM 12. However, since a short to the H level has occurred between the C_CKE terminal and the CKE terminal, as illustrated at <3> in FIG. 7, the CKE terminal input remains at the H level. In order to achieve normal operation of the CS control circuit 26, as illustrated at <4> in FIG. 7, the short detection circuit 24-5 sends an H level to the CKE control circuit 30.

(55) However, in this example, when attempting to write an L level to the 1-bit memory in the DRAM 12, since the signal input to the CKE terminal remains at the H level, as illustrated at <5> in FIG. 7, the short detection circuit 24-6 sends an H level to the DQ control circuit 28. Accordingly, an H level is written to the DRAM 12. As illustrated at <6> in FIG. 7, the controller IC 18 therefore reads an H level from the DRAM 12 via the DQ terminal. Even if an L level has been written, the level read from the DRAM 12 will always be H level. Since the write data and the read data do not match, the controller IC 18 determines that a short abnormality to the H level has occurred in the connection between the C_CKE terminal and the CKE terminal.

(56) As described above, the inspection circuit, the semiconductor storage element, the semiconductor device, and the connection inspection method according to the present exemplary embodiment may easily detect a short abnormality (short circuit), in cases in which the short abnormality has occurred in the connection between the C_CKE terminal and the CKE terminal.

(57) Note that in the exemplary embodiments described above, explanation has been given regarding configurations of a semiconductor device that inspects either the connection between the C_CS terminal of the controller IC 18 and the CS terminal of the DRAM 12 separately or inspects the connection between the C_CKE terminal of the controller IC 18 and the CKE terminal of the DRAM 12. However, there is no limitation thereto, and, for example, the semiconductor device may be configured with functionality to inspect both of these connections. In such cases, basically both the inspection circuit 14 illustrated in FIG. 2 and the inspection circuit 14a illustrated in FIG. 5 are provided, and configuration may be such that the short detection circuit 24-1 and the short detection circuit 24-4 employ common configuration, with a single C_TEST terminal being provided to the controller IC 18 and a single TEST terminal being provided to the DRAM 12.