DISPLAY APPARATUS AND DATA DRIVER

Abstract

In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

Claims

1. A display apparatus, comprising: a display panel, comprising a plurality of data lines comprising a first data line group and a second data line group, and a plurality of gate lines disposed intersecting the plurality of data lines; a gate driver, supplying a gate selection signal to each of the plurality of gate lines; and a plurality of data drivers, provided for each predetermined number of data lines, each generating a positive polarity gradation data signal higher than a predetermined standard voltage and a negative polarity gradation data signal lower than the standard voltage in response to a video signal, and alternately and repeatedly executing an operation of supplying the positive polarity gradation data signal to the first data line group and supplying the negative polarity gradation data signal to the second data line group and an operation of supplying the positive polarity gradation data signal to the second data line group and supplying the negative polarity gradation data signal to the first data line group, wherein each of the plurality of data drivers comprises: a control part, executing either a first output mode or a second output mode, and switching from the first output mode to the second output mode or from the second output mode to the first output mode within a predetermined period at intervals of the predetermined period, wherein, in the first output mode, a signal in which a data pulse having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle is output as the positive polarity gradation data signal based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with a phase different from that of the positive polarity gradation data signal is output as the negative polarity gradation data signal based on the video signal, and in the second output mode, a signal in which a data pulse having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle is output as the positive polarity gradation data signal based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with the same phase as that of the positive polarity gradation data signal is output as the negative polarity gradation data signal based on the video signal.

2. The display apparatus according to claim 1, wherein the negative polarity gradation data signal in the first output mode is a signal whose phase is shifted in a direction of being delayed with respect to the phase of the positive polarity gradation data signal.

3. The display apparatus according to claim 2, wherein the control part has a function of adjusting a time length of the phase shift.

4. The display apparatus according to claim 2, wherein the control part reduces a time length of the phase shift of the negative polarity gradation data signal with respect to the positive polarity gradation data signal as a wiring length of the plurality of gate lines wired from the plurality of data lines that receive the gradation data signals to an output terminal of the gate driver is reduced.

5. The display apparatus according to claim 1, wherein the control part controls N frame periods in the video signal to the first output mode, controls M frame periods in the video signal to the second output mode, and controls the N frame periods and the M frame periods to be switched alternately, wherein N and M are each an integer of 1 or more.

6. The display apparatus according to claim 1, wherein the control part divides all of the gradation data signals to be output to the first data line group and the second data line group into a first gradation data signal group and a second gradation data signal group, outputs the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the first gradation data signal group in the first output mode in each frame, and outputs the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the second gradation data signal group in the second output mode in each frame.

7. The display apparatus according to claim 1, wherein, in each frame in the video signal, the control part comprised in at least one of the plurality of data drivers executes one of the first output mode and the second output mode, and the control part comprised in another one of the plurality of data drivers executes the other of the first output mode and the second output mode.

8. The display apparatus according to claim 6, wherein the control part switches the first output mode and the second output mode from one state to another state or from the another state to the one state every N frame periods in the video signal, wherein N is an integer of 1 or more.

9. The display apparatus according to claim 1, further comprising: a display controller, superimposing an output mode designation signal that designates the first output mode or the second output mode on the video signal and supplying the same to the plurality of data drivers.

10. A data driver, configured to generate and output a plurality of positive polarity gradation data signals having a positive polarity voltage value higher than a predetermined standard voltage and a plurality of negative polarity gradation data signals having a negative polarity voltage value lower than the standard voltage in response to a video signal, the data driver comprising: a control part, executing either a first output mode or a second output mode, and switching from the first output mode to the second output mode or from the second output mode to the first output mode within a predetermined period at intervals of the predetermined period, wherein, in the first output mode, a signal in which a data pulse having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle is output as the positive polarity gradation data signal based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with a phase different from that of the positive polarity gradation data signal is output as the negative polarity gradation data signal based on the video signal, and in the second output mode, a signal in which a data pulse having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle is output as the positive polarity gradation data signal based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with the same phase as that of the positive polarity gradation data signal is output as the negative polarity gradation data signal based on the video signal.

11. The data driver according to claim 10, wherein the negative polarity gradation data signal in the first output mode is a signal whose phase is shifted in a direction of being delayed with respect to the phase of the positive polarity gradation data signal.

12. The data driver according to claim 11, wherein the control part has a function of adjusting a time length of the phase shift.

13. The data driver according to claim 10, wherein the control part reduces a time length of the phase shift of the negative polarity gradation data signal with respect to the positive polarity gradation data signal as a wiring length of a gate line wired from a data line that receives the gradation data signals to an output terminal of a gate driver is reduced.

14. The data driver according to claim 10, wherein the control part controls N frame periods in the video signal to the first output mode, controls M frame periods in the video signal to the second output mode, and controls the N frame periods and the M frame periods to be switched alternately, wherein N and M are each an integer of 1 or more.

15. The data driver according to claim 10, wherein the control part divides all of the gradation data signals to be output to a first data line group and a second data line group into a first gradation data signal group and a second gradation data signal group, outputs the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the first gradation data signal group in the first output mode in each frame, and outputs the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the second gradation data signal group in the second output mode in each frame.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 is a waveform diagram showing an example of waveforms of a gate selection signal applied to a gate line and positive polarity and negative polarity gradation data signals applied to a pair of adjacent data lines by conventional driving.

[0035] FIG. 2 illustrates an example of crosstalk (streak unevenness) appearing in an image with a gray background that includes a white square area in the center of a screen when the image is displayed.

[0036] FIG. 3 is a waveform diagram showing waveforms of a group of gradation data signals which, in order to display an image with a gray background that includes a white square area in the center of a screen, are respectively applied to a pair of data lines passing through the white square area and a pair of data lines not passing through the white square area, as well as a waveform of a counter substrate voltage.

[0037] FIG. 4 is a block diagram showing a configuration of a data driver 120 according to the disclosure.

[0038] FIG. 5A is a waveform diagram showing an example of a form of output timing signals LOAD1 and LOAD2 in a first output mode.

[0039] FIG. 5B is a waveform diagram showing an example of the form of the output timing signals LOAD1 and LOAD2 in a second output mode.

[0040] FIG. 6 is a time chart showing an example of transition of a polarity state (positive polarity or negative polarity) of each of gradation data signals Vd1 to Vd4 output from the data driver 120.

[0041] FIG. 7 is a waveform diagram showing an example of waveforms of the gate selection signal Vgk applied to a gate line and the positive polarity gradation data signal Vdx and the negative polarity gradation data signal Vd(x+1) applied to a pair of data lines in the first output mode.

[0042] FIG. 8 is a waveform diagram showing an example of the waveforms of the gate selection signal Vgk applied to a gate line and the positive polarity gradation data signal Vdx and the negative polarity gradation data signal Vd(x+1) applied to a pair of data lines in the second output mode.

[0043] FIG. 9 is a block diagram showing an example of an internal configuration of the data driver 120.

[0044] FIG. 10 schematically illustrates an example of a structure of a display cell 154.

[0045] FIG. 11 illustrates an example of a setting form of an output mode with respect to a first data driver group and a second data driver group.

[0046] FIG. 12 illustrates another example of the setting form of the output mode with respect to the first data driver group and the second data driver group.

[0047] FIG. 13A is a waveform diagram showing a form of output timing signal groups LOAD1-Grs and LOAD2-Grs generated in the first output mode.

[0048] FIG. 13B is a waveform diagram showing a form of the output timing signal groups LOAD1-Grs and LOAD2-Grs generated in the second output mode.

DESCRIPTION OF THE EMBODIMENTS

[0049] The disclosure provides a display apparatus and a data driver in which, in driving a display panel by column inversion driving, an image can be displayed with reduced flicker and image quality deterioration such as crosstalk.

[0050] In the disclosure, upon inversion of the polarity of a gradation data signal every one frame period based on a video signal and output of the same to each data line of a display panel by column inversion driving, a first output mode and a second output mode below are alternatively executed while being switched.

[0051] In the first output mode, a phase of a negative polarity gradation data signal is shifted in a direction of being delayed with respect to a positive polarity gradation data signal. Accordingly, even if rounding occurs at a rear edge of a gate selection signal applied to a gate line of the display panel, a difference between a pixel charging rate by the negative polarity gradation data signal and a pixel charging rate by the positive polarity gradation data signal can be reduced. Thus, according to the first output mode, it is possible to suppress flicker or image quality deterioration in association with the difference between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal.

[0052] On the other hand, in the second output mode, the positive polarity gradation data signal and the negative polarity gradation data signal have the same phase. According to the second output mode, a difference occurs between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal. However, since the positive polarity gradation data signal and the negative polarity gradation data signal have the same phase, crosstalk (streak unevenness) due to the different phases of the two gradation data signals in the first output mode does not occur.

[0053] Accordingly, by performing output of the gradation data signal in the first output mode and output of the gradation data signal in the second output mode alternately, a state in which crosstalk (streak unevenness) occurs and a state in which crosstalk does not occur are visually integrated in a time direction, and visually recognized crosstalk (streak unevenness) is reduced.

[0054] Accordingly, according to the disclosure, an image can be displayed with reduced flicker or image quality deterioration such as crosstalk (streak unevenness).

[0055] FIG. 4 is a block diagram showing an internal structure of the data driver 120 according to the disclosure, in which the data driver 120 drives a liquid crystal display panel according to a video signal.

[0056] The data driver 120 receives a video signal DVS in serial form, generates gradation data signals Vd1 to Vdi (i is an integer of 2 or more) corresponding to a luminance level of each pixel represented by the video signal DVS, and outputs each of them to the outside via output terminals T1 to Ti. The output terminals T1 to Ti are terminals for connecting to i data lines of a display panel.

[0057] The data driver 120 is formed of a semiconductor IC chip, and includes a gradation voltage generator 54, a level shifter 80, a decoder part 90, an output amplifier 95, a control core 510, a setting storage part 600, a timing control part 650, and a latch part 700.

[0058] The control core 510 performs deserialization, that is, serial-to-parallel conversion processing, on the video signal DVS in serial form. Through the serial-to-parallel conversion, the control core 510 extracts a series of video data PD, digital setting information, and a clock signal CLK from the video signal DVS. The digital setting information includes output delay direction information CF, output delay shift amount information SA1 and SA2, and output start timing information TA1 and TA2.

[0059] The output delay direction information CF is information as below designating an increasing direction of an output delay time with respect to each of first to i-th output channels that output the gradation data signals Vd1 to Vdi. That is, the output delay direction information CF is information designating whether to increase the output delay time of each of a positive polarity gradation data signal and a negative polarity gradation data signal in either ascending or descending order of the output channel number, or whether to increase the output delay time from both end sides toward the center of the i output channels. The output delay shift amount information SA1 is information indicating, as a delay shift amount when a positive polarity gradation data signal is output, a delay time taken for each output channel group obtained by dividing the first to i-th output channels into a plurality of groups from when a positive polarity gradation data signal corresponding to the leading output channel in the output channel group is output until a positive polarity gradation data signal corresponding to the last output channel is output. The output delay shift amount information SA2 is information indicating, as a delay shift amount when a negative polarity gradation data signal is output, a delay time taken for each of the above output channel group from when a negative polarity gradation data signal corresponding to the leading output channel in the output channel group is output until a negative polarity gradation data signal corresponding to the last output channel is output. The output start timing information TA1 is information designating an output timing of the leading channel with respect to an output channel group serving to output a positive polarity gradation data signal Vd. The output start timing information TA2 is information designating an output timing of the leading channel with respect to an output channel group serving to output a negative polarity gradation data signal Vd.

[0060] The control core 510 supplies the digital setting information (CF, SA1, SA2, TA1, and TA2) to the setting storage part 600 and supplies the series of video data PD to the latch part 700.

[0061] The control core 510 generates a binary (of logic level 0 or 1) polarity inversion signal POL that inverts the polarity of each gradation data signal output by the data driver 120 per frame period based on the video signal DVS, and supplies the same to the latch part 700.

[0062] The control core 510 generates a binary standard timing signal STD of one horizontal cycle (1H cycle) based on the video signal DVS, and supplies the same to the timing control part 650.

[0063] In response to the standard timing signal STD, the control core 510 takes a video signal for positive polarity into the latch part 700 every one horizontal scanning period, and generates an output timing signal LOAD1 indicating a timing of outputting the same. Furthermore, in response to the standard timing signal STD, the control core 510 takes a video signal for negative polarity into the latch part 700 every one horizontal scanning period, and generates an output timing signal LOAD2 indicating a timing of outputting the same. The output timing signals LOAD1 and LOAD2 are binary signals in which, for example, a pulse having a voltage value corresponding to logic level 0 and a pulse having a voltage value corresponding to logic level 1 alternately appear every one horizontal scanning period.

[0064] Here, the control core 510 includes an output mode setting part set to, in generating the output timing signals LOAD1 and LOAD2, the first output mode in which the phase of the output timing signal LOAD2 is delayed with respect to the output timing signal LOAD1 as shown in FIG. 5A or the second output mode in which the phases of the output timing signals LOAD1 and LOAD2 are matched as shown in FIG. 5B.

[0065] In the first output mode, the control core 510 has a function of adjusting a phase shift amount (that is, a time length) for delaying the phase of the output timing signal LOAD2 with respect to the output timing signal LOAD1 to any time length specified in advance.

[0066] The control core 510 supplies the output timing signals LOAD1 and LOAD2 generated by the output mode setting part to the timing control part 650 and the latch part 700.

[0067] The setting storage part 600 captures and stores the digital setting information (CF, SA1, SA2, TA1, and TA2) supplied from the control core 510. The setting storage part 600 supplies the stored digital setting information, that is, the output delay direction information CF, the output delay shift amount information SA1 and SA2 and the output start timing information TA1 and TA2, to the timing control part 650. The digital setting information stored in the setting storage part 600 is refreshed in every predetermined cycle.

[0068] The timing control part 650 includes functional blocks respectively for positive polarity and negative polarity, and generates a timing signal for outputting video data signals respectively for positive polarity and negative polarity that are taken into the latch part 700 described later.

[0069] That is, the functional block (positive polarity timing control part) for positive polarity of the timing control part 650 generates an output timing signal group LOAD1-Grs of a gradation data signal for positive polarity based on the output delay direction information CF, the output delay shift amount information SA1, the output start timing information TA1, the standard timing signal STD and the output timing signal LOAD1.

[0070] The functional block (negative polarity timing control part) for negative polarity of the timing control part 650 generates an output timing signal group LOAD2-Grs of a gradation data signal for negative polarity based on the output delay direction information CF, the output delay shift amount information SA2, the output start timing information TA2, the standard timing signal STD and the output timing signal LOAD2.

[0071] The output timing signal group LOAD1-Grs (LOAD2-Grs) is, for each of the above output channel group, a signal group representing an output timing of a gradation data signal corresponding to the output channel group. For example, the positive polarity timing control part generates the output timing signal group LOAD1-Grs indicating a timing delayed by a time based on the output delay direction information CF, the output delay shift amount information SA1 and the output start timing information TA1 from the output timing signal LOAD1 as a starting point. The negative polarity timing control part generates the output timing signal group LOAD2-Grs indicating a timing delayed by a time based on the output delay direction information CF, the output delay shift amount information SA2 and the output start timing information TA2 from the output timing signal LOAD2 as a starting point.

[0072] The timing control part 650 supplies the output timing signal groups LOAD1-Grs and LOAD2-Grs to the latch part 700.

[0073] The latch part 700 includes a positive polarity data latch 710 and a negative polarity data latch 720. The latch part 700 sorts each video data PD in the series of video data PD into those for positive polarity and those for negative polarity in response to the polarity inversion signal POL.

[0074] In response to the output timing signal LOAD1, the positive polarity data latch 710 captures each video data PD sorted for positive polarity. Based on the output timing signal group LOAD1-Grs corresponding to the corresponding output channel, the positive polarity data latch 710 outputs each of the captured video data PD for positive polarity as video data P at an output timing set for each predetermined output channel group.

[0075] In response to the output timing signal LOAD2, the negative polarity data latch 720 captures each video data PD sorted for negative polarity. Based on the output timing signal group LOAD2-Grs corresponding to the corresponding output channel, the negative polarity data latch 720 outputs each of the captured video data PD for negative polarity as video data P at an output timing set for each predetermined output channel group.

[0076] The latch part 700 supplies i (i is an integer of 2 or more) pieces of video data P output from the positive polarity data latch 710 and the negative polarity data latch 720 as video data P1 to Pi to the level shifter 80.

[0077] The level shifter 80 supplies, to the decoder part 90, video data J1 to Ji obtained by subjecting each of the i pieces of video data P1 to Pi supplied from the latch part 700 to level shift processing that increases a signal level (voltage amplitude) of the data.

[0078] The gradation voltage generator 54 generates L (L is an integer of 2 or more) voltages having different voltage values and higher than a standard voltage as a group of positive polarity reference voltages X1 to XL in which a pixel luminance level is represented in L stages. Furthermore, the gradation voltage generator 54 generates L voltages having different voltage values and lower than the standard voltage as a group of negative polarity reference voltages Y1 to YL in which the pixel luminance level is represented in L stages.

[0079] For example, the gradation voltage generator 54 divides voltages between a predetermined high potential VGH and a predetermined low potential VGL lower than the high potential VGH into a plurality of voltages by a ladder resistor, thereby generating the above groups of reference voltages X1 to XL and Y1 to YL.

[0080] The standard voltage is, for example, a voltage (hereinafter referred to as counter substrate voltage VCOM) applied to a counter substrate electrode disposed facing an electrode corresponding to each pixel in a display panel to be driven by the data driver 120.

[0081] The gradation voltage generator 54 supplies the group of positive polarity reference voltages X1 to XL and the group of negative polarity reference voltages Y1 to YL generated to the decoder part 90.

[0082] The decoder part 90 includes i decoders DEC that individually convert each of the video data J1 to Ji into a gradation data signal having an analog voltage value.

[0083] Each of the decoders DEC receives the group of positive polarity reference voltages X1 to XL and the group of negative polarity reference voltages Y1 to YL from the gradation voltage generator 54. Furthermore, each of the i decoders DEC individually receives one of the video data J1 to Ji.

[0084] Each decoder DEC, if the video data J received by the decoder DEC itself is positive polarity data, selects one or more reference voltages designated by the video data J from among the group of positive polarity reference voltages X1 to XL. On the other hand, if the video data J received by the decoder DEC itself is negative polarity data, the decoder DEC selects one or more reference voltages designated by the video data J from among the group of negative polarity reference voltages Y1 to YL.

[0085] The decoder part 90 outputs, to the output amplifier 95, one or more reference voltages selected by each decoder DEC as a gradation voltage corresponding to the luminance level of each pixel.

[0086] The output amplifier 95 includes i output amplifiers (op-amps) respectively corresponding to the i decoders DEC included in the decoder part 90. Each of the output amplifiers is a voltage follower whose output terminal and inverting input terminal (−) are connected together, and receives, by its non-inverting input terminal (+), one or more reference voltages supplied from its corresponding decoder DEC. By amplifying one or more reference voltages received by its non-inverting input terminal (+), each of the i output amplifiers generates a pulse voltage having a voltage value corresponding to the video data J as a gradation data pulse corresponding to the luminance level and outputs the same through the output terminal. The gradation data pulse is continuously output every one data period (for example, one horizontal scanning period) within one frame period. Each of the i output amplifiers outputs, as a gradation data signal Vd, a signal including a series of gradation data pulses appearing every one data period to the outside via the i output terminals T1 to Ti of the semiconductor IC. That is, the i gradation data signals Vd output from the i output amplifiers are supplied to the i data lines of the display panel respectively connected to the output terminals T1 to Ti.

[0087] The column inversion driving by the data driver 120 shown in FIG. 4 will be described in detail below.

[0088] FIG. 6 is a time chart showing an example of a state (positive polarity or negative polarity) of each of the gradation data signals Vd1 to Vd4 output from, for example, the output terminals T1, T2, T3, and T4 of the data driver 120 by the column inversion driving.

[0089] As shown in FIG. 6, in one frame period during which the polarity inversion signal POL is logic level 1, each of the odd-numbered gradation data signals Vd1 and Vd3 among the gradation data signals Vd1 to Vd4 has positive polarity. In one frame period during which the polarity inversion signal POL is logic level 1, each of the even-numbered gradation data signals Vd2 and Vd4 among the gradation data signals Vd1 to Vd4 has negative polarity, as shown in FIG. 6.

[0090] As shown in FIG. 6, in one frame period during which the polarity inversion signal POL is logic level 0, each of the odd-numbered gradation data signals Vd1 and Vd3 among the gradation data signals Vd1 to Vd4 has negative polarity. In one frame period during which the polarity inversion signal POL is logic level 0, each of the even-numbered gradation data signals Vd2 and Vd4 among the gradation data signals Vd1 to Vd4 has positive polarity, as shown in FIG. 6.

[0091] Furthermore, in performing such column inversion driving, the data driver 120 controls consecutive N (N is an integer of 1 or more) frame periods in the video signal DVS to the first output mode shown in FIG. 5A, and controls consecutive M (M is an integer of 1 or more) frame periods to the second output mode shown in FIG. 5B. Furthermore, control is performed to alternately switch between the N frame periods controlled to the first output mode and the M frame periods controlled to the second output mode.

[0092] An output form of a gradation data signal in each of the first and second output modes will be described below with reference to a waveform diagram in the first output mode shown in FIG. 7 and a waveform diagram in the second output mode shown in FIG. 8.

[0093] FIG. 7 and FIG. 8 show an example of a waveform of each of the positive polarity gradation data signal Vdx and the negative polarity gradation data signal Vd(x+1) applied to adjacent data lines DLx and DL(x+1) among the i data lines (hereinafter referred to as data lines DL1 to DLi) of the display panel connected to the data driver 120. Furthermore, in FIG. 7 and FIG. 8, a waveform of the gate selection signal Vgk applied to a gate line GLk disposed in a k-th (k is an integer of 1 to r, and r is an integer of 2 or more) place among r gate lines (hereinafter referred to as gate lines GL1 to GLr) disposed in the display panel is indicated by a dot-and-dash line. That is, in FIG. 7 and FIG. 8, a pulse waveform of the gate selection signal Vgk observed at the position of an intersection with the data lines DLx and DL(x+1) on the gate line GLk is shown.

[0094] As shown in FIG. 7 and FIG. 8, in the gate selection signal Vgk, relatively large waveform rounding occurs under the influence of a high impedance in association with a wiring length of a gate line from a gate driver. On this occasion, in the example shown in FIG. 7 and FIG. 8, it is assumed that the gate selection signal Vgk is subjected to a gate precharge in order to increase the pixel charging rate. That is, the gate selection signal Vgk, together with gradation data pulses Dpk and Dnk corresponding to display cells (pixels) in the k-th row, maintain the high potential VGH in an application period of the gradation data pulses Dp(k+1) and Dn(k+1) prior to the one data period corresponding to the display cells (pixels) in a (k+1)-th row.

[0095] FIG. 7 and FIG. 8 show the waveforms of the gate selection signal Vgk and the gradation data signal Vdx when writing (charging) based on the gradation data pulse Dpk included in the gradation data signal Vdx is performed on a pixel at an intersection of the data line DLx and the gate line GLk in response to the gate selection signal Vgk. FIG. 7 and FIG. 8 show the waveforms of the gate selection signal Vgk and the gradation data signal Vd(x+1) when writing (charging) based on the gradation data pulse Dnk included in the gradation data signal Vd(x+1) is performed on a pixel at an intersection of the data line DL(x+1) and the gate line GLk in response to the gate selection signal Vgk.

[0096] In FIG. 7 and FIG. 8, each of gradation data pulses Dp included in the positive polarity gradation data signal Vdx has a gradation voltage within the voltage range from the lower limit Lpy to the upper limit Lpz. Similarly, each of gradation data pulses Dn included in the negative polarity gradation data signal Vd(x+1) has a gradation voltage within the voltage range from the upper limit Lny to the lower limit Lnz. In FIG. 7 and FIG. 8, the counter substrate voltage VCOM is set between the lower limit Lpy of the positive polarity gradation data signal and the upper limit Lny of the negative polarity gradation data signal. In FIG. 7 and FIG. 8, for convenience of description, gradation data pulses included in the gradation data signals Vdx and Vd(x+1) exhibit a driving pattern in which the gradation voltages of the upper limit and the lower limit within the respective voltage ranges are alternately output every one data period.

[0097] [First Output Mode]

[0098] As shown in FIG. 7, in the first output mode, in response to the output timing signal groups LOAD1-Grs and LOAD2-Grs, the output timing of each of the gradation data signals Vdx and Vd(x+1) is controlled so that the timings of the positive polarity gradation data pulse Dpk and the negative polarity gradation data pulse Dnk are different from each other.

[0099] That is, in the first output mode, as shown in FIG. 7, the phase of the negative polarity gradation data pulse Dnk is delayed with respect to the positive polarity gradation data pulse Dpk by a predetermined phase shift amount.

[0100] Timing control of the positive polarity gradation data signal Vdx and the gate selection signal Vgk will be described below.

[0101] The data driver 120 sets the output timing of the positive polarity gradation data signal Vdx as follows so that a gradation data pulse Dp(k−1) in a data period next to the gradation data pulse Dpk is not supplied to a display cell (pixel) by the gate selection signal Vgk.

[0102] That is, as shown in FIG. 7, the data driver 120 outputs the positive polarity gradation data signal Vdx at a timing so that a potential of a rear edge of the gate selection signal Vgk becomes equal to or lower than the lower limit Lpy of the positive polarity gradation data pulse Dpk at a time of a rear edge of the gradation data pulse Dpk. For example, the phase of the positive polarity gradation data signal Vdx may be adjusted by the timing control part 650 so that such an output form is achieved.

[0103] Accordingly, an effective pixel charging period by the positive polarity gradation data pulse Dpk can be set to a pixel charging period Tp2 equivalent to one data period T1H, as shown in FIG. 7.

[0104] As shown in FIG. 7, the data driver 120 performs a phase shift in a direction of delaying the phase of the negative polarity gradation data signal Vd(x+1) by a time length Ts21 with respect to the phase of the positive polarity gradation data signal Vdx.

[0105] Accordingly, as shown in FIG. 7, the data driver 120 outputs the negative polarity gradation data signal Vd(x+1) synchronized with the output timing signal group LOAD2-Grs and having a phase shifted in a direction of being delayed by the time length Ts21 with respect to the positive polarity gradation data signal Vdx synchronized with the output timing signal group LOAD1-Grs. As a result, as shown in FIG. 7, at a time before a rear edge of the gradation data pulse Dnk included in the negative polarity gradation data signal Vd(x+1), the potential of the rear edge of the gate selection signal Vgk becomes equal to or lower than the lower limit Lpy of the gradation data pulse Dnk.

[0106] Thus, as shown in FIG. 7, the effective pixel charging period by the negative polarity gradation data pulse Dnk is a pixel charging period Tn2 shorter than one data period T1H by a time length Ts22 (0). An effect of the time length Ts22 is as follows.

[0107] Since a potential difference between the gate selection signal Vgk and a gradation data signal is larger in the negative polarity than in the positive polarity, the pixel charging rate is higher in the negative polarity in the same pixel charging period. Accordingly, the time length Ts22 is provided as a period for adjusting a difference in pixel charging rate between the positive polarity and the negative polarity in association with the potential difference between the gate selection signal Vgk and the gradation data signal.

[0108] That is, by the above driving, it is possible to secure a period equivalent to one data period T1H as the effective pixel charging period Tp2 by the positive polarity gradation data pulse Dpk and to reduce the effective pixel charging period Tn2 by the negative polarity gradation data pulse Dnk to be equal to or less than one data period T1H.

[0109] Accordingly, it is possible to make the pixel charging period Tp2 by the positive polarity gradation data pulse Dpk longer than the pixel charging period Tp1 shown in FIG. 1 and to make the pixel charging period Tn2 by the negative polarity gradation data pulse Dnk equal to or less than the pixel charging period Tn1 shown in FIG. 1.

[0110] In this way, by increasing the pixel charging rate by the positive polarity gradation data signal while adjusting the pixel charging rate by the negative polarity gradation data signal to be low, a difference between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal is reduced.

[0111] Accordingly, even if rounding occurs at a pulse edge of the gate selection signal, it is possible to suppress flicker and image quality deterioration caused by the difference between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal.

[0112] [Second Output Mode]

[0113] As shown in FIG. 8, in the second output mode, in response to the output timing signal groups LOAD1-Grs and LOAD2-Grs, the output timing of each of the gradation data signals Vdx and Vd(x+1) is controlled so that the timings of the positive polarity gradation data pulse Dpk and the negative polarity gradation data pulse Dnk are the same as each other.

[0114] Thus, according to the second output mode shown in FIG. 8, while there is a difference between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal, since the positive polarity gradation data signal and the negative polarity gradation data signal have the same phase, crosstalk (streak unevenness) caused by different phases of the two gradation data signals in the first output mode does not occur.

[0115] Here, the data driver 120 outputs a gradation data signal according to the first output mode shown in FIG. 7 for consecutive N (N is an integer of 1 or more) frame periods, outputs a gradation data signal according to the second output mode shown in FIG. 8 for consecutive M (M is an integer of 1 or more) frame periods, and alternately switches between the N frame periods controlled to the first output mode and the M frame periods controlled to the second output mode.

[0116] Accordingly, since a state (first output mode) in which crosstalk (streak unevenness) as shown in FIG. 2 occurs and a state (second output mode) in which the crosstalk does not occur are visually integrated in the time direction, visually recognized crosstalk (streak unevenness) is reduced. By adjusting the numbers N and M of frame periods, it is possible to adjust a ratio of a control period in the first output mode and the second output mode and maximize the effect of reducing crosstalk (streak unevenness).

[0117] Accordingly, according to the data driver 120, it is possible to display an image with reduced flicker or image quality deterioration such as crosstalk (streak unevenness).

[0118] In the above embodiment, the data driver 120 uniformly sets all output channels in each frame to one of the first output mode and the second output mode. However, an output channel group set to the first output mode and an output channel group set to the second output mode may coexist in each frame.

[0119] That is, the i gradation data signals output from the output terminals T1 to Ti are divided into a first gradation data signal group and a second gradation data signal group. In each frame, the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the first gradation data signal group are output in the first output mode, and the positive polarity gradation data signal and the negative polarity gradation data signal belonging to the second gradation data signal group are output in the second output mode. Furthermore, on this occasion, the output mode for outputting the first gradation data signal group and the output mode for outputting the second gradation data signal group are switched every N frames.

[0120] According to the above, as the data driver 120, one may be used which includes the following control part on the occasion of generating and outputting a plurality of positive polarity gradation data signals having a positive polarity voltage value higher than a predetermined standard voltage (VCOM) and a plurality of negative polarity gradation data signals having a negative polarity voltage value lower than the standard voltage in response to a video signal (DVS).

[0121] By executing either the following first output mode or the second output mode, and switching from the first output mode to the second output mode or from the second output mode to the first output mode within a predetermined period at intervals of the predetermined period, the control part (510, 650, 700) outputs a positive polarity gradation data signal and a negative polarity gradation data signal.

[0122] In the first output mode (FIG. 7), a signal in which a data pulse (Dp) having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle (T1H) is output as the positive polarity gradation data signal (Vdx) based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with a phase different from that of the positive polarity gradation data signal is output as the negative polarity gradation data signal [Vd(x+1)] based on the video signal. On the other hand, in the second output mode, a signal in which a data pulse having a positive polarity voltage value corresponding to a luminance level of each pixel appears in a predetermined cycle is output as the positive polarity gradation data signal based on the video signal, and a signal in which a data pulse having a negative polarity voltage value corresponding to a luminance level of each pixel appears in the predetermined cycle with the same phase as that of the positive polarity gradation data signal is output as the negative polarity gradation data signal based on the video signal.

[0123] FIG. 9 is a block diagram showing a configuration of a liquid crystal display 10 as a display apparatus according to the disclosure, the liquid crystal display 10 including the data driver 120 described above.

[0124] As shown in FIG. 9, the liquid crystal display 10 includes a display controller 100, a gate driver 110, data drivers 120-1 to 120-p (p is an integer of 2 or more) each being the data driver 120, and a display panel 150.

[0125] In the display panel 150, the gate lines GL1 to GLr (r is an integer of 2 or more) extending in a horizontal direction of a two-dimensional screen and the data lines DL1 to DLm (m is an integer of 2 or more) extending in a vertical direction of the two-dimensional screen are disposed intersecting each other. A display cell 154 serving as a unit pixel is formed at each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLm. Here, the entire area where the data lines DL1 to DLm and the gate lines GL1 to GLr are disposed serves as a display screen of the display panel 150.

[0126] FIG. 10 schematically illustrates a structure of the display cell 154.

[0127] As shown in FIG. 10, the display cell 154 includes a pixel electrode C1, a liquid crystal layer C2 and a counter substrate electrode C3 that are stacked together, and a thin film transistor TR as a pixel switch. FIG. 10 shows an example of an n-channel thin film transistor. The pixel electrode C1 is a transparent electrode provided independently for each display cell 154, and the counter substrate electrode C3 is a single transparent electrode covering the entire surface of the display panel 150. A control terminal of the thin film transistor TR is connected to a gate line GL, and a first terminal of the thin film transistor TR is connected to a data line DL. Furthermore, a second terminal of thin film transistor TR is connected to the pixel electrode C1. The counter substrate voltage VCOM as a standard voltage is applied to the counter substrate electrode C3.

[0128] The display controller 100 receives the video signal VD, and, based on the video signal VD, supplies to the gate driver 110 a gate timing signal indicating a timing of applying a gate selection signal to each of the gate lines GL1 to GLr.

[0129] Based on the video signal VD, the display controller 100 generates a clock signal and a series of video data PD indicating a luminance level of each pixel, and also generates the digital setting information as described above that corresponds to each of the data drivers 120-1 to 120-p. The display controller 100 includes an output mode designation part generating an output mode designation signal that designates which of the first output mode and the second output mode the output mode is to be set.

[0130] The display controller 100 supplies the video signal DVS including the clock signal, the series of video data PD, the digital setting information, and the output mode designation signal generated as above to the data drivers 120-1 to 120-p. In the liquid crystal display 10, in order to reduce the number of wires between the display controller 100 and each of the data drivers 120-1 to 120-p, the display controller 100 supplies the video signal DVS in the form of a serial signal to each data driver.

[0131] In response to the gate timing signal supplied from the display controller 100, the gate driver 110 generates gate selection signals Vg1 to Vg(r) (r is an integer of 2 or more) in order each including at least one pulse for selecting a gate line, and outputs each individually from each of the r output terminals. The gate driver 110 supplies the gate selection signals Vg1 to Vg(r) output from the r output terminals respectively to the gate lines GL1 to GLr of the display panel 150. In the example shown in FIG. 9, the gate driver 110 is disposed only on one end side of the gate lines GL1 to GLr of the display panel 150. However, a pair of gate drivers 110 may be disposed respectively on both end sides of the gate lines GL1 to GLr.

[0132] The data drivers 120-1 to 120-p are provided respectively corresponding to data line groups obtained by dividing the data lines DL1 to DLm of the display panel 150 into a first to p-th data line groups each consisting of i data lines adjacent to each other. Each of the output terminals T1 to Ti is connected to the i data lines belonging to the corresponding data line group.

[0133] As shown in FIG. 9, the data driver 120-1 is connected to the data lines DL1 to DLi serving to drive a plurality of display cells 154 disposed in an area on each of the gate lines GL1 to GLr of the display panel 150 where the wiring length from the output terminal of the gate driver 110 is relatively short. As shown in FIG. 9, the data driver 120-p is connected to the data lines DLx (x is 2 or more) to DLm serving to drive a plurality of display cells 154 disposed in an area on each of the gate lines GL1 to GLr of the display panel 150 where the wiring length from the output terminal of the gate driver 110 is relatively long.

[0134] By such a configuration, the data drivers 120-1 to 120-p capture the series of video data PD included in the video signal DVS in an amount (m pieces) corresponding to one horizontal scanning line at a time, and converts each video data PD into a gradation data signal having an analog voltage value corresponding to a luminance level. The data drivers 120-1 to 120-p supply the generated gradation data signals Vd1 to Vd(m) respectively to the data lines DL1 to DLm of the display panel 150.

[0135] Here, based on the output mode designation signal and the digital setting information supplied from the display controller 100, the output mode setting part of each of the data drivers 120-1 to 120-p individually sets each data driver to the first output mode or the second output mode.

[0136] For example, in the liquid crystal display 10, the data drivers 120-1 to 120-p are divided into a first data driver group and a second data driver group. As shown in FIG. 11, each data driver belonging to the first data driver group is set to the first output mode, and each data driver belonging to the second data driver group is set to the second output mode. That is, by coexistence of an area driven in the first output mode and an area driven in the second output mode within one frame of the display panel 150, a fluctuation amount of the counter substrate voltage VCOM in the display pattern in which crosstalk as shown in FIG. 2 is likely to be visually recognized is suppressed.

[0137] One of the first output mode and the second output mode respectively set for the first data driver group and the second data driver group may be switched to the other output mode every N (N is an integer of 2 or more) frame periods, as shown in FIG. 12. The allocation of the data drivers 120-1 to 120-p divided into the first data driver group and the second data driver group may be changed every N frame periods.

[0138] In the liquid crystal display 10, whether in the first or second output mode, a delay time of an output timing with a time when the standard timing signal STD rises (or falls) as a starting point in the output timing signal group LOAD1-Grs indicating the output timing of the positive polarity gradation data signal Vd is controlled for each of the data drivers 120-1 to 120-p.

[0139] The data driver 120-1 and the data driver 120-p are selected from the data drivers 120-1 to 120-p, and the output timing signal groups LOAD1-Grs and LOAD2-Grs generated by each of them will be described below. As shown in FIG. 9, the data driver 120-1 is disposed closest to the gate driver 110 and the data driver 120-p is disposed farthest from the gate driver 110.

[0140] FIG. 13A is a time chart showing timings of the output timing signal groups LOAD1-Grs and LOAD2-Grs of each of the data drivers 120-1 and 120-p in the first output mode. FIG. 13B is a time chart showing timings of the output timing signal groups LOAD1-Grs and LOAD2-Grs of each of the data drivers 120-1 and 120-p in the second output mode.

[0141] As shown in FIG. 13A and FIG. 13B, in the data driver 120-1, the timing control part 650 supplies to the positive polarity data latch 710 the output timing signal group LOAD1-Grs in which, each time the standard timing signal STD rises, a pulse indicating an output timing appears at a time when a time length Ts30 has elapsed from the time when the standard timing signal STD rises. On the other hand, in the data driver 120-p, the timing control part 650 supplies to the positive polarity data latch 710 the output timing signal group LOAD1-Grs in which, each time the standard timing signal STD rises, a pulse indicating an output timing appears at a time when a time length Ts20 has elapsed from the time when the standard timing signal STD rises. On this occasion, the time length Ts20 is longer than the time length Ts30 in the data driver 120-1.

[0142] As shown in FIG. 13A, in the first output mode, the timing control part 650 of the data driver 120-1 supplies to the negative polarity data latch 720 the output timing signal group LOAD2-Grs in which a pulse indicating an output timing appears at a time when a time length Ts31 has elapsed from each pulse in the output timing signal group LOAD1-Grs. In the first output mode, the timing control part 650 of the data driver 120-p supplies to the negative polarity data latch 720 the output timing signal group LOAD2-Grs in which a pulse indicating an output timing appears at a time when the time length Ts21 has elapsed from each pulse in the output timing signal group LOAD1-Grs.

[0143] That is, compared to the data driver 120-1, the data driver 120-p has a longer wiring length of each gate line wired from a data line group to be driven by the data driver 120-p itself to an output terminal group of the gate driver 110. Thus, a falling (rising) time of the gate selection signal Vgk observed at the display cell 154 connected to the data line group (DLx to DLm) to be driven by the data driver 120-p is longer as compared to the data line group (DL1 to DLi) to be driven by the data driver 120-1.

[0144] Accordingly, in the liquid crystal display 10, whether in the first or second output mode, to follow the falling (rising) time of the gate selection signal Vgk like this, the output timing of a gradation data signal output from the data driver 120-p is controlled to be later than the output timing of a gradation data signal output from the data driver 120-1. Specifically, the time length Ts20 (Ts21) of the output timing signal group LOAD1-Grs (LOAD2-Grs) generated by the data driver 120-p is controlled to be longer than the time length Ts30 (Ts31) of the output timing signal group LOAD1-Grs (LOAD2-Grs) generated by the data driver 120-1.

[0145] Furthermore, the time length Ts31 of a phase shift in a delay direction of a negative polarity gradation data signal with respect to a positive polarity gradation data signal output from the data driver 120-1 is shorter than the time length Ts21 of a phase shift in a delay direction of a negative polarity gradation data signal with respect to a positive polarity gradation data signal output from the data driver 120-p. That is, in the liquid crystal display 10, each data driver 120 is set so that, the shorter the wiring length of the gate line wired from the data line that receives the gradation data signal to the output terminal of the gate driver 110, the shorter the time length of the phase shift of the negative polarity gradation data signal with respect to the positive polarity gradation data signal.

[0146] By adjusting the output timing of the positive polarity and negative polarity gradation data signals described above, in the liquid crystal display 10, a fluctuation in the pixel charging rate in association with a difference in wiring length of the gate line from the output terminal of the gate driver 110 to each pixel is suppressed.

[0147] In the above embodiment, the output mode designation part of the display controller 100 controls each data driver 120-1 to 120-p to be set to the first or second output mode along a fixed or predetermined sequence as shown in FIG. 11 or FIG. 12.

[0148] However, the display controller 100 may control the data drivers 120-1 to 120-p to be set to the first or second output mode for each of a plurality of areas dividing each frame based on the video signal VD.