SYSTEM FOR BULK CAPACITANCE REDUCTION

Abstract

A rectifier for use in a power supply is provided, including a capacitor charge control circuit operable to enable reduction in bulk capacitance.

Claims

1. Self-driven circuitry to be connected in series with a bulk capacitor between first and second output ports of a rectifier, the self-driven circuitry comprising: a thyristor circuit including an anode terminal, a cathode terminal, and a gate terminal, wherein the anode terminal is connected to a first connector of the bulk capacitor that opposes a second connector of the bulk capacitor that is connected to the second output port, wherein the cathode terminal is connected to the first output port; a diode connected antiparallel to the thyristor circuit between the anode terminal and the cathode terminal; and a Zener diode connected parallel to the thyristor circuit between the gate terminal and the anode terminal.

2. The self-driven circuitry of claim 1 wherein the rectifier includes a full diode-bridge.

3. The self-driven circuitry of claim 1 wherein the thyristor circuit includes a silicon-controlled rectifier (SCR), wherein the SCR includes a cathode connected to the cathode terminal, an anode connected to the anode terminal, and a gate connected to the gate terminal.

4. The self-driven circuitry of claim 1 wherein the thyristor circuit includes: an NPN transistor for which an emitter of the NPN transistor is connected to the cathode terminal; a PNP transistor for which an emitter of the PNP transistor is connected to the anode terminal, a collector of the PNP transistor being connected to a gate of the NPN transistor, a gate of the PNP transistor being connected to a collector of the NPN transistor; and a driving resistor connected between the gate of the NPN transistor and the emitter of the NPN transistor.

5. An AC-DC converter comprising: a rectifier stage operable to output DC voltage, the rectifier stage including: the rectifier including input ports to be connected to an AC-voltage source, the rectifier including the first and second output ports to deliver output voltage based on power from the AC-voltage voltage, the bulk capacitor including a first terminal connected to the second output port, and the self-driven circuitry of claim 1 connected between the first output port and a second terminal of the bulk capacitor that opposes the first terminal of the bulk capacitor, wherein the AC-DC converter is configured to deliver the DC voltage over a voltage range between a maximum voltage VMAX and a minimum voltage VMIN.

6. The AC-DC converter of claim 5 wherein the rectifier includes a full diode-bridge.

7. The AC-DC converter of claim 5 wherein: the rectifier stage includes a first stage output and a second stage output; the cathode terminal of the self-driven circuitry is connected to the first stage output; the second output port of the rectifier is connected to the second stage output; and the DC voltage is output from the first and second stage outputs.

8. The AC-DC converter of claim 5 wherein the Zener diode is configured to have a reverse voltage that is substantially equal to the difference VMAX−VMIN.

9. The AC-DC converter of claim 5 wherein an SCR of the thyristor circuit is configured to include an off-state voltage that is larger than the difference VMAX−VMIN, and a gate current ISCR_GATE that is smaller than a reverse breakdown current of the Zener diode IZENER_REVERSE.

10. The AC-DC converter of claim 5 wherein the DC blocking voltage of the diode is configured to be larger than the difference VMAX−VMIN.

11. The AC-DC converter of claim 5 wherein a capacitance value of the bulk capacitor substantially corresponds to $\frac{2P_o{\beta }_{new}}{2\pi f_{\mathrm{line}}\left(V{\mathrm{MAX}}^2-V{\mathrm{MIN}}^2\right)},\mathrm{where}{\beta }_{new}=\pi -2{\cos }^{-1}\left(\frac{V\mathrm{MIN}}{V\mathrm{MAX}}\right),$ and where f.sub.fine is the frequency of the AC-voltage source, and P.sub.0 is the output power of the rectifier.

12. The AC-DC converter of claim 5 is a GaN-based active-clamp flyback AC-DC converter for universal serial bus power delivery charger applications.

13. A capacitor charge controller operable to control charge and discharge of a bulk capacitor, the bulk capacitor including a first capacitor terminal and a second capacitor terminal, the capacitor charge controller comprising: a switching circuit including a first terminal, a second terminal, and an input terminal, wherein the first terminal is operably coupled to a first rectifier output of a rectifier, wherein the second terminal is operably coupled to the first capacitor terminal of the bulk capacitor, wherein the second capacitor terminal of the bulk capacitor is operably coupled to a second rectifier output of the rectifier; a diode connected in parallel to the switching circuit and including a diode anode terminal and a diode cathode terminal, the diode anode terminal being operably coupled to the first terminal of the switching circuit, the diode cathode terminal being operably coupled to the second terminal of the switching circuit; and a Zener diode operably coupled to the input terminal of the switching circuitry and the first capacitor terminal of the bulk capacitor.

14. The capacitor charge controller of claim 13 wherein the switching circuit includes a thyristor with a thyristor anode, a thyristor cathode, and gate input, wherein the thyristor cathode is coupled to the first terminal and the thyristor anode is coupled to the second terminal, wherein the gate input is coupled to the input terminal.

15. The capacitor charge controller of claim 14 wherein the Zener diode controls operation of the thyristor via the gate input.

16. The capacitor charge controller of claim 14 wherein the diode is connected antiparallel to the thyristor.

17. The capacitor charge controller of claim 13 wherein the switching circuit includes: an NPN transistor for which an emitter of the NPN transistor is connected to the cathode terminal; a PNP transistor for which an emitter of the PNP transistor is connected to the anode terminal, a collector of the PNP transistor being connected to a gate of the NPN transistor, a gate of the PNP transistor being connected to a collector of the NPN transistor; and a driving resistor connected between the gate of the NPN transistor and the emitter of the NPN transistor.

18. The capacitor charge controller of claim 14 wherein the capacitor charge controller is self-driven.

19. The capacitor charge controller of claim 13 wherein the capacitor charge controller and the bulk capacitor are provided in series between first and second output ports of a rectifier, wherein the rectifier is operable to receive AC-voltage from an AC power source, and wherein the rectifier, the capacitor charge controller, and the bulk capacitor are operable to output DC-voltage.

20. The capacitor charge controller of claim 19 wherein the Zener diode is configured to have a reverse voltage that is substantially equal to the difference VMAX−VMIN.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 shows a power supply apparatus in accordance with one embodiment.

[0032] FIG. 2 shows a first state of the power supply apparatus of FIG. 1.

[0033] FIG. 3 shows a second state of the power supply apparatus of FIG. 1.

[0034] FIG. 4 shows a third state of the power supply apparatus of FIG. 1.

[0035] FIG. 5 shows a fourth state of the power supply apparatus of FIG. 1.

[0036] FIG. 6 shows a prior art rectification circuit.

[0037] FIG. 7 shows waveforms with respect to the prior rectification circuit of FIG. 6.

[0038] FIG. 8 shows waveforms with respect to the power supply apparatus of FIG. 1.

[0039] FIG. 9 shows an alternative embodiment of a power supply apparatus according to the present disclosure.

[0040] FIG. 10 depicts a method in accordance with one embodiment.

DETAILED DESCRIPTION

[0041] A self-driven circuit with three components, optionally only three, may be provided in one embodiment to automatically realize line-conduction extension and reduce the bulk capacitance. For instance, the self-driven circuit may utilize a self-driven thyristor configuration that includes only three components in total. No extra control circuit may be needed. In this manner, one embodiment according to the present disclosure may provide a simple and inexpensive implementation for reducing bulk capacitance over conventional approaches. It should be understood that the present disclosure is not limited to a three-component configuration, and that alternative embodiments may include greater or fewer components.

[0042] The self-drive circuitry in one embodiment can be used for power supplies or power adapters, such as USB power delivery chargers, USB power delivery wall sockets, LED lighting, etc., and in a variety of fields, such as information technology, communications, electronics, and energy and utilities.

[0043] A power supply apparatus in accordance with one embodiment is depicted in FIG. 1 and generally designated 100. The power supply apparatus 100 is configured to receive power from a power source 150, such as an AC or DC power source. The power supply apparatus 100 may be coupled to load 106. The load 106 may vary from application to application, including for example passive and/or active circuitry. The power supply apparatus 100 in one embodiment may include power supply circuitry 108 that is 1) integral to the power supply apparatus 100 and 2) operable to supply power to the load 106, which may be external to the power supply apparatus 100. The power output from first and second ports 102, 104 of the power supply apparatus 100 may correspond to output from a rectifier 160, which may include rectification circuitry 120 and a bulk capacitor 110. The power supply apparatus 100 in accordance with one embodiment may correspond to an AC/DC converter.

[0044] The power supply circuitry 108 in one embodiment may be pass-through circuitry (e.g., pass-through conductors) operable to couple power output from first and second ports 102, 104 to the load 106. Alternatively, the power supply circuitry 108 may be operable to receive power from the first and second ports 102, 104 and to translate the received power into a form usable by the load 106 according to one or more power specifications. As an example, the power supply circuitry 108 may include a switched mode power supply operable to convert high voltage power (e.g., 150V) output from the first and second ports 102, 104 into a low voltage (e.g., 5V DC) usable by the load 106. Additional examples of power supply circuitry 108 are described in U.S. Application No. 63/299,511 filed on Jan. 14, 2022 and U.S. application Ser. No. 18/095,765 filed on Jan. 11, 2023—the disclosures of which are hereby incorporated by reference in their entirety. As another example, the power supply circuitry 108 may be a GaN-based active-claim flyback (ACF) converter.

[0045] The power supply apparatus 100 in one embodiment may be a USB power supply operable to receive AC power in the form of 120 VAC and to output 5 VDC, and the power output from the first and second ports 102, 104 may correspond to output from the rectifier 160.

[0046] For instance, in the case of the power source 150 being an AC power source, and the power supply circuitry 108 including a switched mode power supply, the switched mode power supply may include switching circuitry operable to convert and regulate DC power for supply to one or more output ports of the power supply apparatus 100. The one or more output ports may be respectively coupled to one or more loads, collectively forming the load 106. For instance, the first output port may be coupled to a first load, and the second output port may be coupled to a second load. The loads may be removably coupled to the ports of the power supply apparatus 100, such as via a connector (e.g., a USB connector).

[0047] In the illustrated embodiment of FIG. 1, the power supply apparatus 100 includes a rectifier 160 operably coupled to the power source 150. The rectifier 160 may include rectification circuitry 120 configured to receive power from the power source 150 and to provide power via a first rectifier port 122 and a second rectifier port 124. In the illustrated embodiment, the rectification circuitry 120 is a full-bridge rectifier with four diodes D1, D2, D3, D4 arranged in a passive rectification configuration—however, it is to be understood that the rectification circuitry 120 may be configured differently depending on the application. As an example, the rectification circuitry 120 may include active rectification circuitry, such as one or more switches that are actively controlled to rectify power received from the power source 150 and output power with respect to the first and second rectifier ports 122, 124.

[0048] The rectifier 160 in the illustrated embodiment includes a capacitor charge controller 130 operable to control charge and discharge of a bulk capacitor 110. The bulk capacitor 110 may include first and second capacitor terminals, where the first capacitor terminal is coupled to the capacitor charge controller 130 and the second capacitor terminal is coupled to one of the first and second ports 102, 104 of the rectifier 160.

[0049] The capacitor charge controller 130 in the illustrated embodiment may be self-driven. For instance, a controller, such as a microcontroller or microprocessor, may be absent from the capacitor charge controller 130. The capacitor charge controller 130 in one embodiment may provide a reliable control circuit that accommodates in rush, surge, and lightning.

[0050] The capacitor charge controller 130 in the illustrated embodiment includes a switching circuit 132, which may be thyristor, such as a silicon controlled rectifier (SCR) device, or circuitry operable to provide similar functionality. The capacitor charge controller 130 may also include a diode 136 connected in parallel to the switching circuit 132, with an anode of the diode 136 coupled to a first terminal of the switching circuit 132 that is also coupled to the first port 102 and a cathode of the diode 136 coupled to a second terminal of the switching circuit 132 that is also coupled to the bulk capacitor 110.

[0051] The parallel arrangement of the diode 136 and the switching circuit 132 may be an anti-parallel configuration, with the devices coupled in parallel but with their polarities reversed. For instance, in the illustrated embodiment, the switching circuit 132 includes an anode, a cathode, and a gate. The anode of the switching circuit 132 may be connected to the cathode of the diode 136, and the cathode of the switching circuit 132 may be connected to the anode of the diode 136. In this configuration, the switching circuit 132 and the diode 136 are in parallel but with their polarities reversed, thereby providing an antiparallel configuration.

[0052] The capacitor charge controller 130 may include a Zener diode 134 coupled to a gate of the switching circuit 132, with the anode of the Zener diode 134 connected to the gate, and the cathode coupled to the anode of the switching circuit 132.

[0053] To provide context, a conventional rectifier is depicted in the illustrating embodiment of FIG. 6, including full-bridge rectification circuitry (e.g., a diode bridge) and a bulk capacitor coupled to the outputs of the full-bridge rectification circuitry. In this conventional configuration, DC bus voltage is output from the diode bridge by rectifying the AC line voltage from a power source (e.g., utility power from wall outlet). The DC bus voltage is mitigated by the bulk capacitor. In this conventional rectifier, the AC line voltage only supplies the output bus voltage shorter than one-quarter AC line period in a half line cycle, until reaching its maximum value. Meanwhile, the capacitor voltage is charged to the same value as maximum AC line voltage. When AC line voltage is lower than capacitor voltage, the bus voltage is maintained by discharging the bulk capacitor. Thus, bulk capacitors with large capacitance are used in conventional full-bridge rectifiers and use a large amount of space, causing a comparably low power density.

[0054] The rectifier 160 in the illustrated embodiment of FIG. 1 enables use of a much smaller capacitance relative to a conventional full-bridge rectifier with little circuitry (e.g., a capacitor charge controller 130) , thereby enabling much higher power density over conventional constructions. For instance, to reduce the bulk capacitance and system volume, a capacitor charge controller 130 main utilize a self-driven thyristor coupled to a rectification circuitry 120. In one embodiment, the capacitor charge controller 130 may include an SCR, a Zener diode, and an anti-parallel diode, in series of the bulk capacitor 110 for its automatic connection and AC line voltage supply extension.

[0055] Turning to the illustrated embodiment of FIGS. 2-5, several operational stages of the capacitor charge controller 130 are shown relative to current flow within the power supply apparatus 100.

[0056] FIG. 2—State 1: Capacitor charging. In the illustrated embodiment of FIG. 2, the bulk capacitor 110 is shown being charged through the anti-parallel diode 136 until the bulk capacitor 110 voltage reaches maximum bus voltage V.sub.bus_max (e.g., the voltage across ports 102, 104).

[0057] FIG. 3—State 2: Line conduction extension. In the illustrated embodiment of FIG. 3, as AC line voltage drops below its maximum, both the Zener diode 134 and the anti-parallel diode 136 are reverse-biased, preserving the capacitor energy from releasing to the load and leaving the line voltage to supply for an extended conduction angle 0. As a result, the AC line voltage supply angle is doubled from 0 to 20 compared to the conventional rectifier shown in FIG. 6.

[0058] FIG. 4—State 3: SCR turn-on transient. In the illustrated embodiment of FIG. 4, when the difference of the capacitor voltage and the AC line voltage reaches the reverse breakdown voltage of the Zener diode 134, which is likely around or equal to V.sub.bus_max−V.sub.bus_min, the breakdown current of the Zener diode 134 turns on the switching circuit 132 (e.g., an SCR), so the bulk capacitor 110 is re-connected into the circuit and starts to supply the bus voltage to the first and second ports 102, 104.

[0059] FIG. 5—State 4: Capacitor discharging. In the illustrated embodiment of FIG. 5, as the capacitor 110 discharges, the Zener diode 134 resumes reverse blocking and the gate current of the switching circuitry 132 deceases, but the switching circuitry 132 stays on due to its latching characteristic. The bulk capacitor 110 may supply power to the load 106 until the capacitor voltage drops below a minimum bus voltage V.sub.bus_min, where the AC line voltage regains control and the switching circuitry 132 turns off naturally with the forward voltage dropping below its minimum holding-current threshold. The AC line voltage starts to re-charge the capacitor 110 through the forwardly biased anti-parallel diode 136, which completes one operation cycle.

[0060] In other words, with respect to the operational stages, the switching circuitry 132 (e.g., an SCR) may be turned on by a threshold-setting Zener diode 134 at V.sub.bus_max−V.sub.bus_min and is turned off naturally after AC line voltage takes over, realizing an automatic connection of the bulk capacitor 110. Unlike employing active switches to control a connection of the bulk capacitor 110, the capacitor charge controller 130 may not require additional sensing, control logic, or drivers to achieve operation, enabling a robust, high-density, and low-cost solution.

[0061] Turning to the illustrated embodiment of FIG. 8, the four operational stages are depicted relative to bus voltage and the AC input voltage. For context, these operational stages are described relative to operation shown in FIG. 7 with respect to the conventional rectifier in FIG. 6.

[0062] FIG. 8 shows bus voltage waveforms for the power supply apparatus 100 in the illustrated embodiment of FIGS. 1-5, and FIG. 7 shows bus voltage waveforms for the conventional rectifier of FIG. 6. The waveforms in FIGS. 7 and 8 include the rectified AC line voltage shown as rectified sinusoidal waveforms with a 2π period, with both positive and negative cycles rectified to positive voltage, and with portions of the rectified sinusoidal waveforms shown overlapping the bus voltage in the region between V.sub.bus_max and V.sub.bus_min. The bus voltages waveforms are shown in the region between V.sub.bus_max and V.sub.bus_min.

[0063] With respect to operational states (e.g., stages or modes) of the power supply apparatus 100, the bus voltage waveforms depicted in FIG. 8 overlap the rectified AC line voltage waveforms in states 1 and 2.

[0064] In the illustrated embodiment, V.sub.bus_max is equal to the maximum AC line voltage, and V.sub.bus_min, which is adjustable by choosing a Zener diode 134 with a different reverse breakdown voltage, and may be decided by the input voltage requirement of the follow-up circuits, such as the power supply circuitry 108 and/or the load 106.

[0065] In the conventional construction of FIGS. 6 and 7, the AC line voltage supply angle is θ and the bulk capacitor discharging angle β.sub.con is calculated in eq. 1. The capacitance for such a conventional full-bridge rectifier is calculated in equation 2, where Po is the output power of the rectifier and f.sub.line is the AC line frequency.

[00002]$\begin{array}{cc}{\beta }_{con}=\pi -\theta =\pi -{\cos }^{-1}\left(\frac{v_{\mathrm{bus\_min}}}{v_{\mathrm{bus\_max}}}\right)& \mathrm{EQUATION}1\end{array}$$\begin{array}{cc}{C}_{con}=\frac{2P_0{\beta }_{con}}{2^{\pi }{f}_{\mathrm{line}}\left(v_{\mathrm{bus\_max}}^2-v_{\mathrm{bus\_min}}^2\right)}& \mathrm{EQUATION}2\end{array}$

[0066] From equations 1 and 2 for conventional rectifiers, the capacitance is proportional to the angle β.sub.con and inversely proportional to AC line supply angle.

[0067] On the other hand, the rectifier 160 in one embodiment according to the present disclosure may enable decreasing the capacitor discharging angle by increasing the AC line supply angle, providing smaller capacitance and capacitor size under the same voltage rating over the conventional construction. In one embodiment, the AC line voltage supply angle may be extended to 2θ due at least in part to the automatic disconnection of the capacitor 110 realized by the charge control circuitry 130 during the second θ so the bulk capacitor discharging angle is reduced to as shown in eq. 3 and the capacitance can be calculated according to eq. 4.

[00003]$\begin{array}{cc}{C}_{con}=\frac{2P_0{\beta }_{con}}{2^{\pi }{f}_{\mathrm{line}}\left(v_{\mathrm{bus\_max}}^2-v_{\mathrm{bus\_min}}^2\right)}& \mathrm{EQUATION}3\end{array}$$\begin{array}{cc}{C}_{new}=\frac{2P_0{\beta }_{new}}{2^{\pi }{f}_{\mathrm{line}}\left(v_{\mathrm{bus\_max}}^2-v_{\mathrm{bus\_min}}^2\right)}& \mathrm{EQUATION}4\end{array}$

[0068] As can be seen from eqs. 3 and 4, the capacitance of the bulk capacitor 110 is less than the capacitance for the conventional rectifier circuitry. The ratio η of C.sub.con to C can be calculated as follows:

[00004]$\begin{array}{cc}\eta =\frac{C_{new}}{C_{con}}=\frac{\pi -2\theta }{\pi -\theta }& \mathrm{EQUATION}5\end{array}$

[0069] The capacitance ratio versus the ratio of the two bus voltage limitations (e.g., V.sub.bus_max and V.sub.bus_min) is a positive-coefficient relationship. The ratio of the capacitances goes up when the ratio of bus voltage limitations increases, which indicates that more capacitance reduction can be achieved by a larger difference between V.sub.bus_max and V.sub.bus_min. For instance, as V.sub.bus_max approaches or equals the sinusoidal peak of input AC voltage (ignoring voltage drop on the diode-bridge), the lower voltage limit V.sub.bus_min may be selected to be close to or at the absolute minimum in order to enhance or maximize the advantage of the capacitance reduction. However, a high bus voltage limitation ratio from the rectifier 160 may undermine the efficiency of the rectifier 160 and a subsequent converter stage (e.g., the power supply circuitry 108). Therefore, the value of V.sub.bus_min may be selected based on a trade-off between capacitor size and overall efficiency for high-density AC-DC converter applications.

[0070] Note that several portions of the analysis described herein may assume full-load conditions. Under light-load condition, the slower slew-rate of capacitor discharging may slightly increase the capacitor discharging angle β in state 4 and potentially shrink line conduction angle θ in state 1. However, the load condition may not substantially affect the operations and component ratings as V.sub.bus_min is considered constant.

[0071] The voltages and currents of several components of the rectifier 160 according to one embodiment are summarized in Table I. The bus voltage and the capacitor voltage supplying the load as a function of the instantaneous angle a in a half line cycle are given by eqs. 6 and 7, from which the blocking voltage for the switching circuit 132, the anti-parallel diode 136, and the Zener diode 134 can be derived and equal to V.sub.bus max−V.sub.bus_min. Practically, this blocking voltage may be determined in the range of tens of volts where a wide range of low-voltage selections are available for high performance and low-cost components. The equations of current for the input diode bridge (e.g., rectification circuitry 120) as i.sub.BD, the capacitor 110 as i.sub.cap, the anti-parallel diode 136 as i.sub.D, and the switching circuit 132 as i.sub.SCR are provided in eqs. 8-11. for each state to evaluate the power loss performance. Based on equations with respect to one embodiment of the present disclosure, a reduction in RMS currents of both the capacitor 110 and the rectification circuitry 120 in the range of bus voltage limitation ratios can be achieved, thereby saving power losses compared with conventional rectifiers. These power loss savings may offset any additional conduction losses on the switching circuit 132 and the anti-parallel diode 136 caused by i.sub.SCR and i.sub.D.

[0072] An alternative embodiment of the power supply apparatus is depicted in FIG. 9 and generally designated 200. The power supply apparatus 200 is similar to the power supply apparatus 100 described in conjunction with FIG. 1, with several exceptions. For instance, the power supply apparatus 200 includes a power source 250, rectification circuitry 220 with first and second rectification ports 222, 224, first and second ports 202, 204, and a bulk capacitor 210, similar respectively to the power source 150, the rectification circuitry 120, the first and second ports 102, 104, and the bulk capacitor 110. This circuitry of the power supply apparatus 200, other than the power source 250, may form a rectifier 260 that can be coupled to additional power supply circuitry and/or a load. For instance, for purposes of disclosure, a load and power supply circuitry, similar to the load 106 and the power supply circuitry 108, are absent from the embodiment depicted in FIG. 9. However, it is to be understood that the first and second ports 202, 204 may be coupled to power supply circuitry and a load similar to load 106 in the power supply circuitry 108 described herein.

[0073] The power supply apparatus 200 in the illustrated embodiment includes charge control circuitry 230 that operates in a manner similar to the charge control circuitry 130, but incorporating a differently configured switching circuit 232. The charge control circuitry 230 includes a Zener diode 234 and an antiparallel diode 236, similar to the Zener diode 134 and the antiparallel diode 136.

[0074] The switching circuit 232 in the illustrated environment includes an NPN transistor 242 for which an emitter of the NPN transistor 242 is connected to and at least in part forms a cathode terminal of the switching circuit 232. The switching circuitry 232 may include PNP transistor 244 for which an emitter of the PNP transistor 244 is connected to and at least in part forms an anode terminal of the switching circuit 232. A collector of the PNP transistor 244 may be connected to a gate of the NPN transistor 242, and a gate of the PNP transistor 244 may be connected to a collector of the NPN transistor 242. The switching circuit 232 may include a driving resistor 246 connected between the gate of the NPN transistor 242 and the emitter of the NPN transistor 242.

[0075] The switching circuit 232 in the illustrated embodiment may replace the SCR of the switching circuitry 132 in FIG. 1 with two back-to-back connected transistors and a driving resistor. This configuration may be less expensive than the SCR-based configuration and may provide additional design freedom.

[0076] A method of producing a rectifier according to the present disclosure is shown in FIG. 10 and generally designated 1000. The method includes determining the output power and bus voltage limitations based on the power requirements or targeted power density. Step 1002. The method may also include calculate θ and capacitance according to eqs. 3 and 4, and selecting capacitor 110 with a nearest value of capacitance to the calculation. Step 1004.

[0077] The method may also include selecting a Zener diode 134. The reverse breakdown voltage for Zener diode 134 may be substantially equal to the difference of the two bus voltage limitations V.sub.bus_max−V.sub.bus_min. Step 1006.

[0078] The method may include selecting an SCR or switching circuit 132 or switching circuit 232. The off-state voltage of the switching circuit 132 and the two transistors (NPN and PNP) in circuit 232 may be larger than the difference of the bus voltage limitations. And the gate current may be smaller than the reverse breakdown current generated by the Zener diode 134. Step 1008.

[0079] The method may include selecting an anti-parallel diode 136. The DC blocking voltage for the anti-parallel diode 136 may be larger than the difference of the bus voltage limitations. Step 1010.

[0080] Directional terms, such as “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “inner,” “inwardly,” “outer” and “outwardly,” are used to assist in describing the invention based on the orientation of the embodiments shown in the illustrations. The use of directional terms should not be interpreted to limit the invention to any specific orientation(s).

[0081] The above description is that of current embodiments of the invention. Various alterations and changes can be made without departing from the spirit and broader aspects of the invention as defined in the appended claims, which are to be interpreted in accordance with the principles of patent law including the doctrine of equivalents. This disclosure is presented for illustrative purposes and should not be interpreted as an exhaustive description of all embodiments of the invention or to limit the scope of the claims to the specific elements illustrated or described in connection with these embodiments. For example, and without limitation, any individual element(s) of the described invention may be replaced by alternative elements that provide substantially similar functionality or otherwise provide adequate operation. This includes, for example, presently known alternative elements, such as those that might be currently known to one skilled in the art, and alternative elements that may be developed in the future, such as those that one skilled in the art might, upon development, recognize as an alternative. Further, the disclosed embodiments include a plurality of features that are described in concert and that might cooperatively provide a collection of benefits. The present invention is not limited to only those embodiments that include all of these features or that provide all of the stated benefits, except to the extent otherwise expressly set forth in the issued claims. Any reference to claim elements in the singular, for example, using the articles “a,” “an,” “the” or “said,” is not to be construed as limiting the element to the singular.