Abstract
An integrated, quantized inductor, comprising a plurality of identical inductor sections, is provided for multiple applications on the chip. The inductor section represents one turn and includes two stacked metal layers with identical area and configuration, separated by dielectric layers, winding around the insulated ferromagnetic core, and interconnected by via. Power transformer, having a primary winding and multiple secondary windings comprised of a plurality of identical inductor sections and a shielded common ferromagnetic core ring, placed outside of the active chip area between the seal ring and pad-ring enhanced area. Inside of active chip area, in proximity to the related linear RF components are placed sensitive inductors, balun-transformers, resonator, separately protected by EM guard rings, wherein one node is open, and the second one is tied to the ground. The fabrication is compatible with integrated circuits manufacturing.
Claims
1. A chip with an on-chip quantized inductor comprising a plurality of inductor sections, an insulated ferromagnetic core, an electromagnetic (EN) guard ring, dummy inductors, and a metallic envelope, wherein each of the plurality inductor sections represents one turn and includes two patterned, insulated, and stacked metal layers with identical area and configuration, winding around the insulated ferromagnetic core, interconnected by a stacked via, and protected from EM impact by the EM guard ring and shielded by the metallic envelope.
2. A plurality of the on-chip quantized inductors of claim 1 as parts of an on-chip alternative current A( ) power transformer, having a primary winding and multiple secondary windings, comprising the common insulated ferromagnetic core, shielded by the metallic envelope, placed external to an active chip area between a seal ring and a pad-ring enhanced area, wherein the coupling coefficient can be adjusted by changing the number of the inductor sections during physical design, extraction netlist from a layout view, and simulation of the AC power transformer.
3. The on-chip quantized inductor of claim 1, as part of a functional cell, wherein the functional cell is placed inside of an active chip area in proximity to related sensitive linear active and passive components and along with sensitive inductors, separated by the dummy inductors, further wherein the functional cell comprising the insulated ferromagnetic core, the EM guard ring and the common metallic envelope, further wherein the inductance of the sensitive inductors can be adjusted by changing the number of inductor sections during physical design, after extraction netlist from layout view, and stimulation of the functional cell.
4. The on-chip quantized inductor of claim 1, wherein a first node of the quantized inductor is open and a second node is tied to the ground and serves as an EM antenna.
5. The on-chip quantized inductor of claim 1 as part of an on-chip resonator comprising a resistor, and parallel connected metal-oxide-metal (MON) capacitor sections, each of the parallel connected MOM capacitor sections being placed on the tops of each of the inductor sections, wherein a total capacitance value can be adjusted during physical design, extraction net list from a layout view, and simulation of the on-chip resonator in order to achieve the best Q-factor.
6. The on-chip quantized inductor of claim 1, wherein the ferromagnetic core comprises at least one insulated and shielded ferromagnetic layer, the at least one insulated and shielded ferromagnetic layer being fabricated using at least one of CMOS, BICMOS, BCD, MEMS and FINFET technologies with additional lithography processing and thin film physical vapor deposition including one or more of the following ferromagnetic materials: Fe20, FeOIFe2O3, Ni OexO3 and CuOFe201.
7. The on-chip quantized inductor of claim 1, placed inside of an on-chip balanced-to-unbalanced device (balun) in proximity to related sensitive components, further wherein the balun comprising a primary winding and a secondary winding, protected from internal and external EM impact by the EM guard rings and the common metallic envelope.
8. The on-chip quantized inductor of claim 1, wherein the metallic envelope comprises a bottom horizontal metal layer, a top horizontal metal layer and a lateral vertical metallic layer, further wherein the lateral vertical metallic layer is formed from horizontally and vertically stacked vias; the bottom horizontal metal layer, the top horizontal metal layer, and the lateral vertical metallic layer are lithography formed using multiple consecutive vertical deposited metals, the horizontally and vertically stacked vias and multiple horizontally and vertically stacked silicone dioxide layers are fabricated during conventional integrated circuit processing.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The accompanying drawings incorporated in and forming a part of the specification, illustrate the present invention, and together with the description serve to explain the principles of the invention. In the drawings:
(2) FIG. 1 illustrates the first preferred embodiment of the present invention, showing a plan view of the chip with quantized inductors, AC power transformer, placed outside of active chip aria, and balun transformer, inductors and resonators, placed inside of chip area;
(3) FIG. 2 illustrates the floor planning of one inductor section, composed from two identical metal layers, via and a portion of ferromagnetic core;
(4) FIG. 3 illustrates the vertical cross section view of inductor section;
(5) FIG. 4 illustrate the second preferred embodiment of a quantized inductor, composed from inductor sections, ferromagnetic core, metallic envelope and input-output metal connection.
(6) FIG. 5 illustrates the schematic of a complete 1.5 GHz, 8 mW single-ended low noise amplifier (LNA);
(7) FIG. 6 illustrates the third preferred embodiment of the present invention, showing layout floor planning of a complete 1.5 GHz, 8 mW single-ended LNA with EM guard rings on the chip;
(8) FIG. 7 illustrates the schematic of differential amplifier with balun;
(9) FIG. 8 illustrates the fourth preferred embodiment of the present invention, showing layout floor planning of differential amplifier with balun and protecting by EM guard rings on the chip;
(10) FIG. 9 illustrates the schematic model of on-chip resonator;
(11) FIG. 10 illustrates layout floor planning of one capacitor section (pitch), which will be placed on the top of inductor section in quantized resonator;
(12) FIG. 11 illustrates the fifth preferred embodiment of the present invention, showing layout floor planning of the resonator with EM guard ring;
(13) FIG. 12 illustrates an example of prior art, showing partial planar chip view of a differential amplifier with balun and inductors.
DETAILED DESCRIPTION
(14) Turning now to the drawings.
(15) FIG. 1 is a general plan view of the chip 101 with on-chip quantized AC power transformer, having a primary winding 108 and multiple secondary winding 109, a common ferromagnetic core ring 103, shielding metallic envelope 104 and placed out of active chip area 105 between seal ring 102 and pad-ring enhanced area 106. Inside of active chip area 107 proximity to related sensitive linear active components are placed differential amplifier with balun, sensitive inductors 111, LNA 113 and resonator 112, wherein inductors are protected from inside and outside electromagnetic (EM) impact by EM guard rings. All inductors in this application are composed from identical layout of inductor sections 110.
(16) FIG. 2 illustrates the floor planning of one inductor section 206, composed from two identical metal layers 201 and 202, winding around of ferromagnetic core 205, and interconnected by via 203; FIG. 3 illustrates the vertical cross section view of inductor section, were ferromagnetic core 305 is insulated by SiO.sub.2 or Si.sub.3N.sub.4 layers 306, shielded by bottom 310 and top 314 metal layers, interconnected by via 313. Inductor sections are composed from identical shapes of metal 301 and 302, interconnected by via 303. Input and output of inductor are implemented on top metal layer 315 interconnected by via 311 placed on respective via 303, through window 312 in metal layer 314. Inductor is fabricated using CMOS, BICMOS, BCD, FINFET or MEMS processing. In order to minimize EM impact of inductors to components 307, 308 and M1, M2, M3, M4, M5, M6, M7 routings 309 it is required to start implementation of bottom shielding metal layer 310 up to M8.
(17) FIG. 4 illustrate the second preferred embodiment of a quantized inductor, composed from inductor sections 406, each formed from two identical shapes 401 and 402, ferromagnetic core 405, via 403, shielding metal layers 410, 414, 413 and input-output metal connection 415 by via 411 on respective via 403, through window 412 in metal layer 414.
(18) FIG. 5 illustrates the schematic of a complete 1.5 GHz, 8 mW single-ended low noise amplifier (LNA), as an example for physical implementation of the present invention.
(19) FIG. 6 illustrates the third preferred embodiment of present invention showing layout floor planning of a complete 1.5 GHz, 8 mW single-ended LNA with EM guard rings on the chip were 616 and 617 represents inside and outside EM guard rings. 618, 619 and 620 represents quantized inductors respectively 7 nH, 21 nH and 1.4 nH. There one inductor section has the value of L=0.7 nH. 622 represents two parts of EM guard sections with two inductors-antenna each, tied to the ground. Inside of EM guard rings 621 are placed the active and passive components of LNA with symmetry and balancing considerations regarding to the noise and power dissipation.
(20) FIG. 7 illustrates the schematic of differential amplifier with balun as an example for physical design implementation according to the present invention.
(21) FIG. 8 illustrates the fourth preferred embodiment of present invention, showing layout floor planning of differential amplifier with balun and separated EM guard rings 822, 823 and common guard ring 824 on the chip. In comparison with prior art showing in FIG. 12 floor planning takes less rooms, and current flow, symmetry, balancing and insulation are better.
(22) FIG. 9 illustrates the schematic model of on-chip resonator as an example for physical design implementation according to the present invention.
(23) FIG. 10 illustrates layout floor planning of one capacitor section (pitch), which will be placed on the top of inductor section in quantized resonator.
(24) FIG. 11. illustrates the fifths preferred embodiment of present invention, showing layout floor planning of resonator with EM guard ring were 111 represent ferromagnetic core, 112output resistor, parallel connected to the quantized capacitor, 113shows two peripheral adjustable capacitor sections, 114 represent the metal ring connected to the ground and to the first node of guard ring quantized inductor, 115 represent the open second node of guard ring quantized inductor which serves as EM antenna.
(25) FIG. 12. Illustrates an example of prior art showing partial planar chip view of a differential amplifier with balun and inductors.
