Optoelectronic semiconductor chip and method for producing same

Abstract

An optoelectronic semiconductor chip (10) is specified, comprising a p-type semiconductor region (4), an n-type semiconductor region (6), and an active layer arranged between the p-type semiconductor region (4) and the n-type semiconductor region (6), said active layer being designed as a multiple quantum well structure (5), wherein the multiple quantum well structure (5) comprises quantum well layers (53) and barrier layers (51), wherein the barrier layers (51) are doped, and wherein undoped intermediate layers (52, 54) are arranged between the quantum well layers (53) and the barrier layers (51). Furthermore, a method for producing the optoelectronic semiconductor chip (10) is specified.

Claims

1. A method for producing an optoelectronic semiconductor chip, comprising an epitaxial growth of a semiconductor layer sequence having a p-type semiconductor region, an n-type semiconductor region and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, said active layer being in the form of a multi-quantum-well structure, wherein the multi-quantum-well structure comprises quantum-well layers and barrier layers, the barrier layers are doped, undoped intermediate layers are arranged between the quantum-well layers and the barrier layers, and the undoped intermediate layers are grown at a higher growth temperature than the doped barrier layers, wherein the barrier layers comprise Al.sub.m1Ga.sub.1-m1As.sub.n1P.sub.1-n1 with On11, the undoped intermediate layers comprise Al.sub.m2Ga.sub.1-m2As.sub.n2P.sub.1-n2 with Om21 and On21, and wherein |m1m2|0.1 and |n1n2|0.1.

2. The method according to claim 1, wherein the growth temperature during the growth of the undoped intermediate layers is at least 650 C.

3. The method according to claim 1, wherein the growth temperature during the growth of the barrier layers is less than 600 C.

4. An optoelectronic semiconductor chip, comprising: a p-type semiconductor region, an n-type semiconductor region, an active layer arranged between the p-type semiconductor region and the n-type semiconductor region, said active layer being in the form of a multi-quantum-well structure, wherein the multi-quantum-well structure comprises quantum-well layers and barrier layers, the barrier layers are doped, and undoped intermediate layers are arranged between the quantum-well layers and the barrier layers, wherein the barrier layers comprise Al.sub.m1Ga.sub.1-m1As.sub.n1P.sub.1-n1 with 0m11 and 0n11, the undoped intermediate layers comprise Al.sub.m2Ga.sub.1-m2As.sub.n2P.sub.1-n2 with 0m21 and 0n21, and wherein |m1m2|0.1 and |n1n2|0.1.

5. The optoelectronic semiconductor chip according to claim 4, wherein the quantum-well layers each adjoin undoped intermediate layers on both sides.

6. The optoelectronic semiconductor chip according to claim 4, wherein the undoped intermediate layers are between 1 nm and 10 nm thick.

7. The optoelectronic semiconductor chip according to claim 4, wherein the undoped intermediate layers are less than 3 nm thick.

8. The optoelectronic semiconductor chip according to claim 4, wherein the undoped intermediate layers are thinner than the barrier layers.

9. The optoelectronic semiconductor chip according to claim 4, wherein the quantum-well layers comprise In.sub.xAl.sub.yGa.sub.1-x-yAs with 0x1, 0y1 and x+y1.

10. The optoelectronic semiconductor chip according to claim 4, wherein n2=1.

11. The optoelectronic semiconductor chip according to claim 4, wherein an electronic band gap of the undoped intermediate layers differs by no more than 0.1 eV from the electronic band gap of the barrier layers.

12. The optoelectronic semiconductor chip according to claim 4, wherein the barrier layers have the same material composition as the undoped intermediate layers, apart from a dopant.

13. The optoelectronic semiconductor chip according to claim 4, wherein the optoelectronic semiconductor chip is a light-emitting diode emitting in the infrared range of the spectrum.

Description

(1) The figures show the following:

(2) FIG. 1 shows a schematic illustration of a cross-section through an optoelectronic semiconductor chip according to an exemplary embodiment,

(3) FIG. 2 shows a bar diagram of the brightness I.sub.e of the emitted radiation for various thicknesses d.sub.IL of the intermediate layers and

(4) FIG. 3 shows a bar diagram of the rise times t.sub.rise and the fall times t.sub.fall of the emitted radiation in pulsed mode for various thicknesses d.sub.IL of the intermediate layers.

(5) The components illustrated and the size ratios to one another of the components should not be regarded as being to scale.

(6) The optoelectronic semiconductor chip 10 according to one exemplary embodiment illustrated in FIG. 1 is an LED chip comprising a p-type semiconductor region 4, an n-type semiconductor region 6 and an active layer 5 capable of emitting radiation, which is arranged between the p-type semiconductor region 4 and the n-type semiconductor region 6. The LED chip 10 is preferably an LED chip emitting in the infrared range of the spectrum.

(7) In the exemplary embodiment of the optoelectronic semiconductor chip 10, the chip is a so-called thin-film semiconductor chip, from which a growth substrate originally used for the epitaxial growth of the semiconductor layers 4, 5, 6 has been removed and instead, the semiconductor layer sequence has been connected by means of a connecting layer 2, in particular a solder layer, to a carrier substrate 1 which is different from the growth substrate.

(8) In a thin-film LED chip 10 of this type, the p-type semiconductor region 4 generally faces towards the carrier substrate 1. Between the p-type semiconductor region 4 and the carrier substrate 1, a mirror layer 3 is advantageously arranged, which advantageously deflects radiation emitted towards the carrier substrate 1 towards a radiation exit surface 9 of the optoelectronic semiconductor chip. The mirror layer 3 is e.g. a metal layer, which contains Ag, Al or Au.

(9) For the electrical contacting of the optoelectronic semiconductor chip 10, e.g. a first contact layer 7 can be provided on a rear side of the carrier substrate 1 and a second contact layer 8 on a subregion of the radiation exit surface 9.

(10) The p-type semiconductor region 4 and the n-type semiconductor region 6 can each be composed of multiple sublayers and do not necessarily have to consist exclusively of p-doped layers or n-doped layers but can also comprise e.g. one or more undoped layers.

(11) As an alternative to the exemplary embodiment illustrated, the optoelectronic semiconductor chip 10 could also have an opposite polarity, i.e. the n-type semiconductor region 6 could face towards a substrate and the p-type semiconductor region 4 towards a radiation exit surface 9 of the optoelectronic semiconductor chip (not illustrated). This is generally the case in optoelectronic semiconductor chips in which the growth substrate used for the epitaxial growth of the semiconductor layers is not removed, since the n-type semiconductor region is generally grown first on the growth substrate.

(12) The active layer of the optoelectronic semiconductor chip 10 provided to emit radiation is in the form of a multi-quantum-well structure 5. The multi-quantum-well structure 5 comprises a plurality of alternately arranged quantum-well layers 53 and barrier layers 51. The quantum-well layers 53 have a band gap E.sub.QW und the barrier layers 53 have a band gap E.sub.B>E.sub.QW. The multi-quantum-well structure 5 is in particular a periodic layer sequence comprising a number N of periods, wherein N is preferably between 2 and 50. For example, the multi-quantum-well structure can comprise twelve periods.

(13) The barrier layers 51 in the multi-quantum-well structure 5 are doped. The dopant concentration in the barrier layers 51 is advantageously at least 1*10.sup.18 cm.sup.3, preferably at least 1*10.sup.19 cm.sup.3, e.g. for instance 3*10.sup.19 cm.sup.3. The doping of the barrier layers 51 has the advantage that comparatively short switching times can be achieved in the optoelectronic semiconductor chip.

(14) Between the quantum-well layers 53 and the barrier layers 51, undoped intermediate layers 52, 54 are advantageously arranged. A period of the quantum-well structure can consist of e.g. a doped barrier layer 51, a first undoped intermediate layer 52, a quantum-well layer 53 and a second undoped intermediate layer 54, wherein each quantum-well layer 53 adjoins an undoped intermediate layer 52, 54 on both sides. The quantum-well layer 53 therefore advantageously has no interface with a doped barrier layer 51. This has the advantage that electrons in the quantum-well layers 53 do not come into direct contact with the ionized dopant atoms of the barrier layers 51. More precisely, an overlap of the electron wave function with the wave function of the ionized dopant atoms in the barrier layers 51 is reduced. In this way, non-radiative recombinations of electrons are reduced and the efficiency of the optoelectronic semiconductor chip 10 is thus increased.

(15) The undoped intermediate layers 52, 54 preferably have a thickness of at least 1 nm and no more than 10 nm, particularly preferably no more than 3 nm. The undoped intermediate layers 52, 54 are preferably thinner than the barrier layers 51 and/or the quantum-well layers 53. The short switching times that are made possible by the doping of the barrier layers are preferably not substantially affected by the undoped intermediate layers, which are thin compared to the barrier layers.

(16) In the exemplary embodiment illustrated in FIG. 1, for example, the barrier layer 51 can have a thickness of 8.4 nm, the first undoped intermediate layer 52 a thickness of 1.4 nm, the quantum-well layer 53 a thickness of 4.4 nm and the second undoped intermediate layer 54 a thickness of 1.4 nm.

(17) During the production of the multi-quantum-well structure 5, the barrier layers 51 are preferably grown at a lower growth temperature than the undoped intermediate layers 52, 54 and the quantum-well layers 53. The growth of the barrier layers 51 takes place at a growth temperature of preferably less than 600 C., e.g. at about 575 C. The undoped intermediate layers 52, 54 and the quantum-well layers 53 are preferably grown at a growth temperature of more than 650 C., e.g. at about 665 C. As a result of the higher growth temperature during the growth of the undoped intermediate layers 52, 54 and the quantum-well layers 53, the incorporation of foreign atoms (impurities) is advantageously kept low. Since impurities can form centers for non-radiative recombinations, non-radiative recombinations are further reduced by a reduction of impurities and thus the efficiency of the optoelectronic semiconductor chip is increased further.

(18) The band gaps of the semiconductor materials of the quantum-well layers 53, the barrier layers 51 and the undoped intermediate layers 52, 54 can in particular be adjusted by varying the aluminum content and/or the indium content in the semiconductor material. For example, the quantum-well layers and barrier layers can comprise semiconductor materials with the composition In.sub.xAl.sub.yGa.sub.1-x-yAs or In.sub.xAl.sub.yGa.sub.1-x-yAs.sub.zP.sub.1-z with 0x1, 0y1, x+y1 and 0z1. In these types of semiconductors, the band gap increases with increasing aluminum content y and decreases with increasing indium content x. In the exemplary embodiment of FIG. 1, for example, the quantum-well layers 53 comprise Ga.sub.0.92In.sub.0.08As, the barrier layers 51 comprise Al.sub.0.23Ga.sub.0.77As.sub.0.94P.sub.0.06 and the undoped intermediate layers 52, 54 comprise Al.sub.0.28Ga.sub.0.72As.

(19) The barrier layers 51 and the undoped intermediate layers 52, 54 have substantially the same material composition. The barrier layers 51 preferably comprise Al.sub.m1Ga.sub.1-m1As.sub.n1P.sub.1-n1 with 0m11 and 0n11. A dopant of the barrier layers 51, such as for example C, can be ignored here since the concentration of the dopant is typically orders of magnitude lower than that of the other material components. For example, the barrier layers can have a dopant concentration of about 2*10.sup.19 cm.sup.3.

(20) The undoped intermediate layers 52, 54 preferably comprise Al.sub.m2Ga.sub.1-m2As.sub.n2P.sub.1-n2 with 0m21 and 0n21. Preferably, n2=1, i.e. the undoped intermediate layers have no phosphorus content. The following preferably applies here: |m1m2|0.1, particularly preferably |m1m2|0.05. Furthermore, the following preferably applies: |n1n2|0.1, particularly preferably |n1n2|0.05. Since the material compositions of the barrier layers 51 and the undoped intermediate layers 52, 54 do not differ substantially from one another, the electronic band gap E.sub.B of the barrier layers also does not differ substantially from the electronic band gap E.sub.IL, of the undoped intermediate layers. The following preferably applies: |E.sub.BE.sub.IL|0.1 eV, particularly preferably |E.sub.BE.sub.IL|0.05 eV. The energetic properties of the undoped intermediate layers 52, 54 therefore correspond substantially to the barrier layers 51.

(21) FIG. 2 shows a bar diagram, which shows the brightness of the emitted radiation I.sub.e (in arbitrary units) for exemplary embodiments of optoelectronic semiconductor chips with various layer thicknesses d.sub.IL of the undoped intermediate layers. The bar labelled 0 nm relates to an exemplary embodiment which is not according to the invention, in which no undoped intermediate layers are arranged between the quantum-well layers and the barrier layers. The bar labelled ref relates to a further exemplary embodiment which is not according to the invention, in which the barrier layers are undoped and no undoped intermediate layers are arranged between the quantum-well layers and the barrier layers.

(22) It is shown that, for the layer thicknesses cited, the brightness of the emitted radiation increases with the thickness of the undoped intermediate layers. This can be attributed in particular to the reduction in non-radiative recombinations of charge carriers.

(23) In FIG. 3, a further bar diagram is shown which shows the rise time t.sub.rise (left-hand bar) and the fall time t.sub.fall (right-hand bar) when the optoelectronic semiconductor chips are operated in pulsed mode with a current strength of 1 A as a function of the layer thickness d.sub.IL of the undoped intermediate layers. It is shown that the switching times t.sub.rise and t.sub.fall increase with increasing layer thickness of the undoped intermediate layers. The increase in switching times is only very low with low layer thicknesses, however, so that comparatively short switching times can be achieved despite the undoped intermediate layers. Furthermore, FIG. 3 shows that the switching times are significantly greater in the comparative example labelled ref, in which the barrier layers are undoped.

(24) The description with the aid of the exemplary embodiments does not limit the invention thereto. Rather, the invention comprises any new feature and any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination is not itself explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

(25) 1 Carrier substrate 2 Connecting layer 3 Mirror layer 4 P-type semiconductor region 5 Multi-quantum-well structure 6 N-type semiconductor region 7 First contact layer 8 Second contact layer 9 Radiation exit surface 10 Optoelectronic semiconductor chip 51 Barrier layer 52 Intermediate layer 53 Quantum-well layer 54 Intermediate layer 52c Sublayer of the barrier layer 53 Intermediate layer