Ring oscillator based all-digital Bluetooth low energy transmitter

Abstract

A Bluetooth Low-Energy (BLE) transmitter is presented for used in ultra-low-power radios in short range IoT applications. The power consumption of state-of-the-art BLE transmitter has been limited by the relatively power-hungry local oscillator due to the use of LC oscillators for superior phase noise performance. This disclosure addresses this issue by analyzing the phase noise limit of a BLE TX and proposes a ring oscillator-based solution for power and cost savings. The proposed transmitter features: 1) a wideband all-digital phase locked loop (ADPLL) featuring an f.sub.RF/4 RO, with an embedded 5-bit TDC; 2) a 4 frequency edge combiner to generate the 2.4 GHz signal; and 3) a switch-capacitor digital PA optimized for high efficiency at low transmit power levels. These not only help reduce the power consumption and improve phase noise performance, but also enhance the transmitter efficiency for short range applications.

Claims

1. A frequency synthesizer, comprising: a modulation controller configured to receive a reference signal from a reference source and operates to frequency modulate the reference signal in accordance with a frequency control word; a phase-locked loop circuit interfaced with the modulation controller to receive a frequency modulated input signal, wherein the phase-locked loop circuit includes a ring oscillator with an embedded time-to-digital converter circuit; and a frequency multiplier circuit configured to receive a frequency modulated output signal from the phase-locked loop circuit and increase frequency of the frequency modulated output signal by a multiplier.

2. The frequency synthesizer of claim 1 wherein the frequency multiplier circuit is further defined as a windowed edge combiner.

3. The frequency synthesizer of claim 2 wherein the time-to-digital converter circuit and the windowed edge combiner are configured to concurrently receive phases of the ring oscillator.

4. The frequency synthesizer of claim 1 wherein the time-to-digital converter circuit directly samples phases of the ring oscillator without delay lines.

5. The frequency synthesizer of claim 1 wherein the phase-locked loop circuit includes a digital-to-analog converter coupled to an input of the ring oscillator and operates to tune frequency of the ring oscillator.

6. The frequency synthesizer of claim 5 wherein the digital-to-analog converter includes a coarse tuning bank comprised of one or more transistors biased on in a linear region and a fine tuning bank comprised of one or more transistors only biased in a saturation region.

7. The frequency synthesizer of claim 1 wherein the ring oscillator is further defined as a pseudo-differential ring oscillator with at least 32 phases.

8. The frequency synthesizer of claim 1 wherein the modulation controller uses single-point modulation control to frequency modulate the carrier signal.

9. The frequency synthesizer of claim 1 bandwidth for the phase-locked loop circuit is programmable and larger than modulation bandwidth.

10. The frequency synthesizer of claim 1 integrated into a wireless transmitter.

11. An ultra-low power wireless transmitter, comprising: an antenna; a phase-locked loop circuit configured to receive a carrier signal from an oscillating source and operates to generate a frequency modulated output signal, wherein the phase-locked loop circuit includes a ring oscillator with an embedded time-to-digital converter circuit; a controller interfaced with the phase-locked loop circuit and operates to frequency modulate the carrier signal in accordance with a frequency control word; a frequency multiplier circuit configured to receive the frequency modulated output signal from the phase-locked loop circuit and increase frequency of the frequency modulated output signal by a multiplier; and a power amplifier electrically coupled between an output of the frequency multiplier circuit and the antenna.

12. The wireless transmitter of claim 11 wherein the phase-locked loop circuit exhibits less than 65 kilohertz of frequency deviation.

13. The wireless transmitter of claim 11 wherein the frequency multiplier circuit outputs a signal at 2.4 GHz and the phase-locked loop circuit has a bandwidth greater than 5 megahertz and operates with 85 dBc/Hz in-band phase noise.

14. The wireless transmitter of claim 11 wherein the frequency multiplier circuit is further defined as a windowed edge combiner.

15. The wireless transmitter of claim 11 wherein the time-to-converter circuit directly samples phase of the ring oscillator without delay lines.

16. The wireless transmitter of claim 11 wherein the phase-locked loop circuit includes a digital-to-analog converter coupled to an input of the ring oscillator and operates to tune frequency of the ring oscillator.

17. The wireless transmitter of claim 16 wherein the digital-to-analog converter includes a coarse tuning bank comprised of one or more transistors biased on in a linear region and a fine tuning bank comprised of one or more transistors only biased in a saturation region.

18. The wireless transmitter of claim 11 wherein the ring oscillator is further defined as a pseudo-differential ring oscillator with at least 32 phases.

19. The wireless transmitter of claim 11 wherein the modulation controller uses single-point modulation control to frequency modulate the carrier signal.

20. The wireless transmitter of claim 11 wherein the power amplifier is further defined as a switched-capacitor digital power amplifier.

Description

DRAWINGS

(1) The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

(2) FIG. 1A is a graph showing simulated LO phase noise vs IFV in an open-loop oscillator compared to typical small bandwidth PLL.

(3) FIG. 1B is a graph showing a PLL bandwidth requirement for different phase noise levels.

(4) FIG. 2A is a simplified block diagram showing a divider based ADPLL with TDC as the PD.

(5) FIG. 2B is a simplified block diagram showing a divider-less ADPLL with TDC.

(6) FIG. 2C is a simplified block diagram showing a divider-less ADPLL with embedded TDC.

(7) FIG. 2D is a simplified block diagram showing a proposed ADPLL with quarter frequency OSC and 4 edge combiner.

(8) FIG. 3 is a block diagram of an example embodiment of a frequency synthesizer incorporating the proposed ADPLL.

(9) FIG. 4 is a diagram of a system level noise analysis with different noise sources including reference noise, TDC noise, DAC noise, VCO noise and EC noise.

(10) FIG. 5A is a graph showing noise performance of the proposed ADPLL showing modeled with different phase noise sources.

(11) FIG. 5B is a graph showing simulated vs modeled noise performance of the proposed ADPLL.

(12) FIG. 5C is a graph showing measured phase noise with corresponding IFV for the proposed ADPLL.

(13) FIG. 6 is a schematic of an example 16-stage pseudo-differential ring oscillator block and the RO delay cell with buffers.

(14) FIG. 7 is a schematic of an example current steering DAC for RO tuning and its major noise contributions.

(15) FIG. 8 is a schematic of an example edge combiner block and its working principle.

(16) FIG. 9 is a schematic of an example programmable switch-capacitor digital power amplifier.

(17) FIG. 10 shows a die photo of the proposed BLE transmitter.

(18) FIG. 11A is a graph showing the measured phase noise comparison between a free running ring oscillator vs the RF output.

(19) FIG. 11B is a graph showing measured phase noise comparison between a closed loop ring oscillator vs the RF output.

(20) FIG. 12 is a graph showing a PLL transient measurement.

(21) FIG. 13 is a graph showing PA efficiency versus output power with different power supplies.

(22) FIG. 14A is a graph showing output spectrum of the transmitter in low-power and high-power mode.

(23) FIG. 14B is a graph showing a spectrum comparison of FSK and GFSK in the PN limit region for the transmitter.

(24) FIG. 14C is a graph showing captured BLE packets and an eye diagram for the transmitter.

(25) FIG. 15 is a graph showing transmitter harmonic measurement with external matching network.

(26) FIG. 16 are charts showing a transmitter power breakdown in low-power and high-power mode.

(27) Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

(28) Example embodiments will now be described more fully with reference to the accompanying drawings.

(29) The relationship among phase noise, period jitter and instantaneous frequency variation has been well analyzed in various works. Frequency error of an LO can be roughly calculated based on the integrated PN. Since BLE is frequency modulated, it is beneficial to derive an intuitive relationship to link circuit level specs such as phase noise, and system level specs such as frequency deviation, modulation index, etc.

(30) In a high SNR regime where the target communication range is within 1-2 meters, phase noise is the dominant noise source. Flicker noise will contribute more in the slow frequency drift, so its effect in random jitter and instantaneous frequency variation (IFV) is negligible in this analysis. The mean squared value of period jitter and IFV is given by
.sub.f.sup.2=f.sub.0.sup.4.sub..sup.2(1)
where .sub.f, .sub. represent the standard deviation of IFV and jitter, and f.sub.0 is the center frequency. Using the Wiener-Khinchine theorem, one can calculate the mean squared jitter from the spectral density:

(31) $\begin{array}{cc}{}_{}^2={}_0^{}{S}_{}\left(f\right)\mathrm{df}=\frac{1}{f_0^4}{}_0^{}{S}_{}\left(f\right)f^2\sin c^2\left(\frac{f}{f_0}\right)\mathrm{df}& \left(2\right)\end{array}$
where S.sub.(f) and S.sub.(f) are the power spectral densities (PSDs) of jitter and random phase, respectively. It can be further simplified as:

(32) $\begin{array}{cc}{}_{}^2=\frac{2}{f_0^3}{}_0^{}\left(f\right)f^2\mathrm{df}{}_0^{}\sin c^2\left(x\right)\mathrm{dx}& \left(3\right)\end{array}$
where (f) is the PN PSD and with only white noise taken into consideration, (f)f.sup.2 is a constant. Thus, across the whole single side band (SSB), the relation among period jitter, IFV and PN can be simplified as:

(33) $\begin{array}{cc}{}_{}^2=\frac{1}{f_0^3}\left(f\right)f^2& \left(4\right)\end{array}$
.sub.f.sup.2=f.sub.0(f)f.sup.2(5)

(34) This is the classical link between jitter and PN, with a relation to IFV when noise in the whole SSB is considered. However, when it comes to the phase noise impact in radio circuit designs, one needs to consider the noise filtering effect in the receiver. Assuming a brick wall filter in the RX with a bandwidth BW.sub.rx:

(35) $\begin{array}{cc}{}_{}^2=\frac{2}{f_0^3}\left(f\right)f^2{}_0^{\frac{{\mathrm{BW}}_{\mathrm{rx}}}{f_0}}\sin c^2\left(x\right)\mathrm{dx}& \left(6\right)\end{array}$
Since the RX bandwidth is much smaller than the carrier frequency, the integral of the squared sinc function can be approximated as:

(36) $\begin{array}{cc}{}_0^{\frac{{\mathrm{BW}}_{\mathrm{rx}}}{f_0}}\sin c^2\left(x\right)\mathrm{dx}\mathrm{Si}\left(\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}\right)\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}& \left(7\right)\end{array}$
Thus, with the RX filter, the relation among jitter, PN and IFV can be modified as:

(37) $\begin{array}{cc}{}_{}^2=\frac{4{\mathrm{BW}}_{\mathrm{rx}}}{f_0^4}\left(f\right)f^2& \left(8\right)\\ {}_f^2=4{\mathrm{BW}}_{\mathrm{rx}}\left(f\right)f^2& \left(9\right)\end{array}$
This offers a simple intuition for circuit designers that once the RX filter BW is known, the PN spec at certain offset, say 1 MHz, can be calculated directly from the system level requirements for the frequency modulated signal.

(38) Next, consider the case where a PLL affects the PN noise shaping. When the PLL has a bandwidth BW.sub.pll, and with all the PLL noise sources taken into account, the in-band PN can be approximated as a constant .sub.in. So (2) becomes:

(39) $\begin{array}{cc}{}_{}^2=\frac{2{}_{\mathrm{in}}}{f_0^4}{}_0^{{\mathrm{BW}}_{\mathrm{pll}}}\frac{f_0^2}{{}^2}{\sin }^2\left(\frac{f}{f_0}\right)\mathrm{df}+\frac{2{}_{\mathrm{in}}{f}_{{\mathrm{BW}}_{\mathrm{pll}}}^2}{f_0^4}{}_{{\mathrm{BW}}_{\mathrm{pll}}}^{{\mathrm{BW}}_{\mathrm{rx}}}\sin c^2\left(\frac{f}{f_0}\right)\mathrm{df}\mathrm{Simplified}\mathrm{as}\text{:}& \left(10\right)\\ {}_{}^2=\left\{\begin{array}{c}\frac{1}{2{}^3{f}_0}\left(\frac{2{\mathrm{BW}}_{\mathrm{pll}}}{f_0}-\sin \left(\frac{2{\mathrm{BW}}_{\mathrm{pll}}}{f_0}\right)\right)+\\ \frac{4}{f_0^4}\left({\mathrm{BW}}_{\mathrm{rx}}-{\mathrm{BW}}_{\mathrm{pll}}\right){\mathrm{BW}}_{\mathrm{pll}}^2\end{array}\right\}{}_{\mathrm{in}}& \left(11\right)\\ {}_f^2=\left\{\begin{array}{c}\frac{f_0^3}{2{}^3}\left(\frac{2{\mathrm{BW}}_{\mathrm{pll}}}{f_0}-\sin \left(\frac{2{\mathrm{BW}}_{\mathrm{pll}}}{f_0}\right)\right)+\\ 4\left({\mathrm{BW}}_{\mathrm{rx}}-{\mathrm{BW}}_{\mathrm{pll}}\right){\mathrm{BW}}_{\mathrm{pll}}^2\end{array}\right\}{}_{\mathrm{in}}& \left(12\right)\end{array}$
Note that (11) and (12) show that the larger the PLL bandwidth, the larger the jitter and IFV. That is because in these equations, the in-band phase noise is set as a constant, and larger BW means a higher oscillator PN. On the other hand, larger BW means lower L.sub.in if the oscillator PN is preset. In PLL designs, the in-band PN is a more valuable spec than the oscillator spot PN at certain offset, since it also defines specs for other circuit blocks, which are also major PLL noise sources such as the reference, divider, TDC, and DAC, etc. For the BW.sub.rx<BW.sub.pll case, the PH, jitter and IFV relations are shown as follows:

(40) $\begin{array}{cc}{}_{}^2=\frac{1}{2{}^3{f}_0}\left(\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}-\sin \left(\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}\right)\right){}_{\mathrm{in}}& \left(13\right)\\ {}_f^2=\frac{f_0^3}{2{}^3}\left(\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}-\sin \left(\frac{2{\mathrm{BW}}_{\mathrm{rx}}}{f_0}\right)\right){}_{\mathrm{in}}& \left(14\right)\end{array}$
This case is very useful for RO based designs where RO PN is the dominant noise source for PLL design and it needs to be regulated with a wide PLL bandwidth.

(41) The above derivations show the relationship among PN, jitter, and IFV. Even though seemingly more complicated than the simple integral format, it offers a more intuitive link between spot/in-band PN to a system level spec in frequency modulated radios. This is because the 6.sub.f of the IFV is approximately the peak-to-peak frequency error, and spot/in-band PN is a direct indicator of oscillator/PLL design. For example, as shown in FIG. 1A, BLE requires a >370 kHz minimum frequency difference for a 250 k frequency deviation. Therefore a 3.sub.f<65 kHz can be used to define the PN spec (40 kHz for GFSK but in the noise limited region, Gaussian shaping won't effectively improve the spectrum efficiency). Comparing the open loop oscillator and PLL regulated case when the PLL BW and RX BW are set to 100 kHz and 2 MHz, FIG. 1A shows that the resulting IFV is comparable and leaves a big margin to the 65 kHz BLE requirement using LCVCO, which indicates an over-design in the LO noise-power penalty. FIG. 1B further shows that with a wide band PLL to suppress the in-band PN, an ULP RO could also achieve the target. This disclosure proposes to utilize a 80 dBc/Hz RO @ 1 MHz offset with a 4 MHz bandwidth PLL to verify the above analysis.

(42) In order to achieve the target PN using a noisy RO rather than the generally used LCVCO, the PLL design for the BLE transmitter is critical. Even though the major noise source is the VCO PN, other building blocks also need to be carefully dealt with, especially for low power designs. FIGS. 2A-2D show four different architectures of the TDC based DPLLs. The divider based ADPLL shown in FIG. 2A needs a relatively high power divider and suffers from divider noise folding as well as reference noise up-conversion. For fractional operation, an extra Delta-Sigma Modulator (DSM) is needed for the divider. Thus, this is a relatively power hungry choice. The divider-less ADPLL shown in FIG. 2B removes the divider and directly uses a TDC to generate the fractional error. This architecture removes the noise contributed from the divider and the DSM, but a TDC running at RF frequency consumes a significant amount of power, let alone an extra normalization circuit. Advanced designs in this architecture effectively reduce the TDC power consumption by introducing a DTC and snapshot circuit, but the timing misalignment and non-linearity of the DTC and TDC will introduce spurs. The pre-calibration circuit will result in extra power consumption too. As for the architecture shown in FIG. 2C with an embedded TDC, the power is saved by removing the removing the divider, TDC and the normalization circuit. However, the TDC resolution is severely limited by the number of RO stages at high frequency, which will result in a high in-band phase noise.

(43) FIG. 2D shows the simplified block diagram of a proposed all-digital phase-locker loop (ADPLL) 20 to address the above issues. The ADPLL 20 is comprised of a voltage-controlled oscillator 24, an embedded time-to-digital converter 23, a phase comparator 21 and a low pass filter 22. In an example embodiment, the voltage-controlled oscillator 24 includes a ring oscillator. As is commonly understood, embedded means the TDC circuit 23 directly samples phase of the ring oscillator without delay lines. The ADPLL 20 also includes a frequency multiplier circuit 25 configured to receive output from the phase-locked loop circuit and increase frequency of the output signal by a multiplier. In one example, the frequency multiplier circuit 25 is further defined as a windowed edge combiner.

(44) FIG. 3 further illustrates an example embodiment of a frequency synthesizer 30 with the proposed ADPLL. The frequency synthesizer 30 is comprised of a modulation controller 31, a phase-locked loop circuit 32 and a frequency multiplier circuit 33. The modulation controller 31 is configured to receive a reference signal from a reference source and operates to frequency modulate the reference signal in accordance with a frequency control word that is associated with the baseband data. The reference signal may be received via a programmable divider 34 from the reference source. The modulation controller 31 is interfaced via a serial peripheral interface (SPI) 35 with a digital gain block 42 to control loop gain of the phase-locked loop circuit 32 as well as interfaced with the switched capacitor digital amplifier 36 to control its power gain.

(45) In this example embodiment, the phase-locked loop circuit 32 includes a phase comparator 41, a digital gain block (e.g., type I loop filter) 42, a digital-to-analog converter 43, and a ring oscillator 44 with an embedded time-to-digital converter 45. A reference phase accumulator 37 provide the input to the phase-locked loop circuit 32, and a counter 46 and TDC encoder complete the loop of the phase-locked loop circuit 32. While a particular arrangement has been described, other implementations are also contemplated for the phase-locked loop circuit.

(46) To achieve the targeted frequency variation error with the ring oscillator 44, a 5 MHz bandwidth ADPLL for aggressive in-band phase noise suppression is implemented. It features a fast settling time and direct reference phase modulation at the frequency control word (FCW) since the PLL BW is much larger than the modulation bandwidth. The bandwidth is programmable by changing the loop filter gain through the SPI interface 35. Several techniques are used to save the PLL power and enhance its in-band phase noise at the same time. In the example embodiment, the ring oscillator 44 is designed at a frequency of f.sub.RF/4 and implemented with a 16-stage pseudo-differential architecture with 32 phases directly used as an embedded TDC. Its phases are also used in a windowed edge combiner 33 (EC) for 4 frequency multiplication to produce the 2.4 GHz RF frequency. The lower frequency ring oscillator 44 saves the power of the frequency divider. It also prevents the noise folding effect from happening in the divider based PLL, thus improving in-band phase noise performance.

(47) At the same time, the high power TDC 45 and its delay normalization circuits are also saved, and the TDC performance can be relaxed by dealing with the same amount of jitter at a lower frequency while maintaining the same resolution. The edge combiner 33 consumes much less power compared to a TDC, and it can maintain the low flicker noise corner from the low frequency ring oscillator 44, which will again, enhance the in-band phase noise. However, extra deterministic jitter will be introduced because of the mismatches in the different paths of the edge combiner, as modeled in FIG. 4. And due to periodical phase shifts, the edge combiner will also introduce spurs at f.sub.RF/4 off the center frequency. Its negative effect will be analyzed in more detail below.

(48) Referring to FIG. 4, major noise sources are modelled for the PLL, including reference noise, TDC noise, DAC noise and RO phase noise. The PLL is designed to achieve a 5 MHz BW with a 85 dBc/Hz in-band PN after edge combining. In this design, the in-band PN is dominated by both the RO and TDC. Due to the extended TDC bits, the TDC noise floor is around 100 dBc/Hz, which is comparable to the in-band PN of the quarter frequency RO, as shown in FIG. 5A. Ideally, the relative noise floor difference between RO and TDC are the same with or without the quadruple effect. However, since the absolute delay offset due to layout mismatch, loading variation and RO jitter are the same, the actual TDC noise floor is slightly enhanced in the quarter frequency RO architecture due to the larger VCO period:

(49) $\begin{array}{cc}{}_{\mathrm{TDC}}=\frac{{\left(2\right)}^2}{T_v^2}\left(\frac{t_{\mathrm{res}}^2}{12}+\frac{{}_M^2}{3}+\frac{2}{}{}_{}^2\right)\frac{1}{f_{\mathrm{REF}}}& \left(15\right)\end{array}$
where t.sub.res and T.sub.V is the TDC delay and the VCO period, and M correspond to the average mismatch. Here the mismatch is assumed as uniformly distributed. And for the embedded TDC, the jitter on the TDC edges follows the Gaussian distribution of the ring oscillator output. Since the delay, jitter and average mismatch are not correlated, the actual TDC noise floor with and without quarter frequency multiplication are shown in FIG. 5A, assuming a 10 ps rms jitter for the RO at 2.4 GHz. And after frequency multiplication, the in-band PN at 2.4 GHz output is slightly improved. The DAC resolution is restricted by the modulation, thus, the DAC noise floor is pretty low. And because of the divider-less nature of this design, the reference noise won't be up-converted as a problem.

(50) The edge combiner, due to loading mismatch, will add a certain delay D for each path. Thus the variance of the timing uncertainty from one path is:

(51) 0$\begin{array}{cc}{}_{{}_{\mathrm{EC}}}=\frac{{\left(D\right)}^2}{12}& \left(16\right)\end{array}$
In the worst case, there will be 3 phases with positive delay and 1 phase with negative delay, or vice versa. Thus the worst case delay is 3D in (16). The phase uncertainty is:

(52) $\begin{array}{cc}{}_{{}_{\mathrm{EC}}}=\frac{2{}_{{}_{\mathrm{EC}}}}{T_v}& \left(17\right)\end{array}$
So the worst case phase noise introduced by the EC is:

(53) $\begin{array}{cc}{}_{\mathrm{EC}}=\frac{{\left(2\right)}^2}{12}\frac{{\left(3D\right)}^2}{T_v^2}\frac{1}{f_V}& \left(18\right)\end{array}$
It shows that the EC will add an extra non-filtered noise floor in the overall PN output due to the path delay from layout mismatch. But in practice its level is relatively low compared to other noise sources unless the farout PN is of concern.

(54) Monte Carlo simulations for the EC show that the average delay offset is around 1.5 ps, and 1.7 ps calculated from indirect open loop PN measurement, which translates into a worst case noise floor of around 130 dBc/Hz. Thus the EC noise basically doesn't contribute to the in-band PN. From a time domain perspective, the EC-introduced jitter is much smaller than, and not correlated with, the random jitter from the high-PN RO. The windowed EC won't affect the overall RF performance in the random noise region. FIG. 5B shows the simulated PLL noise performance versus the model from the above analysis and FIG. 5C shows the measured PN of the proposed ADPLL. The phase noise performance corresponds to a 68.1 kHz 3.sub.f IFV, which is close to the target design. The spur level is equal to 20 log (t/T.sub.V), so it can be estimated that the typical spur level is <50 dBc according to simulation. With this f.sub.RF/4 RO and edge combiner architecture as well as the 5 b embedded TDC, the PLL controller's power consumption is 253 W in a 40 nm technology.

(55) Further details regarding the example implementation are set forth below. First, a detailed circuit design for the co-designed 16-stage pseudo-differential ring oscillator 44 with the embedded TDC 45 and the edge selector for the edge combiner 33 is shown in FIG. 6. All the 32 phases of the ring oscillator are buffered out and directly sampled by 32 D flip-flops. Then the 32 b outputs are encoded in a TDC encoder to form a 5b TDC as a fractional phase error sampler. One phase output is sent to the counter for integer phase error calculation, while the rest phases are connected to dummies for a balanced output to minimize the TDC DNL. On the other hand, all phases are also buffered out to an edge selection circuit, where 24 of them are arranged and fed to the edge combiner while the other 8 phases are connected to dummies for phase balance as well. To perform the 4 frequency multiplication through the edge combiner, 8 of the 24 phases are arranged as the input signal of the edge combiner while the other 16 phases are used to form 4 windows as the control signal of the edge combiner. The ring oscillator cell is implemented with 2 inverter stages for each cell and NMOS-only cross couple pairs rather than cross coupled inverters for minimized loading. And each cell has 6 buffered outputs for TDC, EC and counter (or dummies). This helps achieve the best balance among speed, phase noise and power efficiency for the ring oscillator.

(56) Next, a current steering DAC 43 for digital ring oscillator tuning is shown in FIG. 7. The DAC is one of the most important circuit blocks for the PLL noise performance since supply and bias noise are critical to ring oscillator based designs. The coarse DAC is 4b binary weighted and can cover up to 300 MHz, which tunes the oscillator from 400 MHz to 700 MHz. The medium and fine current steering DACs are 6b each that covers 70 MHz range with approximately 20 kHz LSB tuning step for the RO to keep a low DAC noise floor in the PLL. Since the PLL BW is very large for in-band phase noise suppression and direct reference phase modulation, the decap on the virtual VDD of the RO has to be fairly small to keep the PLL loop stable, thus plenty of noise from the supply and the bias network will pass through. To deal with this, the coarse DAC bank is designed at the edge of the triode region to minimize the noise gain since the coarse DAC has the highest current ratio and dominates the noise performance. Coarse tuning linearity and tuning range of the RO will be sacrificed for noise performance. The medium and fine DAC banks are designed in the saturation region to keep the required tuning linearity while the PLL is locked. Additional large on chip decaps are added to the gate of the DAC cells to filter the accumulated supply and bias noise.

(57) FIG. 8 shows an example embodiment of the windowed edge combiner 33. In the 24 phases of the ring oscillator input, 6 phases are used for each rising and falling edge to be combined, in which the 2 windows are spaced by 4 ring oscilaltor delays and the window width is 5 delays to ensure all selected phases pass through in different PVT corners. Tristate gates are used to pass the selected phase and buffer the interference from other phases. The timing diagram for edge combining is shown in FIG. 8. In this design, the edge combiner consumes just 20 W from simulation and its added jitter is much smaller than the RO jitter itself, keeping the RF output in the random noise region. In applications where the edge combiner jitter is comparable to the oscillator jitter, then it cannot be treated as working in the random noise region for frequency multiplication. Power has to be traded off for mismatch in the edge combiner circuit design according to system requirement.

(58) The power amplifier 36 is a switch-capacitor digital PA. The efficiency of this kind of PA is related to the ratio of the loading impedance and on resistance of the driving transistor minus the power of the harmonics. Higher loading impedance helps with efficiency but at the cost of lower output power level. As shown in FIG. 9, the SCDPA is thermometer coded with 8-bit cells and is matched and optimized for the highest efficiency for 10 dBm operation, which is sufficient for 2-3 meters short range communication.

(59) The frequency synthesizer with the proposed ADPLL described above is particularly suited for a BLE transmitter. As a proof of concept, a BLE transmitter was fabricated in 40 nm CMOS and the die photo of the prototype chip is shown in FIG. 10. The core area of the transmitter is 0.0166 mm2. The measurement results are shown as follows. FIG. 11A shows the measurement of the open loop and closed loop. FIG. 11B shows phase noise performance of the proposed ADPLL. When the RO is free running at 494 MHz, the PN @ 1 MHz offset is 95 dBc/Hz and the EC output at around 2 GHz is 83 dBc/Hz, with the noise corner both at around 1 MHz. The PN of the ADPLL is shown in FIG. 11B. It's locked at 600.5 MHz with a 37.5 MHz reference. The PLL bandwidth is around 5 MHz and the measured in-band PN of the oscillator and the EC output at 2.402 GHz are 96 dBc/Hz and 85 dBc/Hz, respectively.

(60) The PLL locking transient is shown in FIG. 12. As can be seen from the frequency vs time diagram, due to the large bandwidth, the PLL locks within 400 ns after reset from a 70 MHz initial frequency offset.

(61) FIG. 13 shows the SCDPA measurement showing the PA efficiency vs output power at different supply voltages. Using a 0.6V power supply, the PA consumes 107 W with a 19.2 dBm output power, yielding a 10.8% PA efficiency at the lower boundary of the BLE output power requirement. In its highpower mode with a 0.9V supply, it can deliver 3.3 dBm while consuming 1.2 mW with a 39% efficiency. The maximum efficiency of 41% is achieved at around 8 dBm (@0.7V) output power. Due to the non-linear nature of the SCDPA, an external matching network is used to suppress TX harmonic emissions. And the measured harmonic performance is shown in FIG. 15. With the off chip matching network, both HD2 and HD3 are smaller than 42 dBm with a 1.2V PA power supply, which complies with BLE requirements.

(62) The transmitter spectrum is measured while transmitting a repeated BLE packet, which meets the BLE spectrum mask requirement in both high power and low power modes using a 0.6V supply, as shown in FIG. 14A. A comparison of FSK and GFSK at the PN limit region is shown in FIG. 14B, showing that when operating at the PN limit region, FSK and GFSK basically have the same spectrum efficiency. This simplification in modulation could potentially help reduce the power consumption even more for applications such as self-powered sensors with power consumption as the primary concern. The measured frequency vs. time for part of the BLE packets are also shown. The eye-diagram is calculated from the captured frequency domain signal. The phase noise from the RO-based design does degrade the eye performance, but as designed, both the symbol timing and 3 IFV barely meet the BLE communication limit. The FSK error is 9.1% for this design, which can be expected from the 68 kHz frequency variation.

(63) The power breakdown is shown in FIG. 16. While working at the low power mode with a 37.5 MHz off chip reference, the RO with the DAC bias network consumes 126 W, the PA consumes 107 W and the PLL blocks with the edge combiner consumes 253 W. In high power mode, the PA consumes 1.2 mW. The all-digital RO based BLE TX consumes a total 486 W and 1.6 mW in low-power and high-power mode.

(64) The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.