MAGNETIC MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

Claims

1. A magnetic memory device, comprising: a bottom electrode layer; a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer; a dielectric cap layer disposed on the MTJ stack; and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

2. The magnetic memory device according to claim 1, wherein each of the second metal layers are sandwiched between two of the first metal layers.

3. The magnetic memory device according to claim 1, wherein the first metal layers respectively comprise Ru, the second metal layers respectively comprise Mn, Zn, Mo, Ta, or W.

4. The magnetic memory device according to claim 1, wherein the dielectric cap layer directly contacts one of the first metal layers.

5. The magnetic memory device according to claim 1, wherein the dielectric cap layer comprises MgO.

6. The magnetic memory device according to claim 1, further comprising a hard mask layer disposed on the metal cap layer and directly contacting one of the first metal layers.

7. The magnetic memory device according to claim 6, wherein the hard mask layer comprises TiN.

8. The magnetic memory device according to claim 1, wherein among the first metal layers, a thickness of the first metal layer on the top of the metal cap layer is larger than thicknesses of the rest of the first metal layers.

9. The magnetic memory device according to claim 1, further comprising: a buffer layer disposed between the dielectric cap layer and the metal cap layer, wherein the buffer layer directly contacts one of the first metal layers.

10. The magnetic memory device according to claim 9, wherein the buffer layer comprises CoFeB.

11. A method for forming a magnetic memory device, comprising: forming a magnetic tunneling junction (MTJ) stack on a bottom electrode layer; forming a dielectric cap layer on the MTJ stack; and forming a metal cap layer on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

12. The method for forming a magnetic memory device according to claim 11, wherein each of the second metal layers are sandwiched between two of the first metal layers.

13. The method for forming a magnetic memory device according to claim 11, wherein the first metal layers respectively comprise Ru, the second metal layers respectively comprise Mn, Zn, Mo, Ta, or W.

14. The method for forming a magnetic memory device according to claim 11, wherein the dielectric cap layer directly contacts one of the first metal layers.

15. The method for forming a magnetic memory device according to claim 11, wherein the dielectric cap layer comprises MgO.

16. The method for forming a magnetic memory device according to claim 11, further comprising forming a hard mask layer on the metal cap layer and directly contacting one of the first metal layers.

17. The method for forming a magnetic memory device according to claim 16, wherein the hard mask layer comprises TiN.

18. The method for forming a magnetic memory device according to claim 11, wherein among the first metal layers, a thickness of the first metal layer on the top of the metal cap layer is larger than thicknesses of the rest of the first metal layers.

19. The method for forming a magnetic memory device according to claim 11, further comprising: forming a buffer layer on the dielectric cap layer; and forming the metal cap layer on the buffer layer.

20. The method for forming a magnetic memory device according to claim 19, wherein the buffer layer comprises CoFeB.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 to FIG. 4 are schematic cross-sectional diagrams of a magnetic memory device at different steps of a manufacturing process according to an embodiment of the present invention.

[0009] FIG. 5 is a schematic cross-sectional diagram of a magnetic memory device according to another embodiment of the present invention.

DETAILED DESCRIPTION

[0010] To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

[0011] Please refer to FIG. 1 to FIG. 4, which are schematic cross-sectional diagrams showing a magnetic memory device at different steps of a manufacturing process according to an embodiment of the present invention. At the beginning of the manufacturing process, as shown in FIG. 1, a substrate 10 is provided. The substrate 10 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or a Group III-V semiconductor substrate, but is not limited thereto. The substrate 10 may include semiconductor devices formed therein, such as transistors, capacitors, resistors, inductors, or other active or passive semiconductor devices, which are not shown in the diagrams for the sake of simplification. Following, at least a dielectric layer and interconnect structures disposed in the dielectric layer may be formed on the substrate 10. For example, as shown in FIG. 1, a dielectric layer 12 having interconnect structures 14 (such as metal interconnect structures) formed therein may be formed on the substrate 10, and another dielectric layer 16 having interconnect structures 18 (such as contact vias) formed therein are then formed on the dielectric layer 12. The dielectric layer 12 and the dielectric layer 16 may respectively include silicon oxide (SiO.sub.2) or a suitable low-k dielectric material such as fluorinated silica glass (FSG), silicon oxycarbide (SiCOH), spin-on-glass, porous low-k dielectric material, organic dielectric polymers, or a combination thereof, but is not limited thereto. The interconnect structures 14 and the interconnect structures 18 may respectively include a conductive metal or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto.

[0012] Please refer to FIG. 2. Subsequently, a stack structure 100 is formed on the substrate 10. The stack structure 100 may include (sequentially from the bottom that is close to the substrate 10 to the top that is away from the substrate 10) a bottom electrode layer BE, a magnetic tunneling junction (MTJ) stack 20, a dielectric cap layer 30, a metal cap layer 32, and a hard mask layer 34. After that, an anneal process P1 may be performed to increase the perpendicular magnetic anisotropy (PMA) of the magnetic tunneling junction stack 20. According to an embodiment of the present invention, the temperature of the anneal process P1 may be between 350° C. and 450° C., and a process time of the anneal process P1 may be between 30 minutes and 5 hours, but is not limited thereto.

[0013] The bottom electrode layer BE is disposed on the dielectric layer 16 and directly contacts the interconnect structures 18. The bottom electrode layer BE may include a conductive metal or a metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto.

[0014] The magnetic tunneling junction stack 20 has a multilayer structure that includes (sequentially from the bottom that is close to the substrate 10 to the top that is away from the substrate 10) a reference layer 24, a pinned layer 25, a tunneling barrier layer 26, and a free layer 28. The reference layer 24 may include an anti-ferromagnetic (AFM) material such as PtMn, IrMn, PtIr, other suitable anti-ferromagnetic materials, or a combination thereof, but is not limited thereto. The reference layer 24 is used to pin or fix nearby ferromagnetic layers to a particular magnetic polarity. The pinned layer 25 and the free layer 28 may respectively include a ferromagnetic material, such as Fe, Co, Ni, FeNi, FeCo, CoNi, FeB, FePt, FePd, CoFeB, or the like, but are not limited thereto. The magnetic polarity of the pinned layer 25 is fixed (anti-ferromagnetic coupled) by the reference layer 24, while the magnetic polarity of the free layer 28 may be changed by an external magnetic field. The tunneling barrier layer 26 is sandwiched between the pinned layer 25 and the free layer 28 and may include a metal oxide such as MgO, Al.sub.2O.sub.3, NiO, GdO, Ta.sub.2O.sub.5, MoO.sub.2, TiO.sub.2, WO.sub.2, or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, the tunneling barrier layer 26 includes MgO. The reference layer 24, the pinned layer 25, the tunneling barrier layer 26 and the free layer 28 may respectively have a single layer or a multilayer structure, and each layer may have a thickness approximately between several angstroms (Å) to several tens of nanometers (nm).

[0015] The dielectric cap layer 30 may be directly disposed on the free layer 28 of the magnetic tunneling junction stack 20 to provide protection to the magnetic tunneling junction stack 20. The dielectric cap layer 30 may include a metal oxide such as MgO, Al.sub.2O.sub.3, NiO, GdO, Ta.sub.2O.sub.5, MoO.sub.2, TiO.sub.2, WO.sub.2, or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, the dielectric cap layer 30 includes MgO.

[0016] The metal cap layer 32 may be directly disposed on the dielectric cap layer 30, or may be disposed on a buffer layer (such as the buffer layer 31 shown in FIG. 5) on the dielectric cap layer 30. The metal cap layer 32 has a multilayer structure that includes a plurality of first metal layers 32a and a plurality of second metal layers 32b alternately stacked on the dielectric cap layer 30, wherein the topmost layer and the bottommost layer of the multilayer structure of the metal cap layer 32 are the first metal layers 32a. The second metal layers 32b are respectively sandwiched between two of the first metal layers 32a. According to an embodiment of the present invention, the metal cap layer 32 may include n+1 numbers of first metal layers 32a and n numbers of second metal layers 32b, wherein n is a positive integer greater than or equal to 2. When the metal cap layer 32 is directly disposed on the dielectric cap layer 30, the dielectric cap layer 30 is in direct contact with the bottommost first metal layers 32a of the metal cap layer 32. The first metal layers 32a may include a metal material with a good conductivity and able to protect the underlying layers from being oxidized. In a preferred embodiment, the first metal layers 32a include ruthenium (Ru) which may react with oxygen (such as ambient oxygen) to form a dense ruthenium oxide film on the surface. The surface ruthenium oxide film may block oxygen penetration, so that the underlying material layers may be well protected from being oxidized. Furthermore, ruthenium oxide still has good conductivity and would not evidently influence the resistance of the magnetic memory device. The second metal layers 32b may respectively include a metal material that is able to react with the material of the first metal layers 32a (the portion not being oxidized) to form an alloy during a thermal process (such as the anneal process P1). By turning the first metal layers 32a into alloy, the problems of abnormal tunneling magnetoresistance due to diffusion of the material of the first metal layers 32a into the magnetic tunneling junction stack 20 may be prevented. According to an embodiment of the present invention, when the first metal layers 32a include ruthenium (Ru), preferably, the second metal layers 32b may respectively include vanadium (V), manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), or other metal materials that have an alloy forming enthalpy with ruthenium (Ru) approximately between −330 and −15 kJ/mol to react with ruthenium (Ru) to form alloy easily. According to an embodiment of the present invention, all of the first metal layers 32a of the metal cap layer 32 are made of ruthenium (Ru), and the second metal layers 32b of the metal cap layer 32 are respectively made of one selected from manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), and tungsten (W). According to another embodiment of the present invention, all of the second metal layers 32b of the metal cap layer 32 are made manganese (Mn). As shown in FIG. 2, the first metal layer 32a on the top of the metal cap layer 32 is used as the major oxygen blocking layer, and may have a thickness larger than thicknesses of the rest of the first metal layers 32a.

[0017] The hard mask layer 34 may be directly disposed on the metal cap layer 32 and is in direct contact with the first metal layer 32a on the top of the metal cap layer 32. The hard mask layer 34 may include a conductive metal or a metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, the hard mask layer 34 includes titanium nitride (TiN). The hard mask layer 34 may be used as an etch stop layer during a subsequent patterning process (such as the patterning process P2 shown in FIG. 3) to protect the underlying layers and help to form memory cells (such as the memory cells 35 shown in FIG. 3) with vertical sidewalls. The hard mask layer 34 may also be used as top electrodes of the memory cells.

[0018] During the anneal process P1, diffusion of atoms may occur in the stack structure 100. For example, nitrogen (N) atoms of the hard mask layer 34 made of TiN and ruthenium (Ru) atoms of the second metal layers 32b of the metal cap layer 32 tend to diffuse downward. The present invention disposes the second metal layers 32b made of Mn, Zn, Mo, Ta, or W between the first metal layers 32a to react with the Ru atoms of the first metal layers 32a to form alloy, so that no free Ru atoms may diffuse into the magnetic tunneling junction stack 20. The nitrogen (N) atoms may also be blocked from diffusing into the magnetic tunneling junction stack 20 by the second metal layers 32b, and the problems of nitridation of the ferromagnetic materials of the magnetic tunneling junction stack 20 may be resolved.

[0019] Please refer to FIG. 3. Subsequently, a patterning process P2 (such as a photolithography-etching process) is performed to pattern the stack structure 100 and remove unnecessary portions of the bottom electrode layer BE, the magnetic tunneling junction (MTJ) stack 20, the dielectric cap layer 30, the metal cap layer 32, and the hard mask layer 34, thereby obtaining a plurality of memory cells 35 respectively disposed on the interconnect structures 18.

[0020] Please refer to FIG. 4. Subsequently, a passivation layer 40 may be conformally formed on the substrate 10 to cover the surface of the dielectric layer 16 and the top surfaces and sidewalls of the memory cells 35. Afterward, an interlayer dielectric layer 42 is formed on the passivation layer 40 in a blanket manner to cover the memory cells 35 and completely fill the spaces between the memory cells 35. The passivation layer 40 may include an insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), or carbon nitride (SiCN), but is not limited thereto. The interlayer dielectric layer 42 may include silicon oxide (SiO.sub.2) or a suitable low-k dielectric material such as fluorinated silica glass (FSG), silicon oxycarbide (SiCOH), spin-on-glass, porous low-k dielectric material, organic dielectric polymers, or a combination thereof, but is not limited thereto. Following, a plurality of interconnect structures 44 are formed directly on the memory cells 35. The interconnect structures 44 respectively penetrate through the interlayer dielectric layer 42 and the passivation layer 40 to direct contact and electrically connect to the hard mask layers 34 (used as the top electrodes) of the memory cells 35. The interconnect structures 44 may include a conductive metal or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto.

[0021] Please continue to refer to FIG. 4, which shows a schematic cross-sectional diagram of a magnetic memory device provided by the present invention. The magnetic memory device includes a bottom electrode layer BE, a magnetic tunneling junction (MTJ) stack 20 disposed on the bottom electrode BE, a dielectric cap layer 30 disposed on the magnetic tunneling junction stack 20, a metal cap layer 32 disposed on the dielectric cap layer 30, and a hard mask layer 34 disposed on the metal cap layer 32. The metal cap layer 32 includes a plurality of alternately stacked first metal layers 32a and second metal layers 32b, wherein the topmost layer and the bottommost layer of the metal cap layer 32 are the first metal layers 32a, and the second metal layers 32b are respectively sandwiched between the first metal layers 32a. The multilayer design of the metal cap layer 32 that comprises alternating first metal layers 32a and second metal layer 32b wherein the first metal layers 32a preferably include ruthenium (Ru) and the second metal layer 32b preferably include at least one of manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum At least one of (Ta) or tungsten (W) may effectively reduce the risk of oxidation and/or nitridation of the underlying magnetic tunneling junction stack 20.

[0022] Please refer to FIG. 5, which is a schematic cross-sectional diagram of a magnetic memory device according to another embodiment of the present invention. The similar or corresponding features between the magnetic memory devices shown in FIG. 5 and FIG. 4 are labeled by the same reference numbers. Details of the features have been elaborated in previous paragraphs and would not be repeated again. A difference between the magnetic memory device shown in FIG. 5 and the magnetic memory device shown in FIG. 4 is that the magnetic memory device shown in FIG. 5 further includes a buffer layer 31 disposed between the dielectric cap layer 30 and the metal cap layer 32 and is in direct with the bottommost first metal layer 32a of the metal cap layer 32. The buffer layer 31 may reduce the influence on the magnetic tunneling junction 20 caused by the stress of the metal cap layer 32 and the hard mask layer 34. The buffer layer 31 may include a ferromagnetic material, such as Fe, Co, Ni, FeNi, FeCo, CoNi, FeB, FePt, FePd, CoFeB, or the like, but are not limited thereto. According to an embodiment of the present invention, the buffer layer 31 may include CoFeB.

[0023] In summary, by forming a metal cap layer 32 with a multilayer structure between the dielectric cap layer 30 and the hard mask layer 34, the magnetic memory device provided by the present invention may prevent oxygen and/or atoms of the hard mask layer 34 penetrating into the magnetic tunneling junction stack 20, so that problems of abnormal tunneling magnetoresistance may be reduced.

[0024] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.