DIFFERENTIAL MODE CONVERTER, AND MEASURING DEVICE INCLUDING DIFFERENTIAL MODE CONVERTER

Abstract

A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.

Claims

1. A differential mode converter comprising: an input mode converter configured to convert an input voltage input in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.

2. The differential mode converter of claim 1, further comprising: a low pass filter configured to remove high frequency noise and offset of the first chopping voltage and the second chopping voltage.

3. The differential mode converter of claim 1, wherein the input mode converter comprises: a first amplifier including a first input terminal to which a signal is inputted through a target resistance, a second input terminal to which the reference voltage is inputted and a first output terminal which outputs the first differential voltage; a second amplifier including a third input terminal to which a signal is inputted through the target resistance, a fourth input terminal to which the reference voltage is inputted and a second output terminal which outputs the second differential voltage; a first switch having one end connected to the input voltage, the other end of the first switch being connected to the first input terminal of the first amplifier; a second switch having one end connected to the first output terminal of the first amplifier, the other end of the second switch being connected to the third input terminal of the second amplifier; a third switch having one end connected to the input voltage, the other end of the third switch being connected to the third input terminal of the second amplifier; and a fourth switch having one end connected to the second output terminal of the second amplifier, the other end of the fourth switch being connected to the first input terminal of the first amplifier.

4. The differential mode converter of claim 3, wherein a first clock signal and a second clock signal are generated from a clock signal generator disposed outside the differential mode converter, the first clock signal and the second clock signal having a form of a square wave and logic states opposite to each other, the first switch and the second switch are turned ON when the logic state of the first clock signal is high, and the third switch and the fourth switch are turned ON when the logic state of the second clock signal is high.

5. The differential mode converter of claim 4, wherein the input mode converter further comprises: a first resistance disposed between the first input terminal and the first output terminal of the first amplifier; a second resistance disposed between the third input terminal and the second output terminal of the second amplifier; a third resistance disposed between the second switch and the first output terminal of the first amplifier; and a fourth resistance disposed between the fourth switch and the second output terminal of the second amplifier.

6. The differential mode converter of claim 5, wherein the first resistance, the second resistance, the third resistance and the fourth resistance have a same resistance value.

7. The differential mode converter of claim 1, wherein the chopper comprises: an input terminal to which the first differential voltage is inputted; an input terminal to which the second differential voltage is inputted; an output terminal which outputs the first chopping voltage; an output terminal which outputs the second chopping voltage; a fifth switch having one end connected to the input terminal to which the first differential voltage is inputted, the other end of the fifth switch being connected to the output terminal which outputs the first chopping voltage; a sixth switch having one end connected to the input terminal to which the second differential voltage is inputted, the other end of the sixth switch being connected to the output terminal which outputs the second chopping voltage; a seventh switch having one end connected to the input terminal to which the first differential voltage is inputted, the other end of the seventh switch being connected to the output terminal which outputs the second chopping voltage; and an eighth switch having one end connected to the input terminal to which the second differential voltage is inputted, the other end of the eighth switch being connected to the output terminal which outputs the first chopping voltage.

8. The differential mode converter of claim 7, wherein a first clock signal and a second clock signal are generated from a clock signal generator disposed outside the differential mode converter, the first clock signal and the second clock signal having a form of a square wave and logic states opposite to each other, the fifth switch and the sixth switch are turned ON when the logic state of the first clock signal is high, and the seventh switch and the eighth switch are turned ON when the logic state of the second clock signal is high.

9. A measuring device comprising: a target resistance whose resistance value is to be measured; an input mode converter configured to convert an input voltage transmitted through the target resistance in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage; and an analog-to-digital converter configured to perform an analog-to-digital conversion on the first output voltage and the second output voltage to output a digital signal based on the resistance value of the target resistance.

10. The measuring device of claim 9, further comprising: a low pass filter configured to remove high frequency noise and offset of the first chopping voltage and the second chopping voltage, and provide the first output voltage and the second output voltage to the analog-digital converter without the high frequency noise and offset.

11. The measuring device of claim 9, wherein the input mode converter comprises: a first amplifier including a first input terminal to which a signal is inputted through a target resistance, a second input terminal to which the reference voltage is inputted and a first output terminal which outputs the first differential voltage; a second amplifier including a third input terminal to which a signal is inputted through the target resistance, a fourth input terminal to which the reference voltage is inputted and a second output terminal which outputs the second differential voltage; a first switch having one end connected to the input voltage, the other end of the first switch being connected to the first input terminal of the first amplifier; a second switch having one end connected to the first output terminal of the first amplifier, the other end of the second switch being connected to the third input terminal of the second amplifier; a third switch having one end connected to the input voltage, the other end of the third switch being connected to the third input terminal of the second amplifier; and a fourth switch having one end connected to the second output terminal of the second amplifier, the other end of the fourth switch being connected to the first input terminal of the first amplifier.

12. The measuring device of claim 11, wherein a first clock signal and a second clock signal are generated from a clock signal generator disposed outside the differential mode converter, the first clock signal and the second clock signal having a form of a square wave and logic states opposite to each other, the first switch and the second switch are turned ON when the logic state of the first clock signal is high, and the third switch and the fourth switch are turned ON when the logic state of the second clock signal is high.

13. The measuring device of claim 12, wherein an input mode converter further comprises: a first resistance disposed between the first input terminal and the first output terminal of the first amplifier; a second resistance disposed between the third input terminal and the second output terminal of the second amplifier; a third resistance disposed between the second switch and the first output terminal of the first amplifier; and a fourth resistance disposed between the fourth switch and the second output terminal of the second amplifier.

14. The measuring device of claim 13, wherein the target resistance has one end connected to the first switch and the third switch.

15. The measuring device of claim 13, wherein the first resistance, the second resistance, the third resistance and the fourth resistance have a same resistance value.

16. The measuring device of claim 15, wherein when the first clock signal is high and the second clock signal is low, the first differential voltage and the second differential voltage are expressed as an equation of V.sub.amp1=V.sub.ref(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref) and an equation of V.sub.amp2=V.sub.ref+(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref), respectively, wherein when the second clock signal is high and the first clock signal is low, the first differential voltage and the second differential voltage are expressed as an equation of V.sub.amp1=V.sub.ref+(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref) and an equation of V.sub.amp2=V.sub.ref(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref), respectively, and wherein the V.sub.amp1 represents the first differential voltage, the V.sub.amp2 represents the second differential voltage, the V.sub.ref represents the reference voltage, the R.sub.std represents the first resistance, the second resistance, the third resistance or the fourth resistance, and the R.sub.sens represents the target resistance and the V.sub.DD represents the input voltage.

17. The measuring device of claim 9, wherein the chopper comprises: an input terminal to which the first differential voltage is inputted; an input terminal to which the second differential voltage is inputted; an output terminal which outputs the first chopping voltage; an output terminal which outputs the second chopping voltage; a fifth switch having one end connected to the input terminal to which the first differential voltage is inputted, the other end of the fifth switch being connected to the output terminal which outputs the first chopping voltage; a sixth switch having one end connected to the input terminal to which the second differential voltage is inputted, the other end of the sixth switch being connected to the output terminal which outputs the second chopping voltage; a seventh switch having one end connected to the input terminal to which the first differential voltage is inputted, the other end of the seventh switch being connected to the output terminal which outputs the second chopping voltage; and an eighth switch having one end connected to the input terminal to which the second differential voltage is inputted, the other end of the eighth switch being connected to the output terminal which outputs the first chopping voltage.

18. The measuring device of claim 17, further comprising: a clock signal generator configured to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal having a form of a square wave and logic states opposite to each other, wherein the fifth switch and the sixth switch are turned ON when the logic state of the first clock signal is high, and wherein the seventh switch and the eighth switch are turned ON when the logic state of the second clock signal is high.

19. The measuring device of claim 9, further comprising: a microcontroller configured to execute a process for displaying the digital signal outputted from the analog-to-digital converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a diagram showing a differential mode converter according to an embodiment of the present disclosure.

[0013] FIG. 2A shows an example of a waveform of a first differential voltage (V.sub.amp1) of an input mode converter in FIG. 1.

[0014] FIG. 2B shows an example of a waveform of a second differential voltage (V.sub.amp2) of the input mode converter in FIG. 1.

[0015] FIG. 3A shows an example of a waveform of a first chopping voltage (V.sub.chop1) of a chopper in FIG. 1.

[0016] FIG. 3B shows an example of a waveform of the second chopping voltage (V.sub.chop2) of the chopper in FIG. 1.

[0017] FIG. 4 shows an example of output waveforms (V.sub.lpf1, V.sub.lpf2) of a low pass filter in FIG. 1.

[0018] FIG. 5 shows a configuration of a measuring device using the differential mode converter according to another embodiment of the present disclosure.

[0019] FIG. 6 is a diagram showing a process of an operation of a switch according to clock signals in the measuring device in FIG. 5.

[0020] FIG. 7 is another diagram showing a process of an operation of a switch according to clock signals in the measuring device in FIG. 5.

[0021] FIG. 8 is a diagram showing a system for measuring a resistance value from a digital bit output from an analog to digital converter in FIG. 5.

DETAILED DESCRIPTION

[0022] Advantages, features and methods for achieving them will become apparent from the embodiments which will be described later in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described herein below but implemented in many different forms. The embodiments are provided to make complete the present disclosure and to completely inform the scope of the present disclosure to those skilled in the art to which the present disclosure pertains. The present disclosure is defined only by the claims.

[0023] In describing the embodiments of the present disclosure, the detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed descriptions of well-known functions or configurations unnecessarily make obscure the spirit of the present disclosure. The terms to be described later are defined in view of the functions exercised in the embodiments of the present disclosure and vary depending on the intention of a user or an operator and the practice. Thus, the definition of terms shall be made based on the overall contents of the subject specification.

[0024] In accordance with an embodiment of the present disclosure, there is provided a differential mode converter capable of converting a signal inputted in a single-ended mode into a differential mode and applying it as a differential input signal for a chopper circuit. Improved measuring accuracy and high resolution can be obtained by filtering a differential output signal of the chopper circuit through a low-pass filter and performing an analog-to-digital conversion. From this technical idea, the object of the present disclosure can be easily achieved.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] FIG. 1 schematically illustrates a differential mode converter 1 in accordance with one embodiment of the present disclosure. As shown in FIG. 1, the differential mode converter 1 includes a target resistance R.sub.sens, an input mode converter 100, a chopper 200 and a low pass filter 300.

[0027] As shown in FIG. 1, the target resistance R.sub.sens is a resistance element to measure a resistance value. One end of the target resistance is connected to an input voltage V.sub.DD. The other end of the target resistance R.sub.sens is connected to respective ends of a first switch 102/1 and a third switch 102/3 of the input mode converter 100.

[0028] The input mode converter 100 serves to receive the input voltage V.sub.DD in a single-ended mode and convert it into a first differential voltage V.sub.amp1 and a second differential voltage V.sub.amp2 to be output, the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 having a form of a square wave and being symmetric with respect to a reference voltage V.sub.ref.

[0029] The input mode converter 100 includes a first amplifier AMP1, a second amplifier AMP2, first to fourth switches 102/1, 102/2, 102/3 and 102/4 and first to fourth resistances R.sub.std1, R.sub.std2, R.sub.std3 and R.sub.std4.

[0030] The first amplifier AMP1 includes a first input terminal (inverting input terminal) to which a signal is inputted through a target resistance R.sub.sens, a second input terminal (non-inverting input terminal) to which the reference voltage V.sub.ref is inputted and a first output terminal which outputs the first differential voltage V.sub.amp1.

[0031] The second amplifier AMP1 includes a third input terminal (inverting input terminal) to which a signal is inputted through a target resistance R.sub.sens, a fourth input terminal (non-inverting input terminal) to which the reference voltage V.sub.ref is inputted and a second output terminal to output the second differential voltage V.sub.amp1.

[0032] The first and second amplifiers AMP1 and AMP2, for example, include an operational amplifier having two input terminals and one output terminal. However, it should be understood that various types of amplifiers for implementing an embodiment of the present disclosure can be employed as long as it is possible to implement two amplifiers each having two input terminals and one output terminal.

[0033] The first switch 102/1 has one end connected to the input voltage V.sub.DD through the target resistance R.sub.sens, and the other end thereof is connected to the first input terminal of the first amplifier AMP1.

[0034] The second switch 102/2 has one end connected to the first output terminal of the first amplifier AMP1 and the other end thereof is connected to the third input terminal of the second amplifier AMP2.

[0035] The third switch 102/3 has one end connected to the input voltage V.sub.DD through the target resistance R.sub.sens, and the other end thereof is connected to the third input terminal of the second amplifier AMP2.

[0036] The fourth switch 102/4 has one end connected to the second output terminal of the second amplifier AMP2 and the other end thereof is connected to the first input terminal of the first amplifier AMP1.

[0037] Here, the first switch 102/1 and the second switch 102/2 are turned ON when the logic state of a first clock signal CK in FIGS. 2A and 2B is high. The third switch 102/3 and the fourth switch 102/4 are turned ON when the logic state of a second clock signal CKB in FIGS. 2A and 2B is high. Specifically, as shown in FIGS. 2A and 2B, when the logic state of the first clock signal CK is high, V.sub.ref voltage of the first differential voltage V.sub.amp1 is generated through the first switch 102/1, and V.sub.ref+ voltage of the second differential voltage V.sub.amp2 is generated through the second switch 102/2. The two differential voltages V.sub.amp1 and V.sub.amp2 are generated in the symmetrical forms to each other with respect to a reference voltage V.sub.ref. On the other hand, when the logic state of the second clock signal CKB is high, V.sub.ref voltage of the second differential voltage V.sub.amp2 is generated through the third switch 102/3 and V.sub.ref+ voltage of the first differential voltage V.sub.amp1 is generated through the fourth switch 102/4. In this case, the two differential voltages V.sub.amp1 and V.sub.amp2 are kept symmetric with respect to the reference voltage V.sub.ref with the values thereof changed. The first clock signal CK and the second clock signal CKB always have the opposite logic states. Accordingly, the first switch 102/1 and the second switch 120/2 always have the opposite logic states to the third switch 102/3 and the fourth switch 102/4. The first clock signal CK and the second clock signal CKB are generated by a clock signal generator to be described later, and the operation process of the first switch 102/1, the second switch 102/2, the third switch 102/3 and the fourth switch 102/4 based on the clock signal of the clock signal generator will be described in detail with reference to FIGS. 6 and 7.

[0038] The first resistance R.sub.std1 is disposed between the first input terminal and the first output terminal of the first amplifier AMP1, the second resistance R.sub.std2 is disposed between the third input terminal and the second output terminal of the second amplifier AMP2. Furthermore, the third resistance R.sub.std3 is disposed between the second switch 102/2 and the first output terminal of the amplifier AMP1, the fourth resistance R.sub.std4 is disposed between the fourth switch 102/4 and the second output terminal of the second amplifier AMP2.

[0039] Here, the first resistance R.sub.std1, the second resistance R.sub.std2, the third resistance R.sub.std3 and the fourth resistance R.sub.std4 are the reference resistances having the same resistance value.

[0040] FIGS. 2A and 2B show an example of an output waveform of the input mode converter 100 in FIG. 1.

[0041] Specifically, FIG. 2A illustrates a waveform of the first differential voltage V.sub.amp1 outputted from the first output terminal of the first amplifier AMP1 of the input mode converter 100. FIG. 2B illustrates a waveform of the second differential voltage V.sub.amp2 outputted from the second output terminal of the second amplifier AMP2 of the input mode converter 100. Here, if the logic state of the clock signal CK, for example, is high, the second clock signal CKB is low which is opposite to the first clock signal CK.

[0042] As shown in FIGS. 2A and 2B, the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 are outputted in the square wave forms symmetrical to each other with respect to a reference voltage V.sub.ref.

[0043] Referring back to FIG. 1, the chopper 200 of the differential mode converter 1 according to the embodiment of the present disclosure receives the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 from the input mode converter 100 and outputs the first chopping voltage V.sub.chop1 and the second chopping voltage V.sub.chop2 which have DC voltage forms symmetrical to each other with respect to a reference voltage V.sub.ref.

[0044] As shown in FIG. 1, the chopper 200 includes an input terminal to which the first differential voltage V.sub.amp1 is inputted, an input terminal to which the second differential voltage V.sub.amp2 is inputted, an output terminals which outputs the first chopping voltage V.sub.chop1, an output terminals which outputs the second chopping voltage V.sub.chop2, and the fifth to eighth switches 102/5, 102/6, 102/7 and 102/8.

[0045] As shown in FIG. 1, one end of the fifth switch 102/5 is connected to the output terminal of the first differential voltage V.sub.amp1 of the input mode converter 100, and the other end thereof outputs the first chopping voltage V.sub.chop1.

[0046] One end of the sixth switch 102/6 is connected to the output terminal of the second differential voltage V.sub.amp2 of the input mode converter 100, and the other end thereof outputs the second chopping voltage V.sub.chop2.

[0047] One end of the seventh switch 102/7 is connected to the output terminal of the first differential voltage V.sub.amp2 of the input mode converter 100, and the other end thereof outputs the second chopping voltage V.sub.chop1.

[0048] One end of the eighth switch 102/8 is connected to the output terminal of the second differential voltage V.sub.amp2 of the input mode converter 100, and the other end thereof outputs the first chopping voltage V.sub.chop1.

[0049] Here, the fifth switch 102/5 and the sixth switch 102/6 are turned ON when the logic state of the first clock signal CK is high, the seventh switch 102/7 and the eighth switch 102/8 are turned ON when the logic state of the second clock signal CKB is high. Specifically, when the logic state of the first clock signal CK is high, V.sub.ref voltage of the first differential voltage V.sub.amp1 is generated through the fifth switch 102/5 and V.sub.ref+ voltage of the second differential voltage V.sub.amp2 is generated through the sixth switch 102/6. In addition, when the logic state of the second clock signal CKB is high, V.sub.ref+ voltage of the first differential voltage V.sub.amp1 is generated through the seventh switch 102/7 and V.sub.ref voltage of the second differential voltage V.sub.amp2 is generated through the eighth switch 102/8. Accordingly, the first chopping voltage V.sub.chop1 is maintained as V.sub.ref voltage and the second chopping voltage V.sub.chop2 is maintained as V.sub.ref+ voltage regardless of high and low of the logic states of the first clock signal CK and the second clock signal CKB. Accordingly, the first chopping voltage V.sub.chop1 outputted through the clock operation of the chopper 200 has the waveform as shown in FIG. 3A, and the second chopping voltage V.sub.chop2 has the waveform as shown in FIG. 3B. The first clock signal CK and the second clock signal CKB of the chopper 200 are generated through the clock signal generator, these operation process of the fifth to eighth switches 102/5, 102/6, 102/7 and 102/8 in the chopper in accordance with the clock signals from the clock signal generator will be described in detail in FIGS. 6 and 7.

[0050] The low pass filter 300 serves to remove high frequency noise and offset of the first chopping voltage V.sub.chop1 and the second chopping voltage V.sub.chop2 outputted from the chopper 200.

[0051] In an actual environment, the complete DC voltages as shown in FIGS. 3A and 3B are not outputted, and high frequency noise and offset component are combined to generate a distorted waveform. Therefore, in the present embodiment, the low-pass filter unit 300 is added to the rear stage to remove high-frequency noise and offset.

[0052] FIG. 4 is a diagram illustrating a final output waveform after removing high frequency noise and offset through the low pass filter 300.

[0053] In FIG. 4, the reference voltage V.sub.ref is exemplified as 0.9V, and it can be seen that the voltages are outputted in the symmetrical form having the same difference in magnitude with respect to the reference voltage V.sub.ref. At this time, the magnitude of the output voltage with respect to the reference voltage V.sub.ref varies depending on the values of the input voltage V.sub.DD and the target resistance R.sub.sens. In FIG. 4, reference numeral B indicates points at which the magnitude of the output voltage is changed in accordance with the change in the resistance value of the target resistance R.sub.sens.

[0054] FIG. 5 is a configuration diagram of the measuring device using the differential mode converter 1 according to an embodiment, the target resistance R.sub.sens and the analog-to-digital converter 400 are added to the differential mode converter shown in FIG. 1.

[0055] The target resistance R.sub.sens shown in FIG. 5 is a resistance element whose resistance value is intended to be measured by the measuring device in FIG. 5. One end of the target resistance R.sub.sens is connected to the input voltage V.sub.DD and the other end thereof is connected to one ends of the first switch 102/1 and the third switch 102/3 of the input mode converter 100.

[0056] The input mode converter 100 receives the input voltage V.sub.DD provided through the target resistance R.sub.sens in a single-ended mode and converts it into the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2, which are symmetric with respect to the reference voltage V.sub.ref and have a square wave form, to be outputted.

[0057] The input mode converter 100 includes the first amplifier AMP1, the second amplifier AMP2, the first switch 102/1, the second switch 102/2, the third switch 102/3, the fourth switch 102/4 and the first to fourth resistance R.sub.std1, R.sub.std2, R.sub.std3 and R.sub.std4.

[0058] The first amplifier AMP1 includes the first input terminal (inverting input terminal) to which a signal is inputted through the target resistance R.sub.sens, the second input terminal (non-inverting input terminal) to which the reference voltage V.sub.ref is inputted, and the first output terminal which outputs the first differential voltage V.sub.amp1.

[0059] The second amplifier AMP2 includes the third input terminal (inverting input terminal) to which a signal is inputted through a target resistance R.sub.sens, the fourth input terminal (non-inverting input terminal) to which the reference voltage V.sub.ref is inputted, and the second output terminal which outputs the second differential voltage V.sub.amp2.

[0060] The first amplifier AMP1 and the second amplifier AMP2, for example, include an operational amplifier having two input terminals and one output terminal. However, it should be understood that various types of amplifiers for implementing an embodiment of the present disclosure can be employed as long as it is possible to implement two amplifiers each having two input terminals and one output terminal.

[0061] The first switch 102/1 has one end connected to the input voltage V.sub.DD through the target resistance R.sub.sens, and the other end thereof is connected to the first input terminal of the first amplifier AMP1.

[0062] The second switch 102/2 has one end connected to the first output terminal of the first amplifier AMP1, and the other end thereof is connected to the third input terminal of the second amplifier AMP2.

[0063] The third switch 102/3 has one end connected to the input voltage V.sub.DD through the target resistance R.sub.sens, and the other end thereof is connected to the third input terminal of the second amplifier AMP2.

[0064] The fourth switch 102/4 has one end connected to the second output terminal of the second amplifier AMP2, and the other end thereof is connected to the first input terminal of the first amplifier AMP1.

[0065] Here, as shown in FIGS. 2A and 2B, when the logic state of the first clock signal CK is high, V.sub.ref voltage of the first differential voltage V.sub.amp1 is generated through the first switch 102/1 and V.sub.ref+ voltage of the second differential voltage V.sub.amp2 is generated through the second switch 102/2. These two differential voltages V.sub.amp1 and V.sub.amp2 are generated in the symmetrical forms to each other with respect to a reference voltage V.sub.ref. On the other hand, when the logic state of the second clock signal CKB is high, V.sub.ref voltage of the second differential voltage V.sub.amp2 is generated through the third switch 102/3 and V.sub.ref+ voltage of the first differential voltage V.sub.amp1 is generated through the fourth switch 102/4. In this case, the two differential voltages V.sub.amp1 and V.sub.amp2 are kept symmetric with respect to the reference voltage V.sub.ref with the values thereof changed. The first clock signal CK and the second clock signal CKB always have the opposite logic states. Accordingly, the logic states of the first switch 102/1 and the second switch 120/2 are always opposite to those of the third switch 102/3 and the fourth switch 102/4. In this regard, the first clock signal CK and the second clock signal CKB are generated by a clock signal generator to be described later. The operation process of the first switch 102/1, the second switch 102/2, the third switch 102/3 and the fourth 102/4 based on the clock signals of the clock signal generator will be described in detail in FIGS. 6 and 7.

[0066] The first resistance R.sub.std1 is disposed between the first input terminal and the first output terminal of the first amplifier AMP1, the second resistance R.sub.std2 is disposed between the third input terminal and the second output terminal of the second amplifier AMP2. Furthermore, the third resistance R.sub.std3 is disposed between the second switch 102/2 and the first output terminal of the amplifier AMP1, the fourth resistance R.sub.std4 is disposed between the fourth switch 102/4 and the second output terminal of the second amplifier AMP2.

[0067] Here, the first resistance R.sub.std1, the second resistance R.sub.std2, the third resistance R.sub.std3 and the fourth resistance R.sub.std4 are the reference resistances having the same resistance value.

[0068] FIGS. 2A and 2B show the examples of the output waveforms of the input mode converter 100 in FIG. 5.

[0069] Specifically, FIG. 2A illustrates a waveform of the first differential voltage V.sub.amp1 outputted from the first output terminal of the first amplifier AMP1 of the input mode converter 100. FIG. 2B illustrates a waveform of the second differential voltage V.sub.amp2 outputted from the second output terminal of the second amplifier AMP2 of the input mode converter 100. Here, if the logic state of the clock signal CK, for example, is high, the clock signal CKB is low which is opposite to the clock signal CK.

[0070] To obtain the output of the first differential voltage V.sub.amp1, an equivalent circuit condition may be applied between the input voltage V.sub.DD and the first amplifier AMP1 and between the input voltage V.sub.DD and the second amplifier AMP2.

[0071] FIG. 6 illustrates an operation process of the first to eighth switches 102/1 to 102/8 according to a clock signal and shows the example when the logic states of the first switch 102/1 and the second switch 102/2 are turned ON by the first clock signal CK whose logic state is high, and shows the example when the logic states of the third switch 102/3 and the fourth switch 102/4 are turned OFF by the second clock signal CKB whose logic state is low. The clock signal at this time is generated from the clock signal generator 106. The clock signal generator 106 may be included in the measuring device or separately provided outside the measuring device in the embodiment of the present disclosure and it should be understood that the configuration thereof can be selectively implemented.

[0072] If Kirchhoff's Current Law (KCL) is applied at the first inverting input terminal of the first amplifier AMP1, it can be expressed as the following Equation 1.

(V.sub.DDV.sub.ref)/R.sub.sens=(V.sub.refV.sub.amp1)/R.sub.std[Equation 1]

[0073] Therefore, when the first switch 102/1 and the second switch 102/2 are turned ON, the third switch 102/3 and the fourth switch 102/4 are turned OFF, the first differential voltage V.sub.amp1 can be expressed as the following Equation 2.

V.sub.amp1=V.sub.ref(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref)[Equation 2]

[0074] Here, V.sub.amp1 is the first differential voltage, V.sub.ref is a reference voltage, R.sub.std is the reference resistance, R.sub.sens is the target resistance, and V.sub.DD is the input voltage.

[0075] Further, in order to obtain the output of the second differential voltage V.sub.amp2, an equivalent circuit condition can be applied between the input voltage V.sub.DD and the first amplifier AMP1 and between the input voltage V.sub.DD and the second amplifier AMP2, which can be expressed as the following Equation 3 by applying KCL at the second input terminal of the amplifier when the first switch 102/1 and the second switch 102/2 are turned on, and the third switch 102/3 and the fourth switch 102/4 are turned off.

(V.sub.amp1V.sub.ref)/R.sub.std=(V.sub.refV.sub.amp2)/R.sub.std[Equation 3]

[0076] Equation 2 can be substituted into Equation 3 and the second differential voltage V.sub.amp2 can be expressed as the following Equation 4.

V.sub.amp2=V.sub.ref+(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref)[Equation 4]

[0077] On the other hand, as shown in FIG. 7, when the first switch 102/1 and the second switch 102/2 are turned OFF by the first clock signal CK whose logic state is low and the third switch 102/3 and the fourth switch 102/4 are turned ON by the second clock signal CKB, by applying KCL in the same way, the waveforms of the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 can be expressed as the following Equation 5 and Equation 6, respectively.

V.sub.amp1=V.sub.ref+(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref)[Equation 5]

V.sub.amp2=V.sub.ref(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref)[Equation 6]

[0078] As shown in the above equations, and FIGS. 2A and 2B, the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 have square wave forms symmetrical to each other with respect to a reference voltage V.sub.ref.

[0079] Referring back to FIG. 6, the chopper 200 in the differential mode converter 1 according to the embodiment of the present disclosure receives the first differential voltage V.sub.amp1 and the second differential voltage V.sub.amp2 from the input mode converter 100 and outputs the first chopping voltage V.sub.chop1 and the second chopping voltage V.sub.chop2 having DC voltage forms symmetrical to each other with respect to the reference voltage V.sub.ref.

[0080] As shown in FIG. 3, the chopper 200 includes the input terminal to which the first differential voltage V.sub.amp1 is inputted, the input terminal to which the second differential voltage V.sub.amp2 is inputted, the output terminal which outputs the first chopping voltage V.sub.chop1, the output terminal which outputs the second chopping voltage V.sub.chop2, and the fifth to the eighth switch 102/5 to 102/8.

[0081] Since the description of the chopper 200 is the same as that described in the embodiment of FIG. 1, detailed descriptions of the embodiments of FIGS. 5 to 7 will be omitted.

[0082] The low pass filter 300 removes the high frequency noise and offset of the first chopping voltage V.sub.chop1 and the second chopping voltage V.sub.chop2 outputted from the chopper 200.

[0083] The first chopping voltage V.sub.chop1 and the second chopping voltage V.sub.chop2 from which the high-frequency noise and offset are removed in the low-pass filter unit 300 are the first output voltage V.sub.lpf1 and the second output voltage V.sub.lpf2 in the symmetrical forms and having the same difference in magnitude with respect to the reference voltage V.sub.ref, and the first output voltage V.sub.lpf1 and the second output voltage V.sub.lpf2 are input signals of the analog-to-digital converter 400.

[0084] As shown in the waveform of FIG. 4, the difference in magnitude between the first output voltage V.sub.lpf1 and the second output voltage V.sub.lpf2, from which the high-frequency noise and offset are removed through the low-pass filter unit 300, with the reference voltage V.sub.ref centered, varies depending on the value of the input voltage V.sub.DD and the reference resistance R.sub.std. As the value of the reference resistance R.sub.std is increased, the difference in magnitude between the output voltages is increased even with a small change in R.sub.sens, which makes it easier for the analog-to-digital converter 400 to output the output voltage as digital bits to sense the resistance with higher resolution.

[0085] The analog-to-digital converter 400 outputs the digital signal corresponding to the resistance value of the target resistance 10 after analog-to-digital converting the first output voltage V.sub.lpf1 and the second output voltage V.sub.lpf2 provided from the low pass filter 300.

[0086] The analog-to-digital converter 400 includes an analog-to-digital converter having a predetermined bit resolution. For example, the analog-to-digital converter 400 includes a successive approximation resistor (SAR) analog-to-digital converter having a resolution of 12 bits.

[0087] If the analog-to-digital converter 400 has a resolution of 12 bits, the first output voltage V.sub.lpf1 can be expressed as the following Equation 7.

V.sub.lpf1=(V.sub.DD/2.sup.12)*(2.sup.11*D11+2.sup.10*D10+2.sup.9*D9+2.sup.8*D8+2.sup.7*D7+2.sup.6*D6+2.sup.5*D5+2.sup.4*D4+2.sup.3*D3+2.sup.2*D2+2.sup.1*D1+2.sup.0*D0)[Equation 7]

[0088] Since the first output voltage V.sub.lpf1 can be obtained by Equation 2 except that noise and offset are removed from the first differential voltage V.sub.amp1, the following Equation 8 can be obtained.

V.sub.lpf1=V.sub.ref(R.sub.std/R.sub.sens)(V.sub.DDV.sub.ref)[Equation 8]

[0089] The resistance value R.sub.sens of the target resistance 10 can be found by substituting the respective variables into the Equation 8.

[0090] For example, assuming that the input voltage V.sub.DD is 1.8V, the reference voltage V.sub.ref is 0.9V, and the binary code of the analog-to-digital converter 400 having a 12-bit resolution is 010111010001, it can be expressed as the following Equation 9.

V.sub.lpf1=(1.8/2.sup.12)*(2.sup.11*0+2.sup.10*1+2.sup.9*0+2.sup.8*1+2.sup.7*1+2.sup.6*1+2.sup.5*0+2.sup.4*1+2.sup.3*0+2.sup.2*0+2.sup.1*0+2.sup.0*1)=0.9(R.sub.std/R.sub.sens)(1.80.9)[Equation 9]

[0091] The resistance value R.sub.sens of the target resistance 10 can be expressed by the following Equation 10 from the calculation of Equation 9.

R.sub.sens=R.sub.std(0.9)/(0.2456)[Equation 10].

[0092] Assuming that the reference resistance R.sub.std in Equation 10 is 1 k, the resistance value R.sub.sens of the target resistance 10 can be accurately measured to 3.66 k.

[0093] FIG. 8 is a system diagram for performing actual measurement through the measuring device in FIG. 5, which includes the micro controller (MCU) 20 connected to the analog-digital converter 400 and the display unit 30.

[0094] The microcontroller 20 receives the digital signal from the analog-to-digital converter 400 and processes the input digital signal to be displayed through the display unit 30. For example, the microcontroller 20 can execute a process so that the resistance value R.sub.sens of the target resistance 10, 3.66 k, is accurately displayed through the display unit 30. In the microcontroller 20, a separate memory such as a flash memory or an EEPROM (Electrically Erasable Programmable Read Only Memory) is incorporated.

[0095] The display unit 30 can display the resistance value R.sub.sens of the target resistance 10, for example, the resistance value of 3.66 kunder the control of the microcontroller 20. For example, the display unit 30 includes any one of display devices such as a light emitting diode (LED) and a liquid crystal display (LCD).

[0096] According to the present embodiment as described above, by providing the differential mode converter 1 capable of converting the single mode input into the differential mode and applying it as a differential input signal for a chopper circuit, it is possible to input the single-ended mode while maintaining the function of the chopper circuit which minimizes the noise and offset voltage. Further, it is possible to improve measuring accuracy and resolution by converting an input signal in a single-ended mode into a differential mode and applying it as a differential input signal to the chopper circuit and performing an analog-to-digital conversion on the differential output signal of the chopper circuit passing through the low-pass filter.