Method and apparatus for processing data with polar encoding

Abstract

A method for performing polar coding is disclosed in the application. A data block is segmented into a plurality of first blocks. Difference in bit length between any two first blocks is not more than one bit. For each first block, one or more consecutive padding bits is added to obtain a second block of a bit length K if the bit length of the first block is less than K, so as to obtain a plurality of second blocks corresponding to the first blocks. N-K consecutive bits are added to each of the second blocks to obtain a plurality of third blocks. Polar encoding is performed on the third blocks.

Claims

1. A processing device for processing data in a communication system, comprising one or more circuitries capable of executing program instructions stored in a memory, wherein, by executing the program instructions, the one or more circuitries are configured to: obtain a data block comprising a plurality of data bits; perform a code block segmentation on the data block, to obtain a plurality of blocks when a quantity of bits of the data block is larger than K, wherein each block comprises K bits, one of the blocks comprises one or more padding bits that are added to make up the K bits, wherein K is a quantity of information bits and each block includes J cyclic redundancy check (CRC) bits, 0J<K; add N-K bits to each block to obtain a N-bit block, wherein each of the N-K added bits has a fixed preset value; and perform polar encoding on each of the N-bit blocks; wherein N is a length of a codeword of a polar code and a value of N is 2{circumflex over ()}n, and wherein n is an integer larger than 0, and N-K0.

2. The processing device according to claim 1, wherein the fixed preset value of each of the N-K bits is 0 or 1.

3. The processing device according to claim 1, wherein value of each padding bit is 0.

4. The processing device according to claim 1, further comprising the memory.

5. The processing device according to claim 1, wherein in performing polar encoding on each of the N-bit blocks, the one or more circuitries, by executing program instructions stored in the memory, are configured to: perform an interleaved mapping on the N-bit blocks to obtain a plurality of interleave mapped blocks; and perform polar encoding on each of the interleave mapped blocks.

6. A method for processing data in a communication system, comprising: with a processor executing program instructions stored in a memory, obtaining a data block comprising a plurality of data bits; performing a code block segmentation on the data block, to obtain a plurality of blocks when a quantity of bits of the data block is larger than K, wherein each block comprises K bits, one of the blocks comprises one or more padding bits that are added to make up the K bits, wherein K is a quantity of information bits and each block includes J cyclic redundancy check (CRC) bits, 0J<K; adding N-K bits to each block to obtain a N-bit block, wherein each of the N-K added bits has a fixed preset value; and performing polar encoding on each of the N-bit blocks; wherein N is a length of a codeword of a polar code and a value of N is 2{circumflex over ()}n, and wherein n is an integer larger than 0, and N-K0.

7. The method according to claim 6, wherein the fixed preset value of each of the N-K bits is 0 or 1.

8. The method according to claim 6, wherein value of each padding bit is 0.

9. The method according to claim 6, wherein performing polar encoding on each of the N-bit blocks comprises: performing an interleaved mapping on the N-bit blocks to obtain a plurality of interleave mapped blocks; and performing polar encoding on each of the interleave mapped blocks.

10. A non-transitory computer readable meduim stroing program instructions thereon for execution by a processing device in a communication system, wherein the program instructions cause the processing device to: obtain a data block comprising a plurality of data bits; perform a code block segmentation on the data block, to obtain a plurality of blocks when a quantity of bits of the data block is larger than K, wherein each block comprises K bits, one of the plurality of the blocks comprises one or more padding bits that are added to make up the K bits, wherein K is a quantity of information bits and each block includes J cyclic redundancy check (CRC) bits, 0J<K; add N-K bits to each block to obtain a N-bit block, wherein each of the N-K added bits has a fixed preset value; and perform polar encoding on each of the N-bit blocks; wherein N is a length of a codeword of a polar code and a value of N is 2{circumflex over ()}n, and wherein n is an integer larger than 0, and N-K0.

11. The non-transitory computer readable meduim according to claim 10, wherein the fixed preset value of the N-K bits is 0 or 1.

12. The non-transitory computer readable meduim according to claim 10, wherein value of each padding bit is 0.

13. The non-transitory computer readable meduim according to claim 10, wherein in performing polar encoding on each of the N-bit blocks, the program instructions cause the processing device to: perform an interleaved mapping on the N-bit blocks to obtain a plurality of interleave mapped blocks; and perform polar encoding on each of the interleave mapped blocks.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The following is a brief description of the accompanying drawings which are used in describing the embodiments of the present application.

(2) FIG. 1 is a flowchart of a method for performing polar encoding on a data block according to an embodiment of the present application.

(3) FIG. 2 is a functional block diagram of an apparatus for processing data according to an embodiment of the present application.

(4) FIG. 3 is a simplified block diagram of an apparatus for processing data according to an embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENTS

(5) The technical solution in the embodiments of the present invention will be described in conjunction with the accompanying drawings. It should be understood that, the technical solution in the embodiments of the present application can be applied to various communication systems, such as a global system of mobile communication (GSM), a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) system, a general packet radio service (GPRS), a long term evolution (LTE) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, a universal mobile telecommunication system (UMTS) and the like.

(6) FIG. 1 is a flowchart of a method for performing polar encoding on a data block according to an embodiment of the present application. The method of FIG. 1 is performed by an apparatus for processing data. The apparatus for processing data may be an apparatus for polar encoding.

(7) 101, code block segmentation is performed on a data block to obtain multiple first blocks, wherein a difference between numbers of bits of any two first blocks in the multiple first blocks is not more than 1 bit.

(8) 102, multiple second blocks are determined according to a padding bit and the multiple first blocks, wherein a quantity of bits of each of the multiple second blocks is K, and K is a quantity of information bits of a polar code. A value of the padding bit is a preset value such as, for example, 0 or 1.

(9) 103, consecutive N-K fixed bits are added to each of the multiple second blocks, so as to obtain multiple third blocks, wherein a value of each fixed bit is a preset value such as, for example, 0 or 1. A value of N is 2{circumflex over ()}n, where n is an integer larger than 0, and N-K0.

(10) 104, polar encoding is performed according to the multiple third blocks.

(11) In the embodiment of the present application, by segmenting the data block uniformly to the greatest extent and performing bit filling processing and fixed bit processing, polar encoding can be performed and performance difference between code blocks is reduced.

(12) In the embodiment of the present application, the data block may be a data block with a check bit for performing CRC check on a transport block added in front of the transport block or behind the transport block, or the data block may be a transport block with no CRC check bit added. If the data block is the data block with the check bit for performing CRC check on a transport block added in front of the transport block or added behind the transport block, one manner for CRC check is as follows: it is assumed that input bits (a transport block with no CRC check bit added) are a.sub.0, a.sub.1, a.sub.2, a.sub.3, . . . , a.sub.A-1, calculated CRC check bits are p.sub.0, p.sub.1, p.sub.2, p.sub.3, . . . , p.sub.L-1, and output bits (a transport block after CRC check being performed), where A is a length of an input sequence, namely, is a quantity of the input bits, L is a quantity of check bits, and B=A+L.

(13) One specific relationship between an output bit b.sub.k and an input bit a.sub.k and between the output bit b.sub.k and a check bit p.sub.k-A that needs to be added for performing CRC check on a transport block is:
b.sub.k=a.sub.k, when k=0,1,2, . . . ,A1;
b.sub.k=p.sub.k-A, when k=A,A+1,A+2, . . . ,A+L1;

(14) namely, the output bit is obtained by adding the check bit that needs to be added for performing CRC check on a transport block behind the input bit (the transport block with no CRC check bit added).

(15) One specific relationship between an output bit b.sub.k and an input bit a.sub.k-L and between the output bit b.sub.k and a check bit p.sub.k needing to be added for performing CRC check on a transport block is as follows:
b.sub.k=p.sub.k, when k=0,1,2, . . . ,L1;
b.sub.k=a.sub.k-L, when k=L,L+1,L+2, . . . ,A+L1;

(16) namely, the output bit is obtained by adding the check bit that needs to be added for performing CRC check on a transport block in front of the input bit (the transport block with no CRC check bit added).

(17) In the embodiment of the present application, if a data block is added with CRC check, a feedback indication of HARQ (hybrid automatic repeat request) may be determined.

(18) In step 101, when code block segmentation is performed on the data block to obtain the first blocks, it is assumed that the data block (i.e., the input bits) is b.sub.0, b.sub.1, b.sub.2, b.sub.3, . . . , b.sub.B-1, and B is a quantity of bits of the data block before the code block segmentation. K is a quantity of information bits of polar encoding and is a preset parameter. C is a quantity of the first blocks obtained after the code block segmentation. J is a quantity of check bits for CRC check in each first block, where 0JK. B is a total quantity of bits of the C first blocks. r is a sequential quantity of a first block, where 1rC.

(19) If the quantity of bits of the data block, B, is smaller than or equal to K, no CRC check bit is added to the data block, the quantity of output code blocks (i.e., the first blocks) C=1, the quantity of check codes of each code block J=0, and the total quantity of bits of the output bits B=B. In this case, the output bits are the input bits.

(20) If the quantity of bits of the data block, B, is larger than K, the data block is divided into C first blocks, where C=B/(KJ), and B=B+C.Math.J. J is a quantity of check bits for performing cyclic redundancy check (CRC) in the first block, where 0JK.

(21) A specific implementation manner of the embodiment of the present application is as follows: the quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C; and when B mod C<rC K.sub.r=B/C.

(22) A specific implementation manner of the embodiment of the present application is as follows: the quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C; and when B mod C<rC, K.sub.r=B/C.

(23) The data block is segmented relatively uniformly, so as to enable generally identical encoding efficiency for each data block, thereby reducing processing performance difference between code blocks.

(24) In step 102, when the multiple second blocks are determined according to the padding bit and the multiple first blocks, a quantity of bits of a first block is firstly determined, and whether to add the padding bit is determined according to the quantity of bits of the first block.

(25) If the quantity of bits of a first block is K, the first block may be taken as a second block, and the padding bit does not need to be added.

(26) If the quantity of bits K.sub.r of a first block is smaller than K, K-K.sub.r consecutive padding bits may be added to the first block, where K.sub.r represents the quantity of bits of the r.sup.th first block in the multiple first blocks, and 1rC. There may be two manners for adding the padding bits, one manner is to add K-K.sub.r consecutive padding bits in front of a first block, and the other manner is to add K-K.sub.r consecutive padding bits behind the first block. It should be noted that, when the padding bit is added to the first blocks, a filling manner should be kept uniformly. That is, if padding bits need to be added, the padding bits are collectively added in front of first blocks with a quantity of bits smaller than K, or the padding bits are collectively added behind the first blocks with the quantity of bits smaller than K. A situation that some padding bits are added in front of the first blocks and some padding bits are added behind the first blocks should not occur. In this case, the quantity of bits of each second block is K.

(27) In step 103, when the fixed bits are added to the multiple second blocks to obtain the multiple third blocks, the fixed bits need to be added according to a filling condition of the padding bit.

(28) If the manner for filling the padding bit is to add the padding bit in front of a first block with a quantity of bits smaller than K, then if a second block has a padding bit, consecutive N-K fixed bits are added at a position that is in front of the padding bits and is adjacent to the padding bit to obtain a third block; and if a second block does not have a padding bit, consecutive N-K fixed bits are added at a position that is in front of the second block and is adjacent to the second block to obtain a third block. In other words, no matter whether a second block has a padding bit or not, a manner for adding the fixed bits is to add consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block.

(29) If the manner for filling the padding bit is to add the padding bit behind a first block with a quantity of bits smaller than K, then if a second block has a padding bit, consecutive N-K fixed bits are added at a position that is behind the padding bit and is adjacent to the padding bit to obtain a third block; and if the second block does not have padding bit, consecutive N-K fixed bits are added at a position that is behind the second block and is adjacent to the second block to obtain a third block. In other words, no matter whether a second block has the padding bit or not, a manner for adding the fixed bits is to add consecutive N-K fixed bits at a position that is behind the second block and is adjacent to the second block.

(30) In one special situation, if all of the multiple second blocks do not have the padding bit, consecutive N-K fixed bits may be uniformly added at a position that is in front of each second block and is adjacent to each second block, so as to obtain the third blocks; or consecutive N-K fixed bits are uniformly added at a position that is behind each second block and is adjacent to each second block, so as to obtain the third blocks.

(31) Optionally, in step 104, polar encoding may be directly performed on the multiple third blocks. A method for polar encoding in the prior art may be referred to for a manner for performing polar encoding on the third blocks, which will not be repeated redundantly herein in the present application.

(32) In step 104, interleaved mapping may be further performed on the multiple third blocks to obtain multiple fourth blocks, and polar encoding is performed on the multiple fourth blocks.

(33) Further, when interleaved mapping is performed on the third blocks to obtain the fourth blocks, it may be processed according to the following manner: it is assumed that the r.sup.th third block in the multiple third blocks is C.sub.r=[c.sub.r0, c.sub.r1, c.sub.r2, c.sub.r3, . . . , c.sub.r(N-1)], where 1rC. An interleaved sequence .sub.N=(i.sub.0, i.sub.1, i.sub.2, . . . , i.sub.N-1) is firstly determined, where i.sub.x{0, K, N1}, 0xN1, and any two elements of the interleaved sequence are different from each other. Interleaved mapping processing is performed on the r.sup.th third block according to the interleaved sequence, wherein a relationship of the processed r.sup.th fourth block C.sub.r.sup.=[c.sub.r0.sup., c.sub.r1.sup., c.sub.r2.sup., c.sub.r3.sup., . . . , c.sub.r(N-1).sup.] and the r.sup.th third block is as follows: c.sub.ri.sub.x.sup.=c.sub.rx, x=0, 1, . . . , N1.

(34) FIG. 2 is a schematic block diagram of an apparatus for processing data 200 in an embodiment of the present application. The apparatus for processing data 200 may include a first obtaining unit 201, a determining unit 202, a second obtaining unit 203 and an encoding unit 204.

(35) The first obtaining unit 201 may perform code block segmentation on a data block to obtain multiple first blocks, wherein a difference between numbers of bits of any two first blocks in the multiple first blocks is not more than 1 bit.

(36) The determining unit 202 may determine multiple second blocks according to a padding bit and the multiple first blocks, wherein a quantity of bits of each of the multiple second blocks is K, K is the quantity of information bits of a polar code, and a value of the padding bit is a preset value such as, for example, 0 or 1.

(37) The second obtaining unit 203 may add consecutive N-K fixed bits to each of the multiple second blocks to obtain multiple third blocks, wherein a value of the fixed bit is a preset value, a value of N is 2{circumflex over ()}n, n is an integer larger than 0, and N-K0.

(38) The encoding unit 204 may perform polar encoding according to the third blocks.

(39) In the embodiment of the present application, the apparatus for processing data 200 may uniformly segment the data block to the greatest extent and perform bit filling processing and fixed bit processing, thereby enabling polar encoding to be performed and reducing performance difference between code blocks.

(40) In the embodiment of the present application, the data block may be a data block that is added with a check bit for performing CRC check on a transport block in front of the transport block or behind the transport block, or may be a transport block with no CRC check bit added.

(41) Optionally, when the first obtaining unit 201 performs the code block segmentation on the data block to obtain the multiple first blocks, if a quantity of bits of the data block, B, is larger than K, the first obtaining unit 201 divides the data block into C first blocks, wherein C=B/(KJ), and B=B+C.Math.J. J is a quantity of check bits for performing cyclic redundancy check (CRC) on the first block, and 0JK.

(42) A specific implementation manner of the embodiment of the present application is as follows: the quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C; and when B mod C<r.Math.C, K.sub.r=B/C.

(43) A specific implementation manner of the embodiment of the present application is as follows: the quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C; when B mod C<rC, K.sub.r=B/C.

(44) By segmenting the data block relatively uniformly, basically identical encoding efficiency of each data block is ensured, thereby reducing processing performance difference between the code blocks.

(45) When the determining unit 202 determines the multiple second blocks according to the padding bit and the multiple first blocks, the determining unit 202 may firstly determine a quantity of bits of the first block and determine whether to add the padding bit or not according to the quantity of the first blocks. If the quantity of bits of a first block is K, the determining unit 202 may take the first block as the second block and the padding bit does not need to be added. If the quantity of bits K.sub.r of a first block is smaller than K, the determining unit 202 may add K-K.sub.r consecutive padding bits to the first block, wherein K.sub.r is the quantity of bits of the r.sup.th first block in the multiple first blocks, and 1rC. There may be two manners for adding the padding bit, one manner is to add K-K.sub.r consecutive padding bits in front of the first block; and one is to add the K-K.sub.r consecutive padding bits behind the first block. It should be noted that, when the padding bit is added to the first block, the filling manner should be kept uniformly. That is, if padding bits need to be added, the padding bits are collectively added in front of first block with a quantity of bits smaller than K, or the padding bits are collectively added behind the first block with quantity of bits smaller than K. A situation that some padding bits are added in front of the first blocks and some padding bits are added behind the first blocks should not occur. In this case, the quantity of bits of each second block is K.

(46) When fixed bit(s) is added to the multiple second blocks to obtain the multiple third blocks, the second obtaining unit 203 may add the fixed bits according to a filling condition of the padding bit.

(47) If a manner for the second obtaining unit 203 to fill the padding bit is adding in front of the first block with a quantity of bits smaller than K, if the second block has the padding bit, the second obtaining unit 203 adds consecutive N-K fixed bits at a position that is in front of the padding bit and is adjacent to the padding bit to obtain the third block; and if the second block does not have the padding bit, the second obtaining unit 203 adds consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block to obtain the third block. Actually, no matter whether the second block has the padding bit or not, a manner for the second obtaining unit 203 to add the fixed bit(s) is to add consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block.

(48) If a manner for the second obtaining unit 203 to fill the padding bit is adding behind the first block with a quantity of bits smaller than K, if the second block has the padding bit, the second obtaining unit 203 adds consecutive N-K fixed bits at a position that is in front of the padding bit and is adjacent to the padding bit to obtain the third block; and if the second block does not have the padding bit, the second obtaining unit 203 adds consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block to obtain the third block. Actually, no matter whether the second block has the padding bit or not, a manner for the second obtaining unit 203 to add the fixed bit(s) is to add consecutive N-K fixed bits at a position that is behind the second block and is adjacent to the second block.

(49) In one special condition, if all of the multiple second blocks do not have the padding bit, the second obtaining unit 203 may uniformly add consecutive N-K fixed bits at a position that is in front of each second block and is adjacent to each second block, so as to obtain the third blocks; or the second obtaining unit 203 may uniformly add consecutive N-K fixed bits at a position that is behind each second block and is adjacent to each second block, so as to obtain the third blocks.

(50) Optionally, when the encoding unit 204 performs polar encoding on the multiple third blocks, the encoding unit 204 may directly perform polar encoding on the multiple third blocks. A polar encoding method in the prior art may be referred to for a polar encoding method for the third blocks, which will not be repeated redundantly in the present application.

(51) When the encoding unit 204 performs polar encoding on the multiple third blocks, the encoding unit 204 may firstly perform interleaved mapping on the multiple third blocks to obtain multiple fourth blocks, and perform polar encoding on the multiple fourth blocks.

(52) Further, when the encoding unit 204 performs interleaved mapping on the third blocks to obtain the fourth blocks, the encoding unit 204 may process in the following manner: it is assumed that the r.sup.th third block in the multiple third blocks is C.sub.r=[c.sub.r0, c.sub.r1, c.sub.r2, c.sub.r3, . . . , c.sub.r(N-1)], where 1rC. An interleaved sequence .sub.N=(i.sub.0, i.sub.1, i.sub.2, . . . , i.sub.N-1) is firstly determined, where i.sub.x{(0, K, N1}, 0xN1, and any two elements of the interleaved sequence are different from each other. The encoding unit 204 may perform interleaved mapping processing on the r.sup.th third block according to the interleaved sequence, wherein a relationship of the processed r.sup.th fourth block C.sub.r.sup.=[c.sub.r0.sup., c.sub.r1.sup., c.sub.r2.sup., c.sub.r3.sup., . . . , c.sub.r(N-1).sup.] and the r.sup.th third block is as follows: c.sub.ri.sub.x.sup.=c.sub.rx, x=0, 1, . . . , N1.

(53) FIG. 3 is a schematic block diagram of an apparatus for processing data 300 according to an embodiment of the present application. The apparatus for processing data 300 includes an input unit 301, an output unit 303, a processor 302 and a memory 304.

(54) The processor 302 is configured to perform code block segmentation on a data block to obtain multiple first blocks, wherein a difference between numbers of bits of any two first blocks in the multiple first blocks is not more than 1 bit.

(55) The memory 304 is configured to store an instruction that enables the processor 302 to perform code block segmentation on the data block to obtain the multiple first blocks.

(56) The processor 302 may further configured to determine multiple second blocks according to a padding bit and the multiple first blocks, wherein a quantity of bits of each of the multiple second blocks is K, and K is the quantity of information bits of a polar code. A value of the padding bit is a preset value such as, for example, 0 or 1. The memory 304 may further configured to store an instruction that enables the processor 302 to determine the multiple second blocks according to the padding bit and the multiple first blocks.

(57) The processor 302 may further configured to add consecutive N-K fixed bits to each of the multiple second blocks to obtain multiple third blocks, wherein a value of the fixed bit is a preset value such as, for example, 0 or 1. A value of N is 2{circumflex over ()}n, n is an integer larger than 0, and N-K0. The memory 304 may further configured to store an instruction that enables the processor 302 to add consecutive N-K fixed bits to each of the multiple second blocks to obtain the multiple third blocks

(58) The processor 302 may further configured to perform polar encoding according to the multiple third blocks. The memory 304 may further configured to store an instruction that enables the processor 302 to perform polar encoding according to the multiple third blocks.

(59) In the embodiment of the present application, the apparatus for processing data 300 may uniformly segment the data block to the greatest extent and perform bit filling processing and fixed bit processing, thereby enabling polar encoding to be performed and reducing performance difference between code blocks.

(60) The processor 302 controls an operation of the apparatus for processing data 300, and the processor 302 may also be called as a central processing unit (CPU). The memory 304 may include a read only memory (ROM) and a random access memory (RAM), and provides an instruction and data to the processor 302. A part of the memory 304 may further include a non-volatile random access memory (NVRAM). In a specific application, respective assemblies of the apparatus 300 are coupled together through a bus system 305, wherein besides a data bus, the bus system 305 may further include a power supply bus, a control bus and a status signal bus and/or the like. However, in order for clear illustration, various buses are marked as a bus system 305 in the figure.

(61) The method disclosed in the above-mentioned embodiment of the present application may be applied to the processor 302 or is implemented by the processor 302. The processor 302 may be an integrated circuit chip having signal processing capability. In an implementation process, respective steps of the above-mentioned method may be completed by an integrated logic circuit of a hardware or an instruction in a form of software in the processor 302. The above-mentioned processor 302 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate, a transistor logic device or a discrete hardware assembly. The processor 302 may achieve or implement the respective methods, steps and the logic block diagrams disclosed in the embodiment of the present application. The general-purpose processor may be a microprocessor, or the processor may be any common processor or the like. The steps of the method disclosed in the embodiment of the present application may be directly implemented by a hardware decoding processor, or is cooperatively implemented by a hardware and a software module in a decoding processor. The software module may be located in a mature storage media in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register or the like. The storage medium is located in the memory 304. The processor 302 reads information in the memory 304, and completes the steps of the above-mentioned method in combination with a hardware thereof.

(62) In the embodiment of the present application, the data block may be a data block that is added with a check bit for performing CRC check on a transport block in front of the transport block or behind the transport block, or may be a transport block with no CRC check bit added.

(63) When the processor 302 performs code block segmentation on the data block to obtain the multiple first blocks, if a quantity of bits of the data block, B, is larger than K, the processor 302 divides the data block into C first blocks, wherein C=B/(KJ), and B=B+C.Math.J. J is a quantity of check bits for performing cyclic redundancy check (CRC) on the first block, and 0JK.

(64) A specific implementation manner of the embodiment of the present application is as follows: a quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C, and when B mod C<rC, K.sub.r=B/C.

(65) A specific implementation manner of the embodiment of the present application is as follows: a quantity of bits of each of the C first blocks, K.sub.r, is as follows: when 1rB mod C, K.sub.r=B/C, when B mod C<rC, K.sub.r=B/C.

(66) By segmenting the data block relatively uniformly, basically identical encoding efficiency of each data block is ensured, thereby reducing processing performance difference between the code blocks.

(67) When the processor 302 determines the multiple second blocks according to the padding bit and the multiple first blocks, the processor 302 may firstly determine a quantity of bits of the first block and determine whether to add the padding bit or not according to the quantity of the first blocks. If the quantity of bits of a first block is K, the processor 302 may take the first block as the second block and the padding bit does not need to be added. If the quantity of bits K.sub.r of a first block is smaller than K, the processor 302 may add K-K.sub.r consecutive padding bits to the first block, wherein K.sub.r is the quantity of bits of the r.sup.th first block in the multiple first blocks, and 1rC. There may be two manners for adding the padding bit, one manner is to add K-K.sub.r consecutive padding bits in front of the first block; and one is to add the K-K.sub.r consecutive padding bits behind the first block. It should be noted that, when the padding bit is added to the first block, the filling manner should be kept uniformly. That is, if padding bits need to be added, the padding bits are collectively added in front of first block with a quantity of bits smaller than K, or the padding bits are collectively added behind the first block with a quantity of bits smaller than K. A situation that some padding bits are added in front of the first blocks and some padding bits are added behind the first blocks should not occur. In this case, the quantity of bits of each second block is K.

(68) When fixed bit(s) is added to the multiple second blocks to obtain the multiple third blocks, the processor 302 may add the fixed bits according to a filling condition of the padding bit.

(69) If a manner for the processor 302 to fill the padding bit is adding in front of the first block with a quantity of bits smaller than K, if the second block has the padding bit, the processor 302 adds consecutive N-K fixed bits at a position that is in front of the padding bit and is adjacent to the padding bit to obtain the third block; and if the second block does not have the padding bit, the processor 302 adds consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block to obtain the third block. Actually, no matter whether the second block has the padding bit or not, a manner for the processor 302 to add the fixed bit(s) is to add consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block.

(70) If a manner for the processor 302 to fill the padding bit is adding behind the first block with a quantity of bits smaller than K, if the second block has the padding bit, the processor 302 adds consecutive N-K fixed bits at a position that is in front of the padding bit and is adjacent to the padding bit to obtain the third block; and if the second block does not have the padding bit, the processor 302 adds consecutive N-K fixed bits at a position that is in front of the second block and is adjacent to the second block to obtain the third block. Actually, no matter whether the second block has the padding bit or not, a manner for the processor 302 to add the fixed bit(s) is to add consecutive N-K fixed bits at a position that is behind the second block and is adjacent to the second block.

(71) In one special condition, if all of the multiple second blocks do not have the padding bit, the processor 302 may uniformly add consecutive N-K fixed bits at a position that is in front of each second block and is adjacent to each second block, so as to obtain the third blocks; or the processor 302 may uniformly add consecutive N-K fixed bits at a position that is behind each second block and is adjacent to each second block, so as to obtain the third blocks.

(72) When the processor 302 performs polar encoding on the multiple third blocks, the processor 302 may directly perform polar encoding on the multiple third blocks. A polar encoding method in the prior art may be referred to for a polar encoding method for the third blocks, which will not be repeated redundantly in the present application.

(73) When the processor 302 performs polar encoding on the multiple third blocks, the processor 302 may firstly perform interleaved mapping on the multiple third blocks to obtain multiple fourth blocks, and perform polar encoding on the multiple fourth blocks.

(74) Further, when the processor 302 performs interleaved mapping on the third blocks to obtain the fourth blocks, the processor 302 may process in the following manner: it is assumed that the r.sup.th third block in the multiple third blocks is C.sub.r=[c.sub.r0, c.sub.r1, c.sub.r2, c.sub.r3, . . . , c.sub.r(N-1)], where 1rC. An interleaved sequence .sub.N=(i.sub.0, i.sub.1, i.sub.2, . . . , i.sub.N-1) is firstly determined, where i.sub.x{0, K, N1}, 0xN1, and any two elements of the interleaved sequence are different from each other. The processor 302 may perform interleaved mapping processing on the r.sup.th third block according to the interleaved sequence, wherein a relationship of the processed r.sup.th fourth block C.sub.r.sup.=[c.sub.r0.sup., c.sub.r1.sup., c.sub.r2.sup., c.sub.r3.sup., . . . , c.sub.r(N-1).sup.] and the r.sup.th third block is as follows: c.sub.ri.sub.x.sup.=c.sub.rx, x=0, 1, . . . , N1.

(75) It should be understood that, in various embodiments of the present application, values of the sequential numbers of the above-mentioned processes do not represent an execution order. An execution order of the processes should be determined by functionalities and internal logics thereof, and should not constitute any limitation to implementation processes of the embodiments of the present application.

(76) To those of ordinary skills in the art, units and algorithm steps of respective examples described in the embodiments disclosed in the present disclosure may be implemented by an electronic hardware or a combination of a computer software and an electronic hardware. Whether these functions are implemented in form of hardware or software is determined by a specific application and design constraint condition of the technical solutions. Professionals may implement the described functions by using different methods for each specific application, but this implementation should not be considered as beyond the scope of the present application.

(77) Those skilled in the art may clearly understand that, for convenience and concision of description, the specific working processes of the system, apparatus and units described above may refer to corresponding processes in the foregoing method embodiments, and will not be repeated redundantly herein.

(78) In several embodiments provided in the present application, it should be understood that, disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely exemplary, e.g., dividing of the units is merely a logic function dividing, other dividing manners may be adopted in a practical implementation. For example, multiple units or components may be combined or integrated to another system, or some features may be omitted or not implemented. From another point of view, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection of devices or units through some interfaces, and may be in electrical, mechanical or other form.

(79) The units described as separate components may be separated physically or not, components displayed as units may be physical units or not, namely, may be located in one place, or may be distributed on multiple network units. A part of or all of the units may be selected to achieve the purposes of the technical solutions in the embodiments according to actual demand.

(80) In addition, the respective functional units in the embodiments of the present application may be integrated in a processing unit, or the respective units separately physically exist, or two or more units are integrated in one unit.

(81) If the function is implemented in a form of a software functional unit and is sold or used as an independent product, it may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application substantially, or a part contributing to the prior art, or a part of the technical solutions, may be implemented in a form of a software product. The computer software product is stored in a storage medium, and includes several instructions enabling a computer device (may be a personnel computer, a server, or a network device, etc.) to execute all or a part of the steps of the methods in the embodiments of the present application. The foregoing storage medium includes a variety of media capable of storing program codes such as, for example, a USB disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk or the like.

(82) The foregoing descriptions are merely specific implementation manners of the present application, rather than limiting the protection scope of the present application. Those skilled in the art could readily think of variations or substitutions within the disclosed technical scope of the present application, and these variations or substitutions shall fall within the protection scope of the present application. Accordingly, the protection scope of the present application shall be defined by the following claims.