Method for producing a plurality of semiconductor chips having recesses in the device layer

Abstract

The invention relates, inter alia, to a method for producing a plurality of semiconductor chips, the method comprising the following steps: providing a substrate (1); applying a semiconductor layer sequence (2) to the substrate (1); generating a plurality of recesses (6) in the semiconductor layer sequence (2) on the side of the semiconductor layer sequence (2) that is facing away from the substrate (1); detaching the substrate (1) from the semiconductor layer sequence (2); thinning the semiconductor layer sequence (2) on the side that was facing the substrate (1) prior to detaching the substrate (1).

Claims

1. Method for producing a plurality of semiconductor chips comprising the following steps: providing a substrate, applying a semiconductor layer sequence on the substrate, generating a plurality of recesses in the semiconductor layer sequence from the side of the semiconductor layer sequence facing away from the substrate, removing the substrate from the semiconductor layer sequence, thinning the semiconductor layer sequence from the side facing the substrate before removal of the substrate, wherein the recesses do not completely penetrate the semiconductor layer sequence before thinning of the semiconductor layer sequence respectively, and the recesses penetrate the semiconductor layer sequence completely after thinning of the semiconductor layer sequence, respectively, and wherein the semiconductor layer sequence is a radiation-emitting semiconductor layer sequence or a nitride semiconductor layer sequence.

2. Method according to claim 1, wherein before thinning of the semiconductor layer sequence a residue of the material of the semiconductor layer sequence remains between the lowermost point of the recesses and the substrate, so that the semiconductor layer sequence has a minimum thickness (D).

3. Method according to claim 1, wherein the recesses are tapering towards the substrate before removal of the substrate.

4. Method according to claim 1, wherein the recesses are generated along a chip grid.

5. Method according to claim 1, wherein the thinning of the semiconductor layer sequence is performed by roughening the semiconductor layer sequence, by means of which roughenings are generated on the side of the semiconductor layer sequence originally facing the substrate.

6. Method according to claim 1, wherein after generating the plurality of the recesses an isolation layer sequence is generated, the isolation layer sequence covering the semiconductor layer sequence on surfaces facing the recesses.

7. Method according to claim 6, wherein during thinning of the semiconductor layer sequence the isolation layer sequence is exposed in some places.

8. Method according to claim 1, wherein a carrier is generated on the side of the semiconductor layer sequence facing away from the substrate before removing the substrate, wherein the carrier includes a plurality of first contactings, a plurality of second contactings, and the shaped body, wherein the shaped body surrounds the contactings laterally.

9. Method according to claim 8, wherein the shaped body extends in the plurality of recesses and fills them at least in some places.

10. Method according to claim 8, wherein a singulation is performed in a plurality of semiconductor chips along separation lines, wherein at least some of the separation lines extend through a recess and the shaped body, wherein each singulated semiconductor chip is assigned at least one first contacting and at least one second contacting.

11. Method for producing a plurality of semiconductor chips comprising the following steps: providing a substrate, applying a semiconductor layer sequence on the substrate, generating a plurality of recesses in the semiconductor layer sequence from the side of the semiconductor layer sequence facing away from the substrate, removing the substrate from the semiconductor layer sequence, thinning the semiconductor layer sequence from the side facing the substrate before removal of the substrate, wherein before thinning of the semiconductor layer sequence a residue of the material of the semiconductor layer sequence remains between the lowermost point of the recesses and the substrate, so that the semiconductor layer sequence has a minimum thickness (D), and wherein the semiconductor layer sequence is a radiation-emitting semiconductor layer sequence or a nitride semiconductor layer sequence.

12. Method for producing a plurality of semiconductor chips comprising the following steps: providing a substrate, applying a semiconductor layer sequence on the substrate, generating a plurality of recesses in the semiconductor layer sequence from the side of the semiconductor layer sequence facing away from the substrate, removing the substrate from the semiconductor layer sequence, thinning the semiconductor layer sequence from the side facing the substrate before removal of the substrate, wherein a carrier is generated on the side of the semiconductor layer sequence facing away from the substrate before removing the substrate, wherein the carrier includes a plurality of first contactings, a plurality of second contactings, and the shaped body, wherein the shaped body surrounds the contactings laterally, and wherein the semiconductor layer sequence is a radiation-emitting semiconductor layer sequence or a nitride semiconductor layer sequence.

Description

BRIEF DESCRIPTION OF THE FIGURES:

(1) The method described here and the semiconductor chip described here will be explained in more detail in the following by means of exemplary embodiments and the corresponding figures.

(2) With reference to FIGS. 1A, 1B, 1C, 1D, 1E, 1F, an exemplary embodiment of the method described here is explained in more detail.

(3) With reference to FIGS. 2A, 2B, 2C, exemplary embodiments of the radiation emitting semiconductor chips described here are explained in more detail.

(4) Identical, similar elements or elements seemingly identical are indicated by the same reference numerals in the figures. The figures and the dimensions of the elements displayed in the figures are not intended to be true to scale. The single elements may be rather shown in a larger size to enhance visibility and/or understanding.

(5) FIGS. 1A to 1F describe an exemplary embodiment of the method described here by using schematic section views.

(6) Reference is made to FIG. 1A, which schematically illustrates that at first a growth substrate 1 is provided. The growth substrate 1 may for example be sapphire substrate. A semiconductor layer sequence 2 is deposited on the growth substrate 1 by using an epitaxial process, for example, the semiconductor layer sequence 2 is based on GaN, for example. The semiconductor layer 2 includes a first region 21, which is formed as n-conducting, for example, and an active region 22, where an electromagnetic radiation may be generated during operation, and a second region 23, which is formed as p-conducting, for example.

(7) On the side of the semiconductor layer sequence 2 facing away from the substrate 1 a first metal layer sequence 3 may be formed, which at least includes one layer that is formed by a metal or which includes a metal. The first metal layer sequence 3 may include a reflecting metal, like silver, for example.

(8) In a next step of the method, which is also described referring to FIG. 1A, vias 5 and recesses 6 are generated. The vias 5 extend through the first metal layer sequence 3, the second region 23, the active region 22 into the first region 21. In the completed semiconductor chip, these vias 5 provide an n-side contacting of the semiconductor chip.

(9) The recesses 6 also extend in the first region 21, however the recesses 6 extend deeper into the first region 21 than the vias 5, and the recesses 6 are formed with a larger width in the illustrated cross-section of the semiconductor layer sequence. The depth of the recesses 6 amounts from at least 4 m to maximum 5 m, for example. The minimum width of the recesses amounts from at least 20 m to maximum 25 m, in particular 25 m, for example.

(10) Here, the recesses 6 do not completely penetrate the semiconductor layer sequence 2, but a region of the semiconductor layer sequence having a residual thickness D remains, due to which the recesses 6 are spaced apart from the substrate 1.

(11) In a further step of the method, an isolation layer sequence 4 is formed on the side facing away from the substrate, which may for example be generated by using an ALD and/or CVD process. The isolation layer sequence 4 comprises for example a silicon nitride layer, which directly abuts on the first metal layer sequence 3 and the semiconductor body 2. In addition, the isolation layer sequence 4 may comprise additional semiconductor layers and/or metal layers, and may be formed as reflecting, for example. The isolation layer sequence 4 includes first holes 41 in the region of the vias 5, where the first region 21 of the semiconductor layer sequence 2 may be accessed. In addition, the isolation layer sequence 4 includes second holes 42, in which the first metal layer sequence 3 is freely accessible. Said holes 41, 42 allow the n- and/or p-side contacting of the semiconductor chip in the completed semiconductor chip.

(12) In a further step of the method, FIG. 1B, a second metal layer sequence 7 is deposited on the isolation layer sequence 4. The metal layer sequence 7 contacts the first metal layer sequence 3 in the region of the second vias 42 and forms second contacts 72 here. In the region of the vias 5, the second metal layer sequence 7 contacts the first region 21 of the semiconductor layer sequence 2 for n-side contacting of the first contacts 71.

(13) The second metal layer sequence 7 may have a mechanically enforcing function for the semiconductor body. In addition, the second metal layer sequence 7 may at least include a layer which functions as seed layer in order to produce contactings later in the method. The second metal layer sequence 7 may for example be formed by metals, like nickel and/or copper.

(14) In FIG. 1B is shown that the recesses 6 may either be filled with material of the second metal layer sequence 7, or there is no material of the metal layer sequence left.

(15) In the next step of the method, FIG. 1C, the carrier 89 is created. Hereto, for example, the shaped body 8 is generated on the lower side facing away from the substrate, wherein the shaped body 8 abuts in some places directly on the first metal layer sequence 3 and the second metal layer sequence 7. The shaped body 8 is formed of an electrically isolating material, for example an epoxy resin.

(16) In the shaped body 8 recesses are created or released, which are filled by using material of the first contactings 91 and second contactings 92, for example by electroplating. Here, the second metal layer sequence 7 may function as seed layer for the contactings 91, 92 in some places. In particular, during application of the shaped body 8, it may be inserted into the recesses 6, thus they are filled with material of the shaped body 8.

(17) In the step of the method described referring to FIG. 1D, the growth substrate 1 is removed from the semiconductor layer sequence 2 by a laser lift-off process, for example.

(18) In the next step of the method, FIG. 1E, the thinning of the semiconductor layer sequence 2 by KOH etching is performed, thus roughenings 24 of the semiconductor layer sequence 2 are generated on the side facing away from the carrier 89. In addition, the semiconductor layer sequence 2 is thinned in a way that the recesses 6 and along with them the isolation layer 4 and/or the shaped body 8 and/or the second metal layer sequence 7 are exposed, for example.

(19) In the last step of the method, FIG. 1F, a singulation in separate semiconductor chips along the separation lines 101 is performed, which extend through the recesses and the carrier 89. Here, the composition consisting of semiconductor layer sequence 2, metal layer sequences 3, 7, and carrier 89 may be attached on an auxiliary carrier.

(20) However, it is not shown in the FIGS. 1A to 1F, that the recesses preferably taper in a direction facing away from the carrier 89, thus the semiconductor layer sequence 2 expands in the direction of the roughenings 24 and thus towards the radiation exit side 2a.

(21) This is shown in detail in the FIGS. 2A to 2C. Here section views of exemplary embodiments of the radiation-emitting semiconductor chip described here are shown, which includes the semiconductor layer sequence 2. The semiconductor layer sequence 2 includes the active region 22, in which electromagnetic radiation is generated during operation of the semiconductor chip, which exits at least in parts on the radiation exit side, which includes the roughenings 24. The semiconductor layer sequence further comprises a side surface 2c, which at first includes a first angle in the vertical direction R towards the radiation exit side 2a having a which value higher than 90, and further along the side surface towards the radiation exit side 2a an angle in the vertical direction R having a value smaller than 90.

(22) In the exemplary embodiment of FIG. 2A it is thus shown, that the isolation layer sequence 4 will not be damaged during thinning of the semiconductor layer sequence 2, as it is formed using SiNx, for example, which forms an etching step for KOH etching. That is, the isolation layer sequence 4 remains unchanged, and the flanks of the semiconductor layer 2 sequence having different directions coincide at contact point 102. Generally, in this exemplary embodiment the semiconductor layer sequence 2 projects beyond the isolation layer sequence and the filling of the recesses 6 at least in the region of the roughenings 24.

(23) This is also true for the exemplary embodiment of FIG. 2B, where the isolation layer sequence 4 is partly removed by thinning of the semiconductor layer sequence, thus underlying materials become exposed. This may cause the isolation layer sequence 4 to decrease, thus a gap exists between the filling of the recess 6, like for example, the shaped body 8 or the second metal layer sequence 7 and the semiconductor body 2.

(24) In the exemplary embodiment of FIG. 2C, the semiconductor layer sequence is arranged on the radiation exit surface 2a thereof completely underneath the filling of the recess and the isolation layer sequence 4. That is, in this exemplary embodiment, the semiconductor layer sequence 2 has been thinned to a particular high depth. This way, the filling of the recess may for example be a mechanical protection of the semiconductor layer sequence 2, however the optical characteristics of such a radiation-emitting semiconductor chip are deteriorated.

(25) The invention shall not be limited by the description of the exemplary embodiments. Rather, the invention comprises any new feature and any combination of features, which in particular includes any combination of features in the claims, even if this feature or this combination is not be explicitly specified in the claims or in exemplary embodiments.

(26) Priority is claimed of the German application 102015111721.5, the disclosure of which is included by reference.

LIST OF REFERENCE NUMERALS

(27) 1 Substrate 2 Semiconductor layer sequence 2a Radiation exit side 2c Side surface 21 First region 22 Active region 23 Second region 24 Roughening 3 First metal layer sequence 4 Isolation layer sequence 41 First hole 42 Second hole 5 Via 6 Recess 7 Second metal layer sequence 71 First contact 72 Second contact 8 Shaped body 89 Carrier 91 First contacting 92 Second contacting 100 Auxiliary carrier 101 Separation line 102 Contact point 103 Auxiliary line First angle Second angle D Minimum thickness R Vertical direction