Method for obtaining a semi-polar nitride layer on a crystalline substrate

Abstract

A process allowing at least one semipolar layer of nitride to be obtained, which layer is obtained from a least one among gallium, indium and aluminum on a top surface of a single-crystal layer based on silicon, wherein the process comprises the following steps: etching, from the top surface of the single-crystal layer, a plurality of parallel grooves comprising at least two opposite inclined facets, at least one of two opposite facets having a crystal orientation; masking the top surface of the single-crystal layer such that the facets having a crystal orientation are not masked; and epitaxial growth of the semipolar layer of nitride from the not masked facets; wherein the etching is carried out on a stack comprising the single-crystal layer and at least one stop layer that is surmounted by the single-crystal layer and wherein the etching etches the single-crystal layer selectively with respect to the stop layer so that the etching stops on contact with the stop layer.

Claims

1. A process allowing at least one semipolar layer of nitride to be obtained, which layer is obtained from a least one among gallium, indium and aluminum on a top surface of a single-crystal layer based on silicon or based on germanium, said process comprising the following steps: etching, from the top surface of the single-crystal layer, a plurality of parallel grooves that mainly extend in a first direction, each groove comprising at least two opposite inclined facets, at least one of said two opposite facets having a {111} crystal orientation; forming a mask on top of the top surface of the single-crystal layer such that the facets opposite said facets having a {111} crystal orientation are masked and that said facets having a {111} crystal orientation are not masked; and epitaxial growth of said semipolar layer of nitride from said not masked facets; wherein said etching is carried out on a stack comprising the single-crystal layer and at least one stop layer (420) that is surmounted by the single-crystal layer and wherein said etching etches said single-crystal layer selectively with respect to said stop layer so that said etching stops on contact with said stop layer, and wherein the single-crystal layer has a thickness smaller than or equal to 900 nm (10.sup.9 meters).

2. The process as claimed in claim 1, wherein the thickness of the single-crystal layer is such that, in the etching step, the two opposite inclined facets of a given groove reach the stop layer without meeting.

3. The process as claimed in claim 1, wherein said first direction, in which the grooves extend, corresponds to a direction common to the plane of said top surface and to the <111> plane.

4. The process as claimed in claim 1, wherein said step of epitaxial growth comprises: a first epitaxial growth of a material based on aluminum nitride from said not masked facets that have a {111} crystal orientation; then at least one second epitaxial growth of a material based on gallium nitride from said material based on aluminum nitride.

5. The process as claimed in claim 1, wherein the stop layer is configured to allow an epitaxial growth from the single-crystal layer without epitaxial growth from the stop layer.

6. The process as claimed in claim 1, wherein the single-crystal layer makes direct contact with the stop layer.

7. The process as claimed in claim 1, wherein the stack comprises a carrier layer surmounted by the stop layer.

8. The process as claimed in claim 7, wherein the stop layer makes direct contact with the carrier layer.

9. The process as claimed in claim 1, wherein the stop layer is obtained by oxidizing one surface at least of the carrier layer.

10. The process as claimed in claim 1, wherein the stop layer is a layer chosen from: a layer of oxide, a layer of SiC, and a layer of Al.sub.2O.sub.3.

11. The process as claimed in claim 1, wherein the single-crystal layer has a thickness comprised between 2 nm (10.sup.9 meters) and 900 nm.

12. The process as claimed in claim 1, wherein the single-crystal layer has a thickness smaller than or equal to 750 nm.

13. The process as claimed in claim 12, wherein the single-crystal layer has a thickness smaller than or equal to 600 nm.

14. The process as claimed in claim 1, wherein the single-crystal layer has a thickness comprised between 50 nm and 600 nm.

15. The process as claimed in claim 1, wherein the single-crystal layer is a layer obtained beforehand on a donor substrate then added to the stop layer.

16. The process as claimed in claim 1, wherein the V/III molar ratio of said material containing nitride and at least one among gallium, indium and aluminum is comprised between 100 and 2000.

17. The process as claimed in claim 16, wherein the V/III molar ratio of said material containing nitride and at least one among gallium, indium and aluminum is comprised between 300 and 500.

18. The process as claimed in claim 1, wherein the step of forming a mask comprises an angular deposition of a masking material, which deposition is carried out such that all the single-crystal layer is covered with the exception of said facets that have a {111} crystal orientation.

19. The process as claimed in claim 18, wherein the masking material comprises at least one among the following materials: silicon oxide, silicon nitride, and titanium nitride.

20. The process as claimed in claim 1, wherein the nitride is gallium nitride.

21. The process as claimed in claim 1, wherein the plurality of parallel grooves has a pitch p1 that is comprised between 50 nm and 20 m.

22. The process as claimed in claim 1, wherein the parallel grooves of the plurality of parallel grooves mainly extend in a first direction, and the process also comprises the following steps, which are executed after the step of obtaining the plurality of parallel grooves and before the step of epitaxial growth of the single-crystal layer: etching a plurality of parallel trenches that extend in a second direction having undergone a rotation with respect to said first direction, and that thus interrupt the continuous grooves so as to form a matrix-array of individual facets each having a {111} single-crystal orientation; the trenches and the grooves each having a bottom, the bottom of the trenches being located at the same depth or below the bottom of the grooves; and wherein, during said epitaxial growth step, said material grows solely from said individual facets that have a {111} crystal orientation and that form said matrix-array.

23. The process as claimed in claim 22, wherein said first and second directions define an angle that is larger than 40.

24. The process as claimed in claim 22, wherein the plurality of parallel grooves has a pitch p1 and wherein the plurality of parallel trenches have a pitch p2 that is larger than $\frac{p1*0.8}{2.5}.$

25. The process as claimed in claim 22, wherein the plurality of parallel grooves has a pitch p1 and wherein the plurality of parallel trenches has a pitch p2 that is smaller than 1.1*p1.

26. A microelectronic device comprising a single-crystal layer and a semipolar layer of at least one layer of a nitride of at least one among gallium, indium and aluminum on a top surface of the single-crystal layer, the single-crystal layer comprising a plurality of parallel grooves, each groove comprising at least two opposite inclined facets each forming a continuous band, at least one of said two opposite facets having a {111} crystal orientation; said nitride layer making direct contact with the facets having a {111} crystal orientation; wherein the single-crystal layer surmounts a stop layer and wherein each groove extends from a top face of the stop layer and passes right through the single-crystal layer and the single-crystal layer has a thickness smaller than or equal to 900 nm (10.sup.9 meters).

27. The device as claimed in claim 26, wherein the grooves have a flat bottom that is formed by the top face of the stop layer.

28. A light-emitting diodes comprising a microelectronic device as claimed in claim 26.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Aims, objects, features and advantages of the invention will become more clearly apparent from the detailed description of one embodiment of the latter, which embodiment is illustrated by the following accompanying drawings, in which:

(2) FIG. 1 is a graph showing the severity of polarization effects as a function of crystal orientation.

(3) FIG. 2 shows the results of growth of a nitride layer obtained by epitaxial lateral overgrowth (ELO).

(4) FIGS. 3a-3f illustrate the steps of a process for localized heteroepitaxial semipolar growth of a layer of GaN.

(5) FIGS. 4a-4i illustrate the steps of an example process according to the invention for obtaining localized heteroepitaxial semipolar growth of a layer of GaN.

(6) The figures are given by way of example and do not limit the invention. They are schematic conceptual representations intended to facilitate the comprehension of the invention and are therefore not necessary to the same scale as practical applications. In particular, the relative thicknesses of the various layers and films are not representative of reality.

DETAILED DESCRIPTION OF THE INVENTION

(7) It will be noted that, in the context of the present invention, the terms on, surmounts, covers and subjacent or their equivalents do not mean in contact with. Thus, for example, the deposition of a first layer on a second layer, does not necessarily mean that the two layers make direct contact with each other but means that the first layer at least partially covers the second layer while being either directly in contact therewith or being separated therefrom by at least one other layer or at least one other element.

(8) In the following description, thickness or height is measured in a direction perpendicular to the main faces of the various layers. In the figures, thickness or height is measured along the vertical.

(9) Likewise, when it is indicated that an element is located plumb with another element, this means that these two elements are both located on the same line perpendicular to the main plane of the substrate, i.e. on a given line that is oriented vertically in the figures.

(10) The general principle of the process according to the invention will now be described, then nonlimiting embodiments will be detailed with reference to FIGS. 4a to 4h.

(11) This process provides a way of solving the problems posed by the growth of an epitaxial layer of semipolar or nonpolar orientation, of gallium nitride (GaN) and of nitride alloys including indium (In) and aluminum (Al).

(12) The process of the invention advantageously makes provision to use processed silicon substrates of SOI type, SOI being the acronym for silicon-on-insulator. There are many well-known techniques for producing such substrates, which comprise a thin surface layer of silicon, preferably single-crystal silicon, which rests on a continuous insulating layer, which will play the role of the stop layer 420. The latter is often silicon oxide (SiO.sub.2).

(13) The single-crystal layer may thus be based on silicon, i.e. it may consist entirely of silicon or indeed it may comprise silicon and at least one other species. According to another embodiment, the single-crystal layer is based on germanium. In the rest of the description, the invention will be described with reference to a single-crystal layer based on silicon. The embodiments described below are applicable to a single-crystal layer based on germanium.

(14) Generally, the insulating layer rests on a thick carrier, called the carrier layer below, intended to provide the assembly with a sufficient mechanical rigidity. The thick or bulk carrier, also called a base or bulk wafer, is also often made of silicon.

(15) More generally, the invention makes use of substrates of SOX type, abbreviation used to designate any type of SOI substrate, i.e. substrates in which the insulating layer and the thick carrier may be made of materials other than silicon (Si) and its oxide (SiO.sub.2). Thus, the carrier layer may be made of alumina (Al.sub.2O.sub.3) or silicon carbide (SiC) or even of any other material commonly used in the microelectronics industry.

(16) The single-crystal surface layer, which is for example made of silicon, may be obtained using various known processes such as, for example, the well-known method called the smart-cut method. In this method, the surface layer is obtained from what is called a donor substrate. The surface layer is then added to the carrier layer by molecular bonding of an insulating layer, generally made of SiO.sub.2, that was, before the addition, created on the surface of the carrier layer.

(17) The crystal orientation of the single-crystal layer must be such that it will allow the desired semipolar orientation to be obtained during the subsequent growth of the nitride layer (of GaN for example) as was described above. The following table summarizes the various crystal orientations of the silicon surface layer that are liable to be suitable:

(18) TABLE-US-00001 Semipolar Orientation of the Si top orientation of the layer: about: toward: GaN: (001) disorientation 7 [1-10] [110] [10-11] (114) disorientation 1 [110] [110] [20-21] (111) disorientation 4 [0-1-1] [211] [20-21] (113) [11-22] or [30-31]

(19) The crystal orientation and nature of the carrier layer or base wafer made of silicon or of one of the other materials mentioned above does not directly affect those of the nitride layer since the insulating layer playing the role of the stop layer 420 forms an interface between the carrier layer and the single-crystal surface layer. Regarding the production of the nitride layer (of GaN for example), only the single-crystal surface layer need be considered.

(20) The choice of the material from which the carrier layer is made will possibly be dictated by other considerations such as its thermal conductivity, its thermal expansion coefficient, its transparency and other physical parameters that may depend on the particular use that is made of the invention. If the carrier layer is made of silicon, its crystal orientation is commonly {100} or {111}.

(21) The thickness of the oxide layer or, more generally, that of the insulating layer created before addition of the single-crystal surface layer is also not a factor that will have a direct influence on the result of the implementation of the process according to the invention. It is commonly comprised in a range of values extending from 150 nm (nanometer=10.sup.9 m) to 900 nm (m=10.sup.6 m) and more generally between 2 nm (10.sup.9 meters) and 900 nm and preferably between 5 nm and 500 nm and preferably between 10 nm and 50 nm.

(22) According to one embodiment, the single-crystal layer has a thickness smaller than or equal to 750 nm, preferably smaller than or equal to 600 nm, preferably smaller than or equal to 500 nm and preferably smaller than or equal to 300 nm. These thicknesses allow the effect of nucleation by melt-back etching to be even more considerably minimized.

(23) This insulating layer is chosen to be such that it forms a stop layer 420 during the etching that reveals the facets etched in the single-crystal surface layer. Typically, the etching is carried out via a chemical etch that etches the single-crystal surface layer with a high selectivity with respect to the stop layer 420.

(24) The stop layer 420 is not necessarily insulating although the use of known processes for forming SOI-type structures is advantageous and these processes conventionally employ an insulating layer. Advantageously, the stop layer is amorphous. It does not react chemically with said semipolar nitride layer.

(25) The stop layer 420 advantageously allows localized growth on the {111} facets defined by the single-crystal surface layer. More precisely, the growth of GaN on the chosen material must not be possible, in order to obtain a selective growth only on the {111} oriented facets revealed by the chemical etch. Silicon oxide (SiO.sub.2) has the advantages of being simple to use and of having a good selectivity with respect to silicon in many etch chemistries. Moreover, it lends itself well to the molecular bonding carried out during the addition of the single-crystal surface layer. Silicon nitride (SiN) is also an advantageous material for forming the stop layer 420. Preferably, the stop layer 420 is amorphous, made of amorphous SiO.sub.2 or SiN for example.

(26) The stop layer 420 may be of nature other than SiO.sub.2, provided that the chosen insulating material is inert with respect to the chemical etching used to reveal the facets (etching carried out, as was seen above, using KOH for example) in the silicon surface layer.

(27) FIGS. 4a to 4i illustrate an example of implementation of the process of the invention on a stack, which in this case is an SOI substrate 400 as illustrated in FIG. 4c.

(28) The orientation of the single-crystal surface layer 410 of the substrate, which is typically made of silicon, has a disorientation of the (001) crystal plane of 7 toward [110] so as to subsequently obtain an epitaxial layer of GaN of (10-11) orientation.

(29) This SOI substrate 400 comprises the carrier layer 402 surmounted by the stop layer 420, which itself is surmounted by the single-crystal surface layer 410.

(30) This SOI substrate 400 is for example obtained in a conventional way, as was briefly explained above and as illustrated in FIGS. 4a and 4b, starting with a thick carrier layer 402, which is for example made of silicon, the surface 404 of which is oxidized before addition of the single-crystal surface layer 410, for example using the technique called the smart-cut technique.

(31) Preferably, before bonding, the single-crystal surface layer 410 is itself oxidized beforehand in order to facilitate the molecular bonding. The in-contact oxidized layers thus form the intermediate stop layer 420 of the SOI substrate.

(32) As illustrated in FIGS. 4e to 4f, grooves 460 are then etched in the single-crystal surface layer 410. These grooves are recessed patterns, and thus form trenches.

(33) To do this, a mask 440 is produced on top of the single-crystal surface layer 410. The mask forms parallel bands 441 covering the single-crystal surface layer 410 and leaves uncovered other parallel bands of the single-crystal surface layer 410.

(34) The mask 440 is produced by depositing or growing a layer of silicon oxide (SiO.sub.2) or silicon nitride (SiN) 430. Next, the bands 441 are formed by lithography, for example by conventional photolithography and etching of the masking layer 430.

(35) The parallel bands 441 are oriented in a preset crystal direction of the single-crystal surface layer 410. The crystal layer 410 has an internal face facing the stop layer 420 and an external face opposite the internal face, said external face also being designated the top surface. The direction of orientation of the parallel bands 441 must correspond to a direction common to the plane of the external face of the crystal layer 410 and to the <111> plane that it is desired to reveal via chemical etching. This direction is a <110> direction. Thus, the bands 441 are parallel to the intersection between the plane of the top surface of the single-crystal layer 410 and the <111> plane. In the example of implementation of the invention illustrated in FIG. 4, it is a question of a <110> direction.

(36) The single-crystal surface layer 410 may then be chemically etched for example using KOH as already mentioned above or even tetramethyl ammonium hydroxide or TMAH.

(37) The grooves 460 thus formed by etching are parallel to the bands 441. Thus, these grooves 460 define parallel grooves that are oriented in the direction common to the plane of the external face of the crystal layer 410 and to the <111> plane.

(38) In the context of the invention, advantageously, the etching stops automatically when the stop layer 420, which is made of SiO.sub.2 in this nonlimiting example, is reached. Thus, the etching stops before the facets 330 of {111} orientation meet as is the case in the conventional process described with respect to the prior art in which a bulk silicon substrate is used.

(39) Thus, rather than setting the height of the facets 330 of {111} orientation via the etch time, said height is completely defined, with the process of the invention, by the thickness of the single-crystal silicon surface layer 410 of the SOI substrate.

(40) The height of the facets 330 depends on the depth of the groove 460. Facet height 330 and the depth of the groove 460 are measured perpendicularly to the plane in which the various layers 402, 420, 410 mainly lie, i.e. along the vertical in FIGS. 4a to 4i.

(41) The grooves 460 therefore preferably have a flat bottom 421. This bottom is formed by the top face of the stop layer 420.

(42) As already mentioned above, chemical baths are a source of nonuniformities. The use of SOI substrates or, more generally, of SOX substrates, thus allows facets 330 to be obtained that have very uniform heights over the entire surface of the substrate and a controlled thickness despite nonuniformities due to the chemical etch. The residual nonuniformity is then that of the thickness 411 of the silicon layer of the SOI, which is only a few percent as specified by various suppliers of this type of substrate. This remains true for substrates (also commonly referred to as wafers) of large diameter (typically 300 mm) and for small silicon-surface-layer thicknesses (smaller than 20 nm).

(43) According to one embodiment, once the grooves 460 have been produced, a mask 419 that is configured to cover all the top face of the structure with the exception of the facets 330 of {111} orientation is then formed. This mask 490 is illustrated in FIG. 4g. This mask 490 is typically formed from an oxide, for example from SiO.sub.2.

(44) Thus, this step of masking the top surface of the single-crystal substrate is carried out such that the facets 331 of {111} orientation opposite the facets 330 having a {111} crystal orientation are masked.

(45) The production of this mask 490 typically comprises depositing a material comprising at least one among: silicon oxide (SiO.sub.2), silicon nitride (SiN), and titanium nitride (TiN).

(46) According to a first embodiment, the deposition of this mask 490 is an angular deposition carried out such that all the top surface of the single-crystal substrate 410 is masked, with the exception of said facets 330 that have a {111} crystal orientation. The angle of inclination of the deposition means that one portion of the trench, corresponding to the facets 330, is not accessible and therefore does not receive the deposited material. This step is accomplished with the aid of a standard piece of equipment known as an ion beam sputterer (IBS), in which the angle of the deposition may be adjusted. This deposition with an inclined angle may also be obtained with the electron-beam-physical-vapor-deposition (EBPVD) technique, in which a target anode under vacuum is bombarded with an electron beam.

(47) Alternatively to these techniques allowing an inclined deposition of the material forming the mask 490, provision may also be made to deposit a masking layer of a material comprising at least one among: silicon oxide (SiO.sub.2), silicon nitride (SiN), and titanium nitride (TiN); then, following the deposition, the facets 330 of {111} orientation are laid bare in order to uncover them and allow the contact between the nitride to be grown epitaxially and the silicon of the facets 330 of {111} orientation.

(48) As shown in FIG. 4h, the crystallites 470 that are then grown from these facets 330 of {111} orientation are then all of a substantially equal size, to within the uncertainty in the variation in the thickness 411 of the single-crystal layer 410, greatly facilitating the coalescence and the obtainment of planar semipolar surfaces 480 over the entire extent of a substrate, such as illustrated in FIG. 4i.

(49) According to one embodiment, a first nitride layer is grown epitaxially and directly in contact with the facets 330 of {111} orientation of the single-crystal layer. Typically, this first layer of nitride is of AlN. Next, a second nitride, for example of GaN, is then grown from the first epitaxially grown nitride layer. The interface between the layers the first and second nitride layers is not shown in the figures. This first nitride layer, typically made of or based on AlN, allows melt-back etching to be decreased as explained above.

(50) The dimensions of the facets 330 of {111} orientation obtained from the single-crystal surface layer 410 are preferably comprised in a range of values extending from 20 nm to 2 m, which corresponds to a range of thicknesses 411 of the surface layer of about 10 nm to 1 m depending on the crystal orientation of the starting surface. The periods of repetition of the bands 441 of the mask 440 are preferably comprised in a range of values extending from 2 to 10 m.

(51) It should be noted that the use of the facets 330 of very small sizes, which may be obtained with the process of the invention even on substrates of large size, allows the problem of melt-back etching described with respect to the prior art and that arises in the step of growth of the layer of GaN to be greatly minimized or even eliminated. As was seen above, this destructive effect is due to the reactivity of the silicon, which is raised during the phase of growth of the crystallites to temperatures high enough that it can react with gallium. This generally leads to the creation of cavities due to the untimely etching of the silicon of the substrate reacting with the gallium. The AlN buffer layer (not shown) that is deposited on the silicon before the growth of GaN is started may here be much more effective because of the small areas of silicon exposed during the growth, drastically decreasing or even completely eliminating this problem.

(52) It will finally be noted that the SOX structure used will allow the layer 480 of nitride of semipolar orientation that is grown from the facets 330 to be easily debonded. Specifically, the interfaces between the single-crystal layer 330 and the stop layer 420 (for example an Si/SiO.sub.2 interface) are mechanically fragile, thereby allowing the nitride layers 480 to be separated from their original substrate without breakage, provided that they are of sufficient thickness, thus obtaining uniform free-standing layers of GaN. For layer thicknesses of several hundred microns (m), semipolar pseudo-substrates are then obtained that may be of very large size, in particular if they are compared to those obtained, as described with respect to the prior art, by cutting at an angle an ingot of GaN of c orientation, of a diameter that does not exceed 1 inch or 2.5 cmthe maximum size that it is currently known how to obtain.

(53) According to one embodiment (not illustrated), an additional step is carried out after the step of producing the plurality of parallel grooves and before the step of epitaxial growth of the single-crystal layer. This additional step comprises producing a plurality of parallel trenches that extend in a direction having undergone a rotation with respect to the main direction in which the parallel grooves 360 extend.

(54) According to one embodiment, the trenches are turned, with respect to the grooves 360, by an angle this is larger than 40 and that is preferably comprised between 50 and 90, this angle being measured in a plane parallel to the main plane in which the carrier layer 402 lies.

(55) Thus, the trenches thus interrupt the continuous grooves 360 so as to form a matrix-array of individual facets each having a {111} crystal orientation. Thus, during the epitaxial growth step, the material grows solely from said individual facets that have a {111} crystal orientation and that form said matrix-array. Preferably, the trenches and the grooves each have a bottom, the bottom of the trenches being located at the same depth or below the bottom of the grooves.

(56) The formation of the trenches, which are inclined with respect to the grooves, allows the available areas of the facets having a {111} crystal orientation to be decreased. This optional but advantageous embodiment thus allows the footprint serving for the epitaxial growth to be decreased and thus the number of defects, during the epitaxial growth, generated at the GaN/AlN/Si or AlN/Si interface to be decreased, while imposing growth in the appropriate +c direction.

(57) The invention is not limited to the embodiments described above and encompasses all the embodiments covered by the claims.