Distortion compensation apparatus and distortion compensation method

Abstract

A DPD operates at a sampling rate at which the input signal not up sampled at an upstream of the DPD is sampled. The DPD includes a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample, and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample. The DPD uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Claims

1. A distortion compensation apparatus for compensating non-linear distortion of a power amplifier, the distortion compensation apparatus comprising: an AD converter configured to feed back an output signal of the power amplifier, convert it from analog to digital, and output the converted signal as a feedback signal; a digital predistorter configured to perform distortion compensation processing on an input signal using the feedback signal and output a signal which has been subjected to the distortion compensation processing; a DA converter disposed between the digital predistorter and the power amplifier and configured to convert the output signal of the digital predistorter from digital to analog and output the converted signal to the power amplifier, wherein the digital predistorter operates at a sampling rate at which the input signal not upsampled at an upstream of the digital predistorter is sampled, the digital predistorter comprises: a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample; and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample, and the digital predistorter uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

2. The distortion compensation apparatus according to claim 1, wherein the digital predistorter comprises: a plurality of the FIR filters; and a first adder configured to add an output signal of each of the plurality of the FIR filters and output an added signal, the digital predistorter includes a configuration in which a plurality of first paths of the polynomial structure are branched in parallel from an input stage of the digital predistorter, and the plurality of the FIR filters are disposed at a downstream of each of the plurality of first paths, and the first adder is disposed at a downstream of the plurality of FIR filters, and the pseudo-interpolation and sub-sample shift processing unit is disposed in the first path.

3. The distortion compensation apparatus according to claim 2, wherein the plurality of the first paths include the first path in which the pseudo-interpolation and sub-sample shift processing unit is disposed and the first path in which the pseudo-interpolation and sub-sample shift processing unit is not disposed.

4. The distortion compensation apparatus according to claim 3, wherein the pseudo-interpolation and sub-sample shift processing unit is a filter including a fixed tap coefficient, and a first delay device including a delay amount determined by the number of taps of the pseudo-interpolation and sub-sample shift processing unit is disposed in the first path in which the pseudo-interpolation and sub-sample shift processing unit is not disposed.

5. The distortion compensation apparatus according to claim 2, wherein each of the plurality of the FIR filters includes a configuration in which a plurality of second paths are branched in parallel from the input stage of the FIR filter, and the sub-sample delay filter is disposed in the second path.

6. The distortion compensation apparatus according to claim 5, wherein the plurality of second paths include the second path in which the sub-sample delay filter is disposed and the second path in which the sub-sample delay filter is not disposed.

7. The distortion compensation apparatus according to claim 6, wherein the sub-sample delay filter is a filter including a fixed tap coefficient, and a second delay device including a delay amount determined by the number of taps of the sub-sample delay filter is disposed in the second path in which the sub-sample delay filter is not disposed.

8. The distortion compensation apparatus according to claim 7, wherein each of the plurality of FIR filters comprises one-sample delay device configured to delay the sample point of the input signal by one sample, in the second path in which the sub-sample delay filter is disposed, the one-sample delay device is disposed at a downstream of the sub-sample delay filter, and in the second path in which the sub-sample delay filter is not disposed, the one-sample delay device is disposed at a downstream of the second delay device.

9. The distortion compensation apparatus according to claim 8, wherein each of the plurality of FIL filters comprises: a plurality of multipliers configured to multiply each of output signals of the sub-sample delay filter, the second delay device, and the one-sample delay device by a corresponding filter coefficient; and a second adder configured to add the output signal of each of the plurality of multipliers and output an added signal.

10. A distortion compensation method performed by a distortion compensation apparatus for compensating non-linear distortion of a power amplifier, the distortion compensation method comprising: performing distortion compensation processing by a digital predistorter on an input signal using a feedback signal obtained by feeding back an output signal of the power amplifier and converting it from analog to digital and outputting the signal which has been subjected to the distortion compensation processing; and converting the output signal of the digital predistorter from digital to analog and outputting the converted signal to the power amplifier, wherein the digital predistorter operates at a sampling rate at which the input signal not upsampled at an upstream of the digital predistorter is sampled, the digital predistorter comprises: a polynomial structure comprising a pseudo-interpolation and sub-sample shift processing unit configured to pseudo-interpolate a sample point between the sample points of the input signal and shift the pseudo-interpolated sample point by a sub-sample; and an FIR (Finite Impulse Response) filter disposed at a downstream of the polynomial structure and including a sub-sample delay filter configured to delay the sample point of the input signal by the sub-sample, and the digital predistorter uses the polynomial structure and the FIR filter to compensate distortion by the sample point of the input signal and also compensate distortion by a sub-sample point between the sample points of the input signal for the digital predistorter.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The above and other aspects, features and advantages of the present disclosure will become more apparent from the following description of certain exemplary embodiments when taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a block diagram showing a configuration example of a DPD according to an embodiment of the present disclosure;

(3) FIG. 2 is a view showing an example of tap coefficients of half-band FIR filters for 2 interpolation incorporated in an interpolation DA converter;

(4) FIG. 3 is a timing chart illustrating an example of 2 interpolation processing in the interpolation DA converter;

(5) FIG. 4 is a view showing an example of a procedure for obtaining tap coefficients of a pseudo-interpolation filter to obtain a sub-sample memory taps=0.5 for a DPD operating at a sampling rate not being up sampled;

(6) FIG. 5-a is a view showing an example of an impulse response of a 0.5 sample delay filter when a delay is a non-integer for a sample;

(7) FIG. 5-b is a view showing an example of a frequency characteristic of a filter attenuation amount for the number of taps when the 0.5 sample delay filter is composed of an FIR filter;

(8) FIG. 6 is a view showing an example of a distortion compensation characteristic when a configuration of a related art is applied to a DPD in a distortion compensation apparatus in which upsampling for the DPD is not performed;

(9) FIG. 7 is a view showing an example of a distortion compensation characteristic when a configuration according to an embodiment of the present disclosure is applied to a DPD in a distortion compensation apparatus in which upsampling for the DPD is not performed;

(10) FIG. 8 is a block diagram showing a configuration example of a distortion compensation apparatus according to the related art;

(11) FIG. 9 is a block diagram showing an example of functions of the interpolation DA converter;

(12) FIG. 10 is a block diagram showing a configuration example of a DPD in the distortion compensation apparatus according to the related art shown in FIG. 8;

(13) FIG. 11 is a block diagram showing a configuration example of a DPD to which a measurement for reducing a coefficient amount is applied to the DPD according to the related art shown in FIG. 10;

(14) FIG. 12 is a view showing an example of a distortion characteristic of an output of a power amplifier model for an interpolated and up sampled signal when the DPD is not operated;

(15) FIG. 13 is a view showing a compensation characteristic by an up sampling DPD according to the related art;

(16) FIG. 14 is a block diagram showing a configuration example of a distortion compensation apparatus according to an embodiment of the present disclosure in which an interpolation circuit is deleted, and up sampling for the DPD is not performed;

(17) FIG. 15 shows an example of a comparison between an amplitude change of a signal in the 800 MHz band at the sampling frequency of 983.04 MHz before interpolation and an amplitude change of a signal obtained by upsampling this signal by a factor of 2 through the 2 interpolation processing to make it 1.96608 GHz; and

(18) FIG. 16 shows an example of a comparison between an amplitude change of a signal upsampled by a factor of 2 to achieve a sampling frequency of 1.96608 GHz through 2 interpolation processing and an amplitude change of a signal obtained by upsampling this signal by a factor of 4 to achieve the sampling frequency of 3.93216 GHz through another 2 interpolation processing.

EMBODIMENTS

(19) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

Outline of Embodiment

(20) FIG. 1 is a block diagram of a configuration example of a DPD 1 according to this embodiment. The DPD 1 according to this embodiment corresponds to the DPD 1 in the distortion compensation apparatus shown in FIG. 14. As described above, the distortion compensation apparatus shown in FIG. 14 has a configuration to address the second problem concerning the device performance in the distortion apparatus according to the related art, in which the interpolation circuit 8 shown in FIG. 8 is deleted, and upsampling for the DPD is not performed.

(21) An outline of this embodiment will be described first prior to giving descriptions about the DPD 1 according to this embodiment shown in FIG. 1

(22) As described above, the distortion compensation apparatus shown in FIG. 14 operates at a low sampling rate not being up sampled without performing up sampling processing for the DPD at the upstream of the DPD 1. Even the distortion compensation apparatus shown in FIG. 14 can compensate the memory effect by sub-sample memory taps between sample points of the DPD 1 generated by the interpolation DA converter 2 at the downstream of the DPD 1, if it can achieve both of the following (A) and (B).

(23) (A) Generating a signal corresponding to the signal x.sub.u(nl.sub.s) in the above equation (8) in which the coefficient amount is reduced and the signal upsampled by a factor of 2 in FIG. 1 from a sample signal sequence of the input signal of the DPD 1 which has not been up sampled.

(24) (B) Achieving the FIR filter equivalent to the FIR filter.sub.0 405a, the FIR filter.sub.1 405b, and the FIR filter.sub.2 405c operating at the doubled sampling frequency shown in FIG. 11 without performing up sampling by the factor of 2.

(25) In the following equation (11), a signal corresponding to x.sub.u(nl.sub.s) upsampled by a factor of 2 in the above equation (8) generated from the sample signal sequence of the input signal of the DPD 1, which has not been upsampled, by pseudo-interpolation and sub-sample shift is substituted as a pseudo-interpolation signal x.sub.u(nl.sub.s). Further, in the following equation (11), a signal corresponding to y.sub.u(n3) obtained by the above equation (8) after the upsampling by a factor of 2 generated by x.sub.u(nl.sub.s) and the sub-sample FIR filter including sub-sample delay taps is substituted as y.sub.u(n3). Furthermore, in the following equation (11), x.sub.u(nl.sub.sr.sub.s) is substituted for x.sub.u(nl.sub.sr.sub.s) in the above equation (8), and y.sub.u(n3) is substituted for y.sub.u(n3) in the above equation (8). Hereinafter, means for achieving the following equation (11) without upsampling by a factor of 2 will be described.

(26) $\begin{array}{cc}{y}_u^{}\left(n-3\right)=\underset{l_s=0}{\overset{2}{.Math.}}\underset{r_s=0}{\overset{4}{.Math.}}{W}_{l_s,r_s}.Math.x_u^{}\left(n-l_s-r_s\right).Math.K_{l_s}\left(.Math.x_u^{}\left(n-l_s-r_s\right).Math.\right)& \left(11\right)\end{array}$

(27) In the equation (11), the memory taps l.sub.s are 0, +1, and +2, and the FIR taps r.sub.s are 0, +1, +2, +3, and +4. They are the sample shift amounts after the sampling by a factor of 2. Thus, for the DPD 1 operating at a sampling rate not being upsampled, the above memory taps correspond to the sub-sample shifts of 0, +0.5, and +1, and the above FIR taps correspond to the sub-sample shifts of 0, +0.5, +1, +1.5, and +2.

(28) First, means for generating x.sub.u(nl.sub.s) corresponding to the memory taps l.sub.s=0, +1, and +2 at the FIR tap r.sub.s=0 in the above equation (11) from the sample signal sequence of the input signal of the DPD 1, which is not upsampled, will be described.

(29) FIG. 2 shows an example of the tap coefficients of the 2 interpolation half-band FIR filter incorporated in the interpolation DA converter 2.

(30) In the half-band FIR filter, a center tap is the i-th tap, the number of taps is (2i1), and the tap coefficients are C.sub.1, C.sub.2, . . . , C.sub.i1, C.sub.1+1, . . . , and C.sub.2i1. As described above, regarding this half-band FIR filter, about half of the tap coefficients are equal to zero, and the half-band FIR filter is commonly composed of about 59 taps. To make descriptions and drawings simple, the taps in FIG. 2 show only 11 taps including the center tap and center tap 5 taps.

(31) FIG. 3 is a timing chart showing the 2 interpolation processing in the interpolation DA converter 2.

(32) For example, when the signal before interpolation is the input signal x(n), the 2 interpolation processing is processing performed after performing zero-stuffing between sampling of the input signal x(n), in which an image is eliminated through the half-band FIR filter for 2 interpolation shown in FIG. 2, and the double-interpolated output signal x.sub.u(n) is obtained.

(33) Here, as described above, the 2 interpolation processing is processing in which zero-stuffing is performed between sampling before the interpolation, and then passing through the half-band filter FIR. Therefore, in order to derive the double-interpolated sample x.sub.u(n) at a certain sample timing n where there are samples before the interpolation, only the center tap coefficient C.sub.i of the above half-band FIR filter for the 2 interpolation is an effective coefficient for the sample signal sequence before the interpolation. Thus, x.sub.u(n) can be expressed by the following equation (12) for the sample signal sequence before the interpolation.
x.sub.u(n)=C.sub.i.Math.x(n)(12)

(34) Next, unlike the above sample timing n, the sample timing n+1 after the 2 interpolation is a sample timing at which no sample before the interpolation is present. Thus, in order to derive x.sub.u(n+1) at the sample timing n+1, only i tap among (2i1) taps other than the center tap and taps of zero coefficients of the above half-band FIR filter for 2 interpolation is the effective coefficient for the sample signal sequence before the interpolation. For this reason, for example, x.sub.u(n+1) can be expressed by the following equation (13) for the sample signal sequence before the interpolation when the tap coefficients of 11 taps, which are given to make descriptions simple in FIGS. 2 and 3.
x.sub.u(n+1)=C.sub.i5.Math.x(n2)+C.sub.i3.Math.x(n1)+C.sub.i1.Math.x(n)+C.sub.i+1.Math.x(n+1)+C.sub.i+3.Math.x(n+2)+C.sub.i+5.Math.x(n+3) (13)

(35) Furthermore, unlike the above sample timing n, the sample timing n1 after the 2 interpolation is a sample timing where no sample before the interpolation is present. Thus, in order to derive x.sub.u(n1) at the sample timing n1, only i tap among (2i1) taps other than the center tap and taps of zero coefficients of the half-band FIR filter for 2 interpolation is the effective coefficient for the sample signal sequence before the interpolation. For this reason, for example, x.sub.u(n+1) can be expressed by the following equation (14) for the sample signal sequence before the interpolation when the tap coefficients of 11 taps, which is simplified for simple descriptions, in FIGS. 2 and 3 are used.
x.sub.u(n1)=C.sub.i5.Math.x(n3)+C.sub.i3.Math.x(n2)+C.sub.i1.Math.x(n1)+C.sub.i+1.Math.x(n)+C.sub.i+3.Math.x(n+1)+C.sub.i+5.Math.x(n+2) (14)

(36) Next, FIG. 4 shows a procedure for obtaining the tap coefficients of pseudo-interpolation filters (corresponding to pseudo-interpolation and sub-sample shift filters 101a and 101b in FIG. 1) in order to obtain the sub-sample memory tap=0.5 for the DPD 1 operating at the sampling rate not upsampled shown in the equations (13) and (14).

(37) The purpose of obtaining the tap coefficients of the pseudo-interpolation filter is not to actually perform the 2 interpolation processing shown in FIG. 2 on the example of the tap coefficients of the half-band FIR filter for 2 interpolation shown in FIG. 1. The purpose of obtaining the tap coefficients of the pseudo-interpolation filter is to obtain the effective coefficient which is to be multiplied by the sample signal sequence of the input signal of the DPD 1 before the interpolation at the sampling timing before the interpolation in order to obtain the sub-sample memory tap=0.5 for the DPD 1 operating at the sampling rate not being upsampled.

(38) At the sample timing at which the sample before the interpolation is present, all the coefficients are normalized with the center tap coefficient C.sub.i so that x.sub.u(n)=x(n) (i.e., C.sub.i=1.0) in the above equation (12), and then the center tap and the taps of zero coefficients are removed. Consequently, the effective coefficient of the i-tap to be multiplied at the sampling timing before the interpolation is obtained. This obtained effective coefficient is the tap coefficient of the i-tap pseudo-interpolation filter for obtaining the sub-sample memory tap=0.5 for the DPD 1 operating at the sampling rate not being up sampled. Thus, when all coefficients in the above equation (13) are normalized with the center tap coefficient C.sub.i, the pseudo interpolation signal x.sub.u(n+1) can be expressed by the following equation (15). Furthermore, when all coefficients in the above equation (14) are normalized with the center tap coefficient C.sub.i, the pseudo interpolation signal x.sub.u(n1) can be expressed by the following equation (16).

(39) $\begin{array}{cc}{x}_u^{}\left(n+1\right)=\frac{C_{i-5}}{C_i}.Math.x\left(n-2\right)+\frac{C_{i-3}}{C_i}.Math.x\left(n-1\right)+\frac{C_{i-1}}{C_i}.Math.x\left(n\right)+\frac{C_{i+1}}{C_i}.Math.x\left(n+1\right)+\frac{C_{i+3}}{C_i}.Math.x\left(n+2\right)+\frac{C_{i+5}}{C_i}.Math.x\left(n+3\right)& \left(15\right)\\ x_u^{}\left(n-1\right)=\frac{C_{i-5}}{C_i}.Math.x\left(n-3\right)+\frac{C_{i-3}}{C_i}.Math.x\left(n-2\right)+\frac{C_{i-1}}{C_i}.Math.x\left(n-1\right)+\frac{C_{i+1}}{C_i}.Math.x\left(n\right)+\frac{C_{i+3}}{C_i}.Math.x\left(n+1\right)+\frac{C_{i+5}}{C_i}.Math.x\left(n+2\right)& \left(16\right)\end{array}$

(40) Here, a processing delay of the i-tap pseudo-interpolation filter is (i1) samples in the sampling after the 2 interpolation, i.e., a sampling conversion of (i/20.5) of the DPD 1 operating at the sampling rate not being upsampled. Therefore, when i/2 samples are delayed for the input in the sampling of the DPD 1 in the path where the sub-sample memory tap=0 in which the pseudo-interpolation filter is not disposed, the pseudo-interpolation filter in the path in which the pseudo-interpolation filter is disposed is 0.5 sample earlier than the path where the sub-sample memory tap=0, i.e., which is the pseudo-interpolation and sub-sample shift filter (corresponding to the pseudo-interpolation and sub-sample shift filter 101a in FIG. 1) for obtaining the sub-sample memory tap=0.5 for the DPD 1. Further, when the pseudo-interpolation filter is disposed after one sample is delayed in the sampling of the DPD 1 for the input, the pseudo-interpolation filter disposed after the delay of one sample is delayed by 0.5 sample from the path where the sub-sample memory tap=0, i.e., which is the pseudo-interpolation and sub-sample shift filter (corresponding to the pseudo-interpolation and sub-sample shift filter 101b in FIG. 1) for obtaining the sub-sample memory tap=+0.5 for the DPD 1.

(41) Note that that the pseudo-interpolation and sub-sample shift filter has a configuration in which the I phase tap coefficient and the Q phase tap coefficient are the same and does not require a complex multiplication.

(42) As described so far, the sub-sample memory taps=0.5 for the DPD 1 operating at the sampling rate not being upsampled can be obtained in each of the paths in which the pseudo-interpolation and sub-sample shift filters are disposed. Further, the sub-sample memory taps of 0.5, 0, and +0.5 can be achieved including the path where the sub-sample memory tap=0 in which the pseudo-interpolation and sub-sample shift filter is not disposed. The sub-sample memory taps of 0.5, 0, and +0.5 correspond to the memory taps 1=1, 0, and +1 after the upsampling by a factor of 2 in the above equation (6). Therefore, like the substitution of the equations (7) and (8) for the equation (6), when substitution is made for the time shift amount l as in l=l.sub.s1, x.sub.u(nl.sub.s) corresponding to the memory taps l.sub.s=0, +1, +2 in the equation (11) is obtained.

(43) Note that i indicating the number of taps of the pseudo-interpolation and sub-sample shift filter is an example of the assumed number of taps for the (2i1) taps of the half-band FIR filter for the 2 interpolation in the interpolation DA converter 2. However, the present disclosure is not limited to this. As described above, when the common half-band FIR filter for 2 interpolation is 59 taps, i=30 according to the above example. However, in practice, the number of taps i of the pseudo-interpolation and sub-sample shift filter may be reduced within a range not affecting the performance for the purpose of reducing the circuit size of the pseudo-interpolation and sub-sample shift filter.

(44) Secondly, means for obtaining sub-sample FIR taps=0, +0.5, +1, +1.5, and +2 in the sampling of the DPD 1 operating at the sampling rate not being upsampled in the equation (11) will be described.

(45) FIG. 5-a shows an impulse response example of a 0.5 sample delay filter when a delay is a non-integer for the sample, for example, the delay is 0.5 sample.

(46) When the delay is a non-integer for the sample, the impulse response s (n) is infinite (IIR: Infinite Impulse Response) and not finite (FIR) as shown in the following equation (17).

(47) $\begin{array}{cc}s\left(n\right)=\frac{\sin \left(n-\right)}{\left(n-\right)}& \left(17\right)\end{array}$

(48) Thus, in terms of a practical implementation, the number of taps is limited to the finite number of taps j to thereby reduce the circuit size of the filter. When the taps of the sub-sample delay IIR filter is limited, in-band ripple occurs. In order to suppress the in-band ripple, processing for a multiplication by a window function with a delayed point as the center is necessary. However, the number of taps and the characteristic is in a trade-off relationship, because the pass band is narrowed through this processing.

(49) FIG. 5-b shows a frequency characteristic of a filter attenuation amount for the number of taps j when the tap coefficient is limited, multiplied by the window function, and the 0.5 sample delay filter is composed of a FIR filter.

(50) The sub-sample delay filter (corresponding to a sub-sample delay filter 111 in FIG. 1) is a filter intended for distortion compensation within the 800 MHz carrier band. Thus, when the attenuation amount at the 400 MHz offset point on one side is suppressed to 0.5 dB or less, an example of the number of taps j required for the sub-sample delay filter is 14 taps or more.

(51) However, unlike the above pseudo-interpolation and sub-sample shift filter, this sub-sample delay filter simply gives a sub-sample delay. Thus, when one j-tap 0.5 sample delay filter is included in one path, a 1.5 sample delay can be achieved by disposing a one-sample delay device at a downstream of the 0.5 sample delay filter.

(52) Here, a processing delay of the j tap sub-sample delay filter is (j1) samples in the sampling after the 2 interpolation, i.e., a sampling conversion of (j/20.5) of the DPD 1 operating at the sampling rate not being upsampled. Therefore, when (j/21) samples are delayed in the sampling of the DPD 1 for the input of the FIR filter in the path in which the sub-sample delay filter is not disposed, the signal that passed through the above sub-sample delay filter becomes a signal delayed by 0.5 sample from the signal after (j/21) samples are delayed. For this reason, the sub-sample delay filter is a sub-sample delay filter for obtaining the sub-sample FIR tap=+0.5 for the DPD 1.

(53) Note that the sub-sample delay filter has a configuration in which the I phase tap coefficient and the Q phase tap coefficient are the same and does not require a complex multiplication.

(54) In the path in which the sub-sample delay filter is disposed, the sub-sample delay filter delays a signal delayed by 0.5 sample from the above signal delayed by (j/21) samples and further delays a signal from the signal delayed by 0.5 sample by one sample, which is a signal delayed by 1.5 samples from the above signal delayed by (j/21) in the sampling of the DPD 1, and then the delayed signals are output. On the other hand, in the path in which the sub-sample delay filter is not disposed, the signal delayed by (j/21) samples in the sampling of the DPD 1, and the signals delayed by one sample and two samples from this signal in the sampling of the DPD 1 are output. As a result, signals having a delay amount of 0 sample, 0.5 sample, 1 sample, 1.5 samples, and 2 samples from the above signal delayed by (j/21) samples can be obtained in the sampling of the DPD 1, thereby achieving the sub-sample FIR taps=0, +0.5, +1, +1.5, and +2 with five taps. With these five taps, the FIR filters corresponding to the FIR taps r.sub.s=0, +1, +2, +3, and +4 operating at twice the sampling frequency can be achieved without upsampling by a factor of 2.

(55) As described above, a signal corresponding to the above equation (11) can be achieved by the polynomial structure including the pseudo-interpolation sub-sample shift filter with the reduced coefficient amount and the sub-sample FIR filter including the sub-sample delay filter.

(56) In practice, with the addition of the above pseudo-interpolation and sub-sample shift filter and the above sub-sample delay filter, a total delay amount (i1)+(j2) samples becomes a processing delay added in l.sub.s=0 and r.sub.s=0 at a certain sample timing n of the input signal of the DPD 1, where the total delay amount is obtained by adding the delay amount (i1) samples in the sampling after the 2 interpolation by the above pseudo-interpolation and sub-sample shift filter and the delay amount (j2) samples obtained by converting the (j/2) sample delay in the sampling of the DPD 1 added to the path in which the above sub-sample delay filter is not disposed. Thus, the above equation (11) becomes the following equation (18).

(57) $\begin{array}{cc}{y}_u^{}\left(n-3-\left(i-1\right)-\left(j-2\right)\right)=\underset{l_s=0}{\overset{2}{.Math.}}\underset{r_s=0}{\overset{4}{.Math.}}{W}_{l_s,r_s}.Math.x_u^{}\left(n-l_s-r_s-\left(i-1\right)-\left(j-2\right)\right).Math.K_{l_s}\left(.Math.x_u^{}\left(n-l_s-r_s-\left(i-1\right)-\left(j-2\right)\right).Math.\right)& \left(18\right)\end{array}$

(58) Further, the equation (18) is organized, and the following equation (19) is obtained.

(59) 0$\begin{array}{cc}{y}_u^{}\left(n-i-j\right)=\underset{l_s=0}{\overset{2}{.Math.}}\underset{r_s=0}{\overset{4}{.Math.}}{W}_{l_s,r_s}.Math.x_u^{}\left(n+3-i-j-l_s-r_s\right).Math.K_{l_s}\left(.Math.x_u^{}\left(n+3-i-j-l_s-r_s\right).Math.\right)& \left(19\right)\end{array}$

(60) That is, at the sampling rate of the DPD 1 operating at the sampling rate not upsampled by a factor of 2, the calculation corresponding to the equation (19) in which the rate upsampled by a factor of 2 is substituted for the rate not upsampled by a factor of 2 can be achieved by calculating the following equation (20).

(61) $\begin{array}{cc}y\left(n-\frac{i}{2}-\frac{j}{2}\right)=\underset{l_s=0}{\overset{2}{.Math.}}\underset{r_s=0}{\overset{4}{.Math.}}{W}_{l_s,r_s}.Math.x\left(n+\frac{3-i-j-l_s-r_s}{2}\right).Math.K_{l_s}\left(.Math.x\left(n+\frac{3-i-j-l_s-r_s}{2}\right).Math.\right)& \left(20\right)\end{array}$

(62) Further, like in the above equation (8), in the equation (20), a polynomial with l.sub.s=1 and r.sub.s=2 where the time shift amount of the output signal of the DPD 1 for the input signal of the DPD 1 becomes zero corresponds to the memoryless polynomial.

(63) As described above, it has been confirmed that the above equation (20) can be achieved from the sample signal sequence of the input signal of the DPD 1 not upsampled without upsampling by a factor of 2, by the polynomial structure including the above pseudo-interpolation and sub-sample shift filter and the above FIR filter including the above sub-sample delay filter.

Configuration of Embodiment

(64) The DPD 1 according to this embodiment has a configuration including the polynomial structure including the above pseudo-interpolation and sub-sample shift filter and the FIR filter disposed at the downstream of the polynomial structure and including the above sub-sample delay filter. With this configuration, the above equation (20) is achieved without upsampling by a factor of 2 from the sample signal sequence of the input signal of the DPD 1 not being upsampled, which has been confirmed as feasible above.

(65) FIG. 1 shows one configuration example of the DPD 1 according to this embodiment when the calculation of the above equation (20) is configured to be performed by, for example, a hardware function. Hereinafter, the DPD 1 according to this embodiment shown in FIG. 1 will be described in detail.

(66) As described above, the DPD 1 according to this embodiment shown in FIG. 1 corresponds to the DPD 1 in the distortion compensation apparatus shown in FIG. 14. FIG. 14 shows a configuration example of the distortion compensation apparatus proposed in this embodiment. As described above, the distortion compensation apparatus shown in FIG. 14 has a configuration to address the second problem concerning the device performance in the distortion apparatus according to the related art, in which the interpolation circuit 8 shown in FIG. 8 is deleted, and upsampling for the DPD is not performed.

(67) The DPD 1 according to this embodiment shown in FIG. 1 includes pseudo-interpolation and sub-sample shift filters 101a and 101b composed of i-tap FIR filters, an i/2 sample delay device 102, a one-sample delay device 103, amplitude address calculation circuits 104a, 104b, and 104c, LUTs 105a, 105b, and 105c, complex multipliers 106a, 106b, and 106c, FIR filter.sub.0 107a, FIR filter.sub.1 107b, FIR filter.sub.2 107c, and an adder 108. Each of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c includes a sub-sample delay filter 111 composed of a j-tap FIR filter, a (j/21) sample delay device 112, one-sample delay devices 113a, 113b, and 113c, complex multipliers 114a, 114b, 114c, 114d, 114e, and an adder 115.

(68) The DPD 1 according to this embodiment shown in FIG. 1 is branched in parallel from the input stage of the DPD 1 into three paths (first paths), and each of the three paths is provided with a pseudo-interpolation and sub-sample shift filter 101a, an i/2 sample delay device 102, and a pseudo-interpolation and sub-sample shift filter 101b.

(69) The pseudo-interpolation and sub-sample shift filters 101a and 101b are an example of a pseudo-interpolation and sub-sample shift processing unit that interpolates sub-sample points in a pseudo manner between sample points of the signal input thereto and shifts the sub-sample points interpolated in a pseudo manner by the sub-samples. The i/2 sample delay device 102 is an example of a first delay unit that delays the sample points of a signal input thereto by i/2 samples.

(70) The amplitude address calculation circuit 104a, the LUT 105a, the complex multiplier 106a, and the FIR filter.sub.0 107a are disposed at a downstream of the pseudo-interpolation and sub-sample shift filter 101a. The amplitude address calculation circuit 104b, the LUT 105b, the complex multiplier 106b, and the FIR filter.sub.1 107b are disposed at a downstream of the i/2 sample delay device 102. The one-sample delay device 103 is disposed at an upstream of the pseudo-interpolation and sub-sample shift filter 101b. The amplitude address calculation circuit 104c, the LUT 105c, the complex multiplier 106c, and the FIR filter.sub.2 107c are disposed at a downstream of the pseudo-interpolation and sub-sample shift filter 101b. The one-sample delay device 103 delays the sample points of the signal input thereto by one sample. Further, the adder 108 is disposed at a downstream of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c. The adder 108 is an example of a first adder. Note that the polynomial structure is defined as a structure, for example, from the beginning to the complex multiplier 106a in the path in which the pseudo-interpolation and sub-sample shift filter 101a is disposed. The same applies to other paths.

(71) Each of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c is branched in parallel from the input stage of its own FIR filter into two paths (second paths). Each of the two paths includes a sub-sample delay filter 111, and a (j/21) sample delay device 112.

(72) The sub-sample delay filter 111 delays the sample points of the signal input thereto by sub-samples. The (j/21) sample delay device 112 is an example of a second delay unit which delays the sample point of the signal input thereto by (j/21) samples.

(73) The one-sample delay devices 113a and 113b connected in series are disposed at a downstream of the (j/21) sample delay device 112. Further, the complex multiplier 114a is disposed in parallel with the one-sample delay device 113a at a downstream of the (j/21) sample delay device 112. The one-sample delay device 113b is disposed in parallel with the complex multiplier 114b at a downstream of the one-sample delay device 113a. The complex multiplier 114c is disposed at a downstream of the one-sample delay 113b. The one-sample delay device 113c is disposed at a downstream of the sub-sample delay filter 111. The complex multiplier 114d is disposed in parallel with the one-sample delay device 113c at the downstream of the sub-sample delay filter 111. The complex multiplier 114e is disposed at the downstream of the one-sample delay device 113c. The one-sample delay devices 113a, 113b, and 113c delay the sample points of the signal input thereto by one sample. The adder 115 is disposed at a downstream of the complex multipliers 114a, 114b, 114c, 114d, and 114e. The adder 115 is an example of the second adder.

(74) The sample amount of each delay described above is a value at the sampling rate of the DPD 1 operating at the sampling rate not being up sampled.

(75) In FIG. 1, to make descriptions simple, the polynomial in the outputs of the complex multipliers 106a, 106b, and 106c for each term of the memory tap l.sub.s of the above equation (20), which are:

(76) $x\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right).Math.K_{l_s}\left(.Math.x\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right).Math.\right)$
is expressed by:

(77) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right)$
as shown in the equation (21).

(78) $\begin{array}{cc}x\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right).Math.K_{l_s}\left(.Math.x\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right).Math.\right)=d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right)& \left(21\right)\end{array}$

Operation of Embodiment

(79) Hereinafter, the operation of the DPD 1 according to this embodiment shown in FIG. 1 will be described.

(80) The pseudo-interpolation and sub-sample shift filter 101a generates:

(81) $x\left(n-\frac{i}{2}+\frac{1}{2}\right)$

(82) at the sampling rate of the DPD 1 corresponding to a 2 interpolation signal x.sub.u (ni+1), which has been delayed from the input signal x(n) of the DPD 1 at a certain sample timing by (i1) samples in the sampling after the 2 interpolation by the pseudo-interpolation and sub-sample shift filter 101a.

(83) Further, the i/2 sample delay device 102 generates:

(84) $x\left(n-\frac{i}{2}\right)$

(85) at the sampling rate of the DPD 1 corresponding to the signal x.sub.u(ni) delayed by i samples (=i/22 samples) in the sampling after the 2 interpolation.

(86) Furthermore, the one-sample delay device 103 and the pseudo-interpolation and sub-sample shift filter 101b generates:

(87) $x\left(n-\frac{i}{2}-\frac{1}{2}\right)$
at the sampling rate of the DPD 1 corresponding to the 2 interpolation signal x.sub.u(ni1) delayed by (i+1) samples in the sampling after the 2 interpolation.

(88) In the manner described above, signals of:

(89) $x\left(n-\frac{i}{2}+\frac{1}{2}\right),x\left(n-\frac{i}{2}\right),x\left(n-\frac{i}{2}-\frac{1}{2}\right)$
which are delayed each by one sample in the sampling after the 2 interpolation are generated.

(90) The amplitude address calculation circuits 104a, 104b, and 104c calculate the amplitude addresses for the LUTs corresponding to the amplitudes:

(91) $.Math.x\left(n-\frac{i}{2}+\frac{1}{2}\right).Math.,.Math.x\left(n-\frac{i}{2}\right).Math.,.Math.x\left(n-\frac{i}{2}-\frac{1}{2}\right).Math.$
of the signals, respectively.

(92) The LUTs 105a, 105b, and 105c are referred to based on the LUT amplitude addresses for the respective signals each delayed by one sample in the sampling after the 2 interpolation, and output signals of the respective LUTs corresponding to the LUT amplitude addresses are obtained. Then, the complex multipliers 106a, 106b, and 106c complex-multiply the output signals of the respective LUTs by the respective signals each delayed by one sample in the sampling after the 2 interpolation. The results of the complex multiplication by the complex multipliers 106a, 106b, and 106c are input to the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c, respectively, as the polynomial:

(93) 0$d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right)$

(94) for each term of the memory taps l.sub.s=0, 1, 2 in the sampling after the 2 interpolation. The FIR filter.sub.0 107a corresponds to the memory tap l.sub.s=0 in the sampling after 2 interpolation. The FIR filter.sub.1 107b corresponds to the memory tap l.sub.s=1 in the sampling after 2 interpolation. The FIR filter.sub.2 107c corresponds to the memory tap l.sub.s=2 in the sampling after 2 interpolation.

(95) In each of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c, the signal shown below is output to correspond to the FIR taps r.sub.s=0, 1, 2, 3, and 4 in the sampling after the 2 interpolation for each input:

(96) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}\right)$

(97) In the FIR tap r.sub.s=0, the (j/21) sample delay device 112 generates and outputs:

(98) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}-\frac{j}{2}+1\right)$
corresponding to a signal delayed by (j2) samples in the sampling after the 2 interpolation.

(99) In the FIR tap r.sub.s=1, the sub-sample delay filter 111 composed of the j-tap FIR filter generates and outputs:

(100) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}-\frac{j}{2}+\frac{1}{2}\right)$
corresponding to a signal delayed by (j1) samples in the sampling after the 2 interpolation.

(101) In FIR tap r.sub.s=2, the one-sample delay device 113a at the downstream of the (j/21) sample delay device 112 generates and outputs:

(102) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}-\frac{j}{2}\right)$
corresponding to a signal delayed by j samples in the sampling after the 2 interpolation.

(103) In the FIR tap r.sub.s=3, the one-sample delay device 113c at the downstream of the sub-sample delay filter 111 generates and outputs:

(104) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}-\frac{j}{2}-\frac{1}{2}\right)$
corresponding to a signal delayed by (j+1) samples in the sampling after the 2 interpolation.

(105) In the FIR tap r.sub.s=4, the one-sample delay device 113b at the downstream of the one-sample delay device 113a generates and outputs:

(106) $d\left(n-\frac{i}{2}+\frac{1}{2}-\frac{l_s}{2}-\frac{j}{2}-1\right)$
corresponding to a signal delayed by (j+2) samples in the sampling after the 2 interpolation.

(107) When the output of each of the five taps in the FIR.sub.ls corresponding to each memory tap l.sub.s is generalized and expressed using the memory taps l.sub.s (=0, 1, 2) and the FIR taps r.sub.s (=0, 1, 2, 3, 4) as variables, it will be:

(108) $d\left(n+\frac{3-i-j-l_s-r_s}{2}\right)$

(109) That is, the output signal of each FIR tap r.sub.s corresponding to delaying by one sample in the sampling after the 2 interpolation is expressed as follows.

(110) $d\left(n+\frac{3-i-j-l_s-r_s}{2}\right)$

(111) Each of the complex multipliers 114a, 114d, 114b, 114e, and 114c complex-multiplies the output signal of each FIR tap r.sub.s by the filter (complex) coefficients W.sub.ls,0, W.sub.ls,1, W.sub.ls,2, W.sub.ls,3, and W.sub.ls,4 corresponding to the FIR taps r.sub.s=0, 1, 2, 3, and 4, respectively. After that, the signals complex-multiplied by the complex multipliers 114a, 114d, 114b, 114e, and 114c are added by the adder 115. The signal added by the adder 115 is output from the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c as:

(112) $\underset{r_s=0}{\overset{4}{.Math.}}{W}_{l_s,r_s}.Math.d\left(n+\frac{3-i-j-l_s-r_s}{2}\right)$
for each memory tap l.sub.s.

(113) At this time, the output signal of the FIR filter.sub.0 107a corresponding to the memory tap l.sub.s=0 is as follows.

(114) 0$\underset{r_s=0}{\overset{4}{.Math.}}{W}_{0,r_s}.Math.d\left(n+\frac{3-i-j-r_s}{2}\right)$

(115) The output signal of the FIR filter.sub.1 107b corresponding to the memory tap l.sub.s=1 is as follows.

(116) $\underset{r_s=0}{\overset{4}{.Math.}}{W}_{1,r_s}.Math.d\left(n+\frac{2-i-j-r_s}{2}\right)$

(117) The output signal of the FIR filter.sub.2 107c corresponding to the memory tap l.sub.s=2 is as follows.

(118) $\underset{r_s=0}{\overset{4}{.Math.}}{W}_{2,r_s}.Math.d\left(n+\frac{1-i-j-r_s}{2}\right)$

(119) The output signals of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c are eventually added by the adder 108, and are output from the DPD 1 as the polynomial expressed by the above equation (20) in which the coefficient amount is reduced.

(120) As described above, the tap coefficients of the pseudo-interpolation and sub-sample shift filters 101a and 101b and the tap coefficients of the sub-sample delay filter 111 are already known fixed coefficients and need not be changed.

(121) Further, the i/2 sample delay device 102 is a fixed delay device determined by the number of taps i of the pseudo-interpolation and sub-sample shift filters 101a and 101b. Likewise, the (j/21) sample delay device 112 is a fixed delay device determined by the number of taps j of the sub-sample delay filter 111.

(122) Therefore, in the DPD 1 according to this embodiment shown in FIG. 1, the power series coefficient amounts in the LUTs 105a, 105b, and 105c and the tap coefficient amounts of the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c, which need to be derived by adaptive control and be updated, are the same as the coefficient amounts of the above equation (8) in which the coefficient amount is reduced by 30% from that of the related art and the configuration of FIG. 11.

Effect of Embodiment

(123) FIG. 6 shows a distortion compensation characteristic when the above-described equation (8) and the configuration of FIG. 11 are applied to the DPD 1 in the distortion compensation apparatus in which the upsampling for the DPD shown in FIG. 14 is not performed.

(124) In the example of FIG. 6, a signal having a system band of 800 MHz at a sampling frequency of 983.04 MHz is used as an input signal of the DPD 1 without upsampling it, and the above equation (8) and the configuration of FIG. 11 are applied to operate the DPD 1 by performing adaptive control using the following equation (22) as an error evaluation function. The characteristic shown in FIG. 6 is a distortion compensation characteristic in which an output signal of the DPD 1 at this time is input to the generalized memory polynomial model of the power amplifier after it is interpolated by the interpolation DA converter 2.

(125) $\begin{array}{cc}NRMSE=10.Math.{\log }_{10}\left(\frac{\underset{n=1}{\overset{N}{.Math.}}{.Math.z\left(n\right)-x\left(n\right).Math.}^2}{\underset{n=1}{\overset{N}{.Math.}}{.Math.x\left(n\right).Math.}^2}\right)& \left(22\right)\end{array}$

(126) Note that in the equation (22), x(n) is substituted for x.sub.u(n) in the equation (10), and z(n) is substituted for z.sub.u(n) in the equation (10) according to FIG. 14 in order to conform to the configuration in which the up sampling for the DPD is not performed.

(127) In the above equation (8) and the configuration of FIG. 11, the DPD 1 operating at the sampling rate before the interpolation which is performed by the interpolation DA converter 2 at the downstream of the DPD 1 cannot generate a distortion compensation signal that compensates the memory effect within the carrier band for the sub-samples. Thus, in particular, an error from a carrier signal due to distortion within a carrier band can be suppressed only to the average value of 41.1 dBc as compared with the average value of 23.6 dBc when the DPD shown in FIG. 12 is not operated. Further, the peak value cannot satisfy the target of the SNR distribution within the carrier band at the time of the above 256 QAM.

(128) FIG. 7 shows the distortion compensation characteristic when the above-described equation (20) and the configuration of FIG. 1 are applied to the DPD 1 in the distortion compensation apparatus in which the upsampling for the DPD shown in FIG. 14 is not performed, which is proposed in this embodiment.

(129) In the example of FIG. 7, a signal having a system band of 800 MHz at a sampling frequency of 983.04 MHz is used as an input signal of the DPD 1 without upsampling it, and the above equation (20) and the configuration of FIG. 1 are applied to operate the DPD 1 by performing adaptive control using the above equation (22) as an error evaluation function. The characteristic shown in FIG. 7 is a distortion compensation characteristic in which an output signal of the DPD 1 at this time is input to the generalized memory polynomial model of the power amplifier after it is interpolated by the interpolation DA converter 2.

(130) As shown in the equation (20) and the description of FIG. 1, the distortion compensation signal that compensates the memory effect within the carrier band for the sub-samples of the DPD 1 can be generated by the sub-sample memory taps achieved by the pseudo-interpolation and sub-sample shift filters 101a and 101b and the sub-sample FIR taps achieved by the sub-sample delay filter 111. Thus, it can be seen that an error from a carrier signal due to distortion within a carrier band can be suppressed only to the average value of 45.5 dBc as compared with the average value of 23.6 dBc when the DPD shown in FIG. 12 is not operated. It is also found that compensation performance to achieve the target SNR distribution within the carrier band at the time of the above 256 QAM including the peak value can be achieved.

(131) As described above, it is assumed that the DPD 1 according to this embodiment operates at a low sampling rate for sampling an input signal not upsampled for the DPD at the upstream of the DPD 1.

(132) The DPD according to this embodiment can generate, from the sample signal sequence of the input signal of the DPD 1 not being upsampled, for example, the signal corresponding to the signal x.sub.u(nl.sub.s) upsampled by a factor of 2 in the above equation (8) in which the coefficient amount is reduced and FIG. 11 using the polynomial structure including the pseudo-interpolation and sub-sample shift filters 101a and 101b.

(133) In addition, the DPD 1 according to this embodiment can achieve the FIR filter equivalent to the FIR filter.sub.0 405a, the FIR filter.sub.1 405b, and the FIR filter.sub.2 405c operating at the double sampling frequency in, for example, FIG. 11 using the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c including the sub-sample delay filter 111 disposed at the downstream of the polynomial structure.

(134) For this reason, by using the polynomial structure and the FIR filter.sub.0 107a, the FIR filter.sub.1 107b, and the FIR filter.sub.2 107c, the DPD 1 according to this embodiment not only compensates for the distortion due to the sample point but also compensates for the sample point and the distortion due to the sub-sample point between the sample point and the sample point.

(135) Therefore, the distortion compensation apparatus according to this embodiment does not perform upsampling processing for the DPD at the upstream of the DPD 1 and operates at a low sampling rate. Further, the distortion compensation apparatus according to this embodiment can reduce the coefficient calculation amount and reduce the operating frequency of the DPD 1 and the sampling rates of the DA converter 2 and the AD converter 7 as compared with the upsampling distortion compensation apparatus according to the related art. Additionally, the distortion compensation apparatus according to this embodiment can achieve the target compensation performance, because it is possible to compensate the memory effect within the carrier band by the sub-sample memory taps between the sample points of the DPD 1.

(136) Although various aspects of the present disclosure have been described with reference to the embodiments, the present disclosure is not limited by the above descriptions. Various changes that can be understood by those skilled in the art within the scope of the present disclosure can be made to the configuration and details in each aspect of the present disclosure.

(137) For example, the number of the memory taps l.sub.s and the number of the FIR taps r.sub.s shown in the above embodiments are examples, and the present disclosure is not limited to them. For example, in the above embodiments, the number of memory taps l.sub.s is set to three, and the number of FIR taps r.sub.s is set to five as an example of approximating the seventh-order memory polynomial model. However, the number of memory taps l.sub.s may be set to five, and the number of FIR r.sub.s may be set to three to approximate the seventh-order memory polynomial model. Alternatively, the number of taps may be increased, if increases in the circuit size and coefficient calculation amount are tolerable.

(138) The polynomial structure including the pseudo-interpolation and sub-sample shift filter shown in the above embodiments is an example, and the present disclosure is not limited to this. For example, regarding the polynomial structure shown in the above equation (20), a signal of:

(139) $x\left(n+\frac{3-i-j-l_s-r_s}{2}\right)$
and an LUT output of:

(140) $K_{l_s}\left(.Math.x\left(n+\frac{3-i-j-l_s-r_s}{2}\right).Math.\right)$
may be complex-multiplied by terms having different values of the memory taps l.sub.s, i.e., the complex-multiplied with the cross terms.

(141) According to the present disclosure, it is possible to achieve an effect that provides a distortion compensation apparatus and a distortion compensation method capable of achieving target compensation performance while reducing a coefficient amount even when a configuration in which an interpolation circuit at an upstream of a DPD is deleted, and upsampling for the DPD is not performed is employed.

(142) While the disclosure has been particularly shown and described with reference to embodiments thereof, the disclosure is not limited to these embodiments. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.