Adaptive burst generation for use with a DC-output converter

Abstract

These teachings apply with respect to a direct current (DC)-output converter and provide for adjusting a number of switching pulses per burst cycle as a function, at least in part, of converter output loading. This adjustment can be made by controlling burst frequency with respect to at least one predetermined threshold frequency. The predetermined threshold frequency can comprise a non-audible frequency such that the number of switching pulses is adjusted to prevent the burst frequency from itself constituting an audible signal. The adjustment of the number of switching pulses per burst cycle may only occur when the output loading is less than a predetermined level of loading. These teachings may also provide for clamping the pulse frequency for the pulses in each burst package to a particular value when dynamically controlling the number of pulses in each burst package. The aforementioned particular value may constitute, for example, a highest available switching frequency.

Claims

1. A direct current (DC)-output converter comprising: a coupler configured to couple to a voltage regulator; an adaptive burst generator that operably couples to the voltage regulator via the coupler; a control circuit that operably couples to the voltage regulator via the coupler and that is configured to adjust a number of switching pulses per burst cycle as a function, at least in part, of output loading by controlling burst frequency with respect to at least one predetermined threshold frequency, wherein the control circuit is configured to adjust a number of switching pulses per burst cycle by, at least in part, regulating a frequency of bursting with respect to the at least one predetermined threshold frequency by dynamically controlling a number of pulses in each burst package.

2. The DC-output converter of claim 1 wherein the DC-output converter comprises an alternating current (AC)-to-DC converter.

3. The DC-output converter of claim 1 wherein the predetermined threshold frequency comprises a non-audible frequency, such that the control circuit adjusts the number of switching pulses as a function of the output loading in order to prevent the burst frequency from constituting an audible signal.

4. The DC-output converter of claim 3 wherein the control circuit is configured to only adjust the number of switching pulses per burst cycle when the output loading is less than a predetermined level of loading.

5. The DC-output converter of claim 1 wherein the control circuit is further configured to dynamically control the number of pulses in each burst package while also clamping pulse frequency for the pulses in each burst package to a particular value.

6. The DC-output converter of claim 5 wherein the particular value constitutes a highest available switching frequency.

7. A method for use with a direct current (DC)-output converter comprising: adjusting a number of switching pulse per burst as a function, at least in part, of output loading by controlling burst frequency with respect to at least one predetermined threshold frequency, wherein adjusting the number of switching pulses per burst cycle comprises, at least in part, regulating a frequency of bursting with respect to the at least one predetermined threshold frequency by dynamically controlling a number of pulses in each burst package.

8. The method of claim 7 wherein the predetermined threshold frequency comprises a non-audible frequency, such that adjusting the number of switching pulses as a function of the output loading further comprises preventing the burst frequency from constituting an audible signal.

9. The method of claim 8 further comprising only adjusting the number of switching pulses per burst cycle when the output loading is less than a predetermined level of loading.

10. The method of claim 7 further comprising dynamically controlling the number of pulses in each burst package while also clamping pulse frequency for the pulses in each burst package to a particular value.

11. The method of claim 10 wherein the particular value constitutes a highest available switching frequency.

12. An integrated circuit comprising: a direct current (DC)-output converter having a control circuit configured to adjust a number of switching pulses per burst cycle as a function, at least in part, of output loading by controlling burst frequency with respect to at least one predetermined threshold frequency, wherein the control circuit is configured to adjust a number of switching pulses per burst cycle by, at least in part, regulating a frequency of bursting with respect to the at least one predetermined threshold frequency by dynamically controlling a number of pulses in each burst package.

13. The integrated circuit of claim 12 wherein the DC-output converter comprises an alternating current (AC)-to-DC converter.

14. The integrated circuit of claim 12 wherein the predetermined threshold frequency comprises a non-audible frequency, such that the control circuit adjusts the number of switching cycles as a function of the output loading in order to prevent the burst frequency from constituting an audible signal.

15. The integrated circuit of claim 14 wherein the control circuit is configured to only adjust the number of switching pulses per burst cycle when the output loading is less than a predetermined level of loading.

16. The integrated circuit of claim 12 wherein the control circuit is further configured to dynamically control the number of pulses in each burst package while also clamping pulse frequency for the pulses in each burst package to a particular value.

17. The integrated circuit of claim 16 wherein the particular value constitutes a highest available switching frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above needs are at least partially met through provision of adaptive burst generation for use with a DC-output converter apparatus and method described in the following detailed description, particularly when studied in conjunction with the drawings, wherein:

(2) FIG. 1 comprises a flow diagram as configured in accordance with various embodiments of these teachings;

(3) FIG. 2 comprises timing diagrams as configured in accordance with various embodiments of these teachings;

(4) FIG. 3 comprises timing diagrams as configured in accordance with various embodiments of these teachings;

(5) FIG. 4 comprises a block diagram as configured in accordance with various embodiments of these teachings;

(6) FIG. 5 comprises timing diagrams as configured in accordance with various embodiments of these teachings;

(7) FIG. 6 comprises a block diagram as configured in accordance with various embodiments of these teachings;

(8) FIG. 7 comprises a graph as configured in accordance with various embodiments of the invention;

(9) FIG. 8 comprises a graph as configured in accordance with various embodiments of these teachings; and

(10) FIG. 9 comprises graphs as configured in accordance with various embodiments of these teachings.

(11) Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present teachings. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present teachings. Certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. The terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above except where different specific meanings have otherwise been set forth herein.

SUMMARY

(12) Generally speaking, these various embodiments are configured to apply with respect to a direct current (DC)-output converter including both alternating current (AC)-to-DC converters and DC-to-DC converters. These teachings provide for adjusting a number of switching cycles per burst as a function, at least in part, of converter output loading. This adjustment can be made by controlling burst frequency with respect to at least one predetermined threshold frequency. By one approach the predetermined threshold frequency comprises a non-audible frequency such that the number of switching cycles is adjusted in a way that prevents the burst frequency from itself constituting an audible signal.

(13) By one approach the aforementioned adjustment of the number of switching cycles per burst only occurs when the output loading is less than a predetermined level of loading. At higher levels of loading amplitude modulation can be employed as per prior art practice in these regards.

(14) By one approach these teachings also provide for clamping the pulse frequency for the pulses in each burst package to a particular value when dynamically controlling the number of pulses in each burst package. The aforementioned particular value may constitute, for example, a highest available switching frequency.

(15) So configured, application of these teachings can yield a number of benefits. In particular, these teachings greatly reduce or eliminate prior issues concerning burst output ripple and audible noise and also provide better light load efficiency without requiring considerably larger capacitors that typify prior art approaches. These teachings will also permit triggering a burst mode of operation at heavier loads and packing more switching pulses for increased efficiency over a wider load range. It will also be appreciated that these teachings are flexible in practice and, for example, can be applied for both conventional flyback and active clamped flyback topologies.

DETAILED DESCRIPTION

(16) FIG. 1 presents a process 100 that generally accords with these teachings. That said, it will be understood that this process 100 as described includes certain specifics for the sake of an illustrative example but that such specific details are not necessarily essential to the practice of these teachings.

(17) Generally speaking, at block 101 these teachings provide for responding differently to different loading levels for a DC-output converter. In particular, normal loading levels can be handled using one approach while lighter-than-normal loading levels are handled using a second, different approach. In this example these differences in approach are represented, in part, as a function of V.sub.C which represents a control voltage used to control peak switching current flowing through a sensing resistor corresponding to the converter. As shown at block 102, during normal loading conditions this control voltage V.sub.C is itself controlled using amplitude modulation techniques that accord with well understood prior art technique in these regards. (Those techniques being well known, further elaboration is not presented here in those regards.)

(18) As shown at block 103, under light loading conditions (for example, at 50 percent loading or less) this process 100 sets V.sub.C to a predetermined value designated herein as MODE. At block 104 this process 100 then provides for regulating the burst frequency F.sub.burst for an adaptive burst generator described herein to cause the latter to approximate a reference frequency F.sub.ref1 and therefore remain above audible frequencies by adjusting the number N.sub.sw of pulse width modulation switching signal pulses (that serve to control the on and off state for a semiconductor switch on the low side of the corresponding converter) PWML in a given burst cycle. At the same time, the switching frequency F.sub.sw for the PWML pulses is clamped to a predetermined switching frequency such as a highest available switching frequency.

(19) Further details in these regards appears below. If desired, at very lightly loaded conditions (such as only 10 percent or less loading), and as denoted by optional block 105, these teachings will accommodate further reducing V.sub.C from MODE to a lower setpoint denoted here as V.sub.C_LL. This modification to the adaptive burst mode control approach disclosed herein can occur, for example, when N.sub.sw=1 and f.sub.burst=f.sub.ref1. When utilizing this particular approach this process 100 can accommodate again setting V.sub.c to MODE from V.sub.c_LL when N.sub.sw=1 and f.sub.swf.sub.ref2.

(20) Illustrative examples in the foregoing regards are well represented in FIGS. 2 and 3 and will be further referenced in context with the operational description appearing below. (FIGS. 2 and 3 are drawn in vertical alignment such that, for example, vertically aligned leading and trailing pulse edges in fact represent such temporal alignment in an operating circuit.) To ensure clarity as regards nomenclature employed herein, the following expressions will be understood to have the following corresponding meanings. ACFActive Clamped Flyback (one available and illustrative converter topology for an AC/DC or DC/DC converter) Bursta signal burst that contains a specific number of grouped switching pulses (in these cases PWML and PWMH) that regulate the output power of the converter F.sub.burstburst frequency (measured, for example, in hertz and which constitutes the inverse of the burst period T.sub.burst that represents the cycle or periodicity of V.sub.on/off) f.sub.swswitching frequency (measured, for example, in hertz and which constitutes the inverse of the switching period T.sub.sw that represents the cycle or periodicity of PWML and PWMH) N.sub.swthe number of PWML pulses in a burst period PWMLthe switching signal used to control the on and off state for the semiconductor switch on the low side of a converter PWMHthe switching signal used to control the on and off state for the semiconductor switch on the high side of a converter T.sub.on(burst) the on time of the V.sub.on/off signal T.sub.off(burst) the time of the V.sub.on/off signal V.sub.on/offa voltage control signal used to determine the number of PWM pulses sent out to the semiconductor switch within the T.sub.on(burst) window of each burst period

(21) Referring now to FIGS. 4 and 5, an illustrative example of an adaptive burst generator 400 configured in accordance with these teachings will be described.

(22) A comparator 401 compares the aforementioned MODE signal with a feedback signal FB provided by the voltage regulator that comprises a part of the corresponding converter. FIG. 2 provides an illustrative example for a V.sub.C signal. In particular, FIG. 2 illustrates that the V.sub.C signal can have a first (lowest) value (V.sub.C-LL) if desired, the aforementioned MODE value that corresponds as described herein to the Adaptive Burst Mode (ABM) state of operation, and finally a ramped value that corresponds as described herein to an Amplitude Modulation (AM) state of operation.

(23) The output of this comparator 401 couples to the input of an OR gate 402, the remaining input of which receives an EN_burst signal (described below). The output of this OR gate 402 couples to the set input of a flip-flop 403, the output of which provides the aforementioned V.sub.on/off signal. FIG. 3 presents an illustrative example in these regards where the V.sub.on/off signal toggles between an on state corresponding to the illustrated T.sub.on(burst) voltage level and an off state corresponding to the illustrated T.sub.off(burst) voltage level. As noted above, and as well illustrated in FIG. 3, this V.sub.on/off signal constitutes a voltage control signal that determines the number of Pulse Width Modulation (PWM) pulses (in this case, PWML signals and/or PWMH signals (to be applied, for example, to a high-side switch of an Active Clamped Flyback (ACF) component) sent out to a switch within the T.sub.on(burst) window of each burst period.

(24) An AND gate 404 receives the aforementioned EN_burst signal, the aforementioned PWML signal (see FIGS. 3 and 5), and the aforementioned V.sub.on/off signal. The output of the AND gate 404 couples to an UP counter 405 having an output that couples to the positive input of a digital comparator 406. The output of the latter then couples to the reset input of the UP counter 405 and to the reset port of the aforementioned flip-flop 403. With this signal chain, the UP counter 405 calculates the total pulse count of PWML for every burst cycle, when V.sub.on/off and EN_burst go high. The total pulse number for a burst cycle is sent to the positive input of the digital comparator 406 to compare with a reference maximum pulse number. The negative input of the digital comparator 406 receives a signal corresponding to N.sub.swf(ref) (see FIGS. 3 and 5) as provided by a limiter 407. N.sub.sw(ref) is a reference value corresponding, in this case, to the maximum value for N.sub.sw (which refers, at noted above, to the maximum number of PWML pulses in a burst period (see FIG. 2 as well)) that can range between 1 and N.sub.max. The limiter 407, in turn, receives input from an integrator 408 that receives the V.sub.on/off signal, an f.sub.ref signal (see FIG. 2), and the output from an F.sub.burst detector 409 that itself responds to the V.sub.on/off signal (where the F.sub.burst signal output by the detector 409 represents the burst frequency and therefore constitutes the inverse of the burst period T.sub.burst that represents the periodicity of the V.sub.on/off signal). With this signal chain, when the PWML pulse number from the UP counter 405 reaches the target N.sub.sw(ref) at the output of the limiter 407, V.sub.on/off will go low and reset the UP counter 405 to prepare for recounting the PWML pulses of the next burst cycle.

(25) At the same time, the F.sub.burst detector 409 calculates the burst frequency of this burst cycle to compare with the target audible noise-free burst frequency f.sub.ref. When the digital integrator 408 determines that the burst frequency is less than f.sub.ref, N.sub.sw(ref) reduces by one to be the maximum pulse count of the next burst cycle. On the other hand, when the comparison result of the digital integrator 408 indicates that the burst frequency is higher than f.sub.ref, N.sub.sw(ref) increases by one to be the maximum pulse count of the next burst cycle. (The limiter 407 constrains the output of the digital integrator 408 to only be able to provide N.sub.sw(ref) within a controllable range of ABM to the digital comparator 406.

(26) FIG. 5 presents an illustrative view of various input, output, and intermediary signals and waveforms at various points within the adaptive burst generator 400 in temporal synchronicity with one another for a given set of illustrative operating conditions.

(27) FIG. 6 presents the adaptive burst generator 400 in an illustrative application setting. In this illustrative example the voltage regulator (not shown) of the converter couples through a photo coupler 601 to provide the aforementioned FB signal to both the adaptive burst generator 402 and a comparator 602. A resistor circuit 603 provides the aforementioned MODE signal to both the adaptive burst generator 400 and to the remaining input of the aforementioned comparator 602 via a capacitor 604.

(28) The above-described comparator 602 and resistor circuit 603 are part of a mode setting circuit 605 that includes a switch 606 that responds to the EN_burst signal provided by the comparator 602. This switch 606, in this illustrative example, sets the V.sub.c control voltage to be either the FB signal or the static MODE value as a function of the EN_burst signal.

(29) That V.sub.C control voltage and the V.sub.on/off signal output of the adaptive burst generator 400 are provided to a peak current loop 607. In particular, the V.sub.C control voltage couples to an input of a comparator 608, the remaining input of which receives a signal CS corresponding to the voltage across a sense resistor 609 that detects the switch state of a corresponding semiconductor switch 610 that comprises a part of the converter. The V.sub.on/off signal, in turn, couples to an input of an OR gate 611. The remaining input of that OR gate 611 couples to a zero-voltage switch (ZVS) mode control circuit 612 (sometimes also referred to as a valley mode control circuit). Such switches are known in the art and serve to deliver a quantized packet of energy to the converter output with switching occurring at zero voltage to thereby essentially comprise a lossless switch. As such switches are known in the art, further elaboration in these regards is not provided here.

(30) The output of the OR gate 611 couples to the set input of a flip-flop 613, the reset port of which couples to the output of the aforementioned peak current loop comparator 608. The output of the flip-flop 613 in turn couples to one input of an AND gate 614, the remaining input of which receives the V.sub.on/off signal from the adaptive burst generator 400. The output of this AND gate 614 provides the aforementioned PWML signal to a driver 615 that couples and corresponds to the aforementioned semiconductor switch 610.

(31) The aforementioned control voltage V.sub.c serves to control the peak switching current flowing through the aforementioned sense resistor 609. That V.sub.c, in turn, is set by the mode setting circuit 605 described above as a function of the EN_burst signal. When the EN_burst signal is low, V.sub.c tracks the voltage signal FB from the converter voltage regulator. When the EN_burst signal is high, V.sub.c clamps to a programmable voltage signal referred to herein as the MODE signal.

(32) As noted above, under extremely light loading conditions V.sub.c can be clamped instead to V.sub.c_LL, the latter being a fixed value that is lower than the MODE clamping voltage. Lowering the V.sub.c clamping voltage when the converter is only very lightly loaded further reduces the peak switching current to thereby further reduce output ripple and audible noise. In general practice, a ratio of 3 to 1 or 4 to 1 can be useful to designate the range between a highest possible V.sub.c during the amplitude modulation mode of operation and the setting of V.sub.c_LL during use of the adaptive burst generator 400.

(33) So configured, and as well illustrated in FIG. 7, the adaptive burst generator 400 limits burst ripple to something less than ripple that occurs at full load, thereby avoiding a need to oversize a corresponding output capacitor for the converter. This adaptive burst generator 400 also provides fast model transition and enables high bandwidth design to further support and permit reduced output capacitor size. Those skilled in the art will appreciate that these teachings enable smooth mode jumping and thereby avoid undue transients and other disturbances. And as well illustrated in FIG. 8, experimental verification for the described use of adaptive burst generation indeed leads to increased efficiency at lower levels of loading.

(34) These teachings will also readily accommodate including a mode transition technique if desired. In particular, as a transition mechanism when switching between the aforementioned amplitude modulation approach and the above-described adaptive burst approach (where V.sub.C equals MODE), the teachings will employ using bursts where unlimited switching pulses are permitted. FIG. 9 depicts an illustrative example in these regards where this burst with unlimited switching pulses approach occurs in a limited operating window between where FB equals MODE and MODE+V.sub.offset (where V.sub.offset is selected to best suit the needs of a given application setting). Using this approach provides a buffer between the other two modes and helps the mode transition itself become smoother.

(35) Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the scope of the invention, and that such modifications, alterations, and combinations are to be viewed as being within the ambit of the inventive concept.