Electronic control unit and electric power steering apparatus equipped with the same

Abstract

An electronic control unit diagnoses a short failure of an inverter FETs and diagnoses whether the failure of the FET-short detecting section has occurred. The unit controls a motor through an inverter including a bridge having an upper-stage FETs and a lower-stage FETs via an MCU, having: an FET-short detecting section to detect a short failure of the upper-stage FETs and the lower-stage FETs based on respective connection point voltages of the upper-stage FETs and the lower-stage FETs; and a diagnostic function to detect a failure of the FET-short detecting section. The diagnostic function diagnoses the failure of the FET-short detecting section at start up and turns-OFF the upper-stage FETs and the lower-stage FETs when the failure is detected. The FET-short detecting section diagnoses the short failure of the upper-stage FETs and the lower-stage FETs when the failure of the FET-short detecting section is not detected.

Claims

1. An electronic control unit that driving-controls a motor, via an inverter comprising a bridge of upper-stage field-effect transistors (FETs) and lower-stage FETs, by inputting a duty signal of a pulse width modulation (PWM) calculated in a micro controller unit (MCU) into a gate driving section, comprising: an FET-short detecting section which detects a short failure of at least one side of said upper-stage FETs and said lower-stage FETs based on voltage-divided voltages obtained by voltage-dividing connection point voltages of said upper-stage FETs and said lower-stage FETs by using diagnostic resistor voltage-dividing circuit, and outputs an error notification; and a detecting-section-failure diagnostic function which is included in said MCU, and detects a failure of said FET-short detecting section, wherein said FET-short detecting section comprising: a serial peripheral interface (SPI) communication circuit; a threshold setting section to set a threshold based on a setting signal from said SPI communication circuit; a comparing section to compare said voltage-divided voltages with said threshold; an AND-circuit to input a compared result of said comparing section and said duty signal; a digital filter to input a setting changing signal, for changing a setting time, from said SPI communication circuit and an output of said AND-circuit and to judge a continuation; and an error logical circuit that inputs a filter output of said digital filter, outputs said error notification and notifies to said MCU via an NDIAG terminal, and turns-OFF said upper-stage FETs and said lower-stage FETs via said gate driving section, wherein said detecting-section-failure diagnostic function diagnoses said failure of said FET-short detecting section at start up and turns-OFF said upper-stage FETs and said lower-stage FETs when said failure of said FET-short detecting section is detected, and diagnoses said short failure of said upper-stage FETs and said lower-stage FETs when said failure of said FET-short detecting section is not detected.

2. The electronic control unit according to claim 1, wherein when said short failure is detected, at least FETs which one of said short failure is not detected are turned-OFF.

3. The electronic control unit according to claim 1, wherein said FET-short detecting section detects said short failure based on a first threshold for said upper-stage FETs and a second threshold for said lower-stage FETs.

4. The electronic control unit according to claim 2, wherein said FET-short detecting section detects said short failure based on a first threshold for said upper-stage FETs and a second threshold for said lower-stage FETs.

5. The electronic control unit according to claim 3, wherein said detecting-section-failure diagnostic function is a diagnostic function that outputs a gate-OFF signal which forcibly turns-OFF said inverter from said MCU at start up, forcibly establishes an abnormality condition of said short failure by calculating with said duty signals of said upper-stage FETs or said duty signals of said lower-stage FETs, and outputs a predetermined signal to said NDIAG terminal.

6. The electronic control unit according to claim 4, wherein said detecting-section-failure diagnostic function is a diagnostic function that outputs a gate-OFF signal which forcibly turns-OFF said inverter from said MCU at start up, forcibly establishes an abnormality condition of said short failure by calculating with said duty signals of said upper-stage FETs or said duty signals of said lower-stage FETs, and outputs a predetermined signal to said NDIAG terminal.

7. The electronic control unit according to claim 5, wherein said detecting-section-failure diagnostic function has a diagnostic function that outputs a signal which forcibly transits said error notification from said MCU to an FET-short detecting state in order to confirm being capable of turning-OFF and stopping said inverter in a case that said FET-short detecting section detects said short failure, calculates with said duty signals of said upper-stage FETs or said duty signals of said lower-stage FETs, monitors said connection point voltages, and diagnoses that a stop of said inverter is completed.

8. The electronic control unit according to claim 6, wherein said detecting-section-failure diagnostic function has a diagnostic function that outputs a signal which forcibly transits said error notification from said MCU to an FET-short detecting state in order to confirm being capable of turning-OFF and stopping said inverter in a case that said FET-short detecting section detects said short failure, calculates with said duty signals of said upper-stage FETs or said duty signals of said lower-stage FETs, monitors said connection point voltages, and diagnoses that a stop of said inverter is completed.

9. The electronic control unit according to claim 1, wherein a dark current suppressing switch is further interposed between control system circuits, said MCU switches-ON said dark current suppressing switch at start up, said detecting-section-failure diagnostic function turns-OFF said upper-stage FETs and said lower-stage FETs when said short failure is detected, and said MCU switches-OFF said dark current suppressing switch when an operation of said MCU is stopped.

10. The electronic control unit according to claim 9, wherein said dark current suppressing switch is transistor kind including an FET, and a parasitic diode is connected in parallel with said transistor for a reverse connection protection.

11. The electronic control unit according to claim 9, wherein said control system circuits include at least said MCU, said resistor voltage-dividing circuit and said FET-short detecting section.

12. An electric power steering apparatus that is equipped with the electronic control unit according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying drawings:

(2) FIG. 1 is a configuration diagram showing a general outline of an electric power steering apparatus;

(3) FIG. 2 is a block diagram showing a configuration example of a control system of an electric power steering apparatus;

(4) FIG. 3 is a circuit diagram showing a general configuration example of a PWM-control section and an inverter;

(5) FIG. 4 is a circuit diagram showing a configuration example of the inverter that has a conventional protection function;

(6) FIG. 5 is a block diagram showing a configuration example of the present invention;

(7) FIG. 6 is a block diagram showing a detail of a resistor voltage-dividing circuit for diagnosis;

(8) FIG. 7 is a circuit diagram showing a detail of a portion of a configuration example (an FET-short detecting section) of the present invention (the first embodiment);

(9) FIG. 8 is a block diagram showing a configuration example of an NDIAG terminal;

(10) FIG. 9 is a block diagram showing a detail of the FET-short detecting section (U-phase);

(11) FIG. 10 is a block diagram showing a detail of the FET-short detecting section (U-phase);

(12) FIG. 11 is a flowchart showing an operation example (the first embodiment) of the present invention;

(13) FIGS. 12A to 12J are timing flowcharts showing the operation example of the present invention;

(14) FIGS. 13A to 13J are timing flowcharts showing the operation example of the present invention;

(15) FIG. 14 is a block diagram showing the configuration example (the second embodiment) of the present invention; and

(16) FIG. 15 is a flowchart showing the operation example (the second embodiment) of the present invention.

MODE FOR CARRYING OUT THE INVENTION

(17) The present invention is an electronic control unit that driving-controls a motor, especially an assist control motor for a vehicle, by means of an MCU (a CPU, an MPU, a microcomputer and the like) via an inverter which comprises an FET bridge having upper-stage FETs (High side) and lower-stage FETs (Low side)) as semiconductor switching devices. The electronic control unit according to the present invention comprises an FET driving circuit that includes a gate driving section to turn-ON or turn-OFF and drive the FETs of the inverter, an FET-short detecting section to detect a short failure of the upper-stage FETs and the lower-stage FETs of the inverter based on the respective connection point voltages of the upper-stage FETs and the lower-stage FETs, and a detecting-section-failure diagnostic function that is incorporated in an inside of the MCU or an external of the MCU in order to diagnose the failure (including an abnormality) of the FET-short detecting section. The FET-short detecting section detects the FET-short failure occurred at one of the upper stage and the lower stage of the inverter, the upper-stage FETs and the lower-stage FETs (at least the FETs that the short failure is not detected) are turned-OFF when the FET-short failure is detected.

(18) At start up time of the electric power steering apparatus, the detecting-section-failure diagnostic function in the MCU diagnoses the failure of the FET-short detecting section, the gate driving section turns-OFF the FETs of the inverter, that is, an operation of the inverter is stopped when the failure of the FET-short detecting section is detected. Or, at start up time of the electric power steering apparatus, a dark current suppressing switch is switched-ON and the detecting-section-failure diagnostic function in the MCU diagnoses the failure of the FET-short detecting section, the FETs of the inverter are turned-OFF by the gate driving section and the dark current suppressing switch is switched-OFF when the failure of the FET-short detecting section is detected.

(19) In addition, in the present invention, it is possible to confirm that the FET-short detecting section correctly works by using the detecting-section-failure diagnostic function of an inside of the MCU or an external, and the inverter FETs are immediately turned-OFF when the failure of the FET-short detecting section is detected. Thus, it is impossible to detect the occurrence of the no-detection failure of the FET-short detecting section corresponding to the first failure by turning-OFF the inverter FETs when the failure of the FET-short detecting section is occurred, and thereafter it is possible to prevent, by continuing the current flowing, that the overcurrent continues flowing through the FETs when the short failure of the inverter corresponding to the second failure is occurred and to maintain the safety of the electric power steering apparatus. By using the FET-short detecting section secured the safety as described above, it is possible to remove the expensive power supply relay or the switch which is disposed on a power supply line of the inverter for blocking the overcurrent which is generated in an occurrence time of the FET-short failure of the inverter. Therefore, it is possible to effectively achieve the miniaturization and the cost down.

(20) Embodiments according to the present invention will be described with reference to the drawings. An example which is applied the electronic control unit of the present invention to the electric power steering apparatus will be described as the embodiments.

(21) As shown in FIG. 5, the electronic control unit according to the present invention comprises an MCU 100 to perform an overall control, an FET 13A for a reverse connection protection that is interposed between a battery 13 and a power supply VR and is switched-ON or switched-OFF based on a switching signal SW2 from the MCU 100, a gate driving section 150 to form an FET driving circuit which drives FETs FET1 to FET6 of an inverter 37 by duty signals HD1 to HD3 (the upper-stage (High side) FETs) and LD4 to LD6 (the lower-stage (Low side) FETs) which are calculated in the MCU 100, a resistor voltage-dividing circuit for diagnosis 120 that voltage-divides connection point (middle point) voltages of the inverter 37 (sources (S) of the upper-stage FETs and drains (D) of the lower-stage FETs) with a resistor circuit, an FET-short detecting section 110 to detect an FET-short failure of the inverter 37 via the resistor voltage-dividing circuit for diagnosis 120, a dark current suppressing switch 130 that is connected to the power supply VR and is switched-ON or switched-OFF with a switching signal SW1 from the MCU 100, and a resistor voltage-dividing circuit for power supply 140 that shifts a level coincident with an input voltage range of the MCU 100 in order to detect a voltage HS from the dark current suppressing switch 130.

(22) The FET 13A is the FET for the reverse connection protection, and prevents from a short failure with a parasitic diode 13D of the inverter FET at a time of the reverse connection. The present invention removes the power supply relay that blocks the power supply VR by using the FET-short detecting function, and deals with the short failure with only the FET 13A for the reverse connection protection. As a trade-off, since the dark current flows via the parasitic diode 13D of the FET 13A for the reverse connection protection, the dark current suppressing switch 130 is provided as the above countermeasure. The voltage HS from the dark current suppressing switch 130 is supplied to the resistor voltage-dividing circuit for diagnosis 120, the FET-short detecting section 110 and the resistor voltage-dividing circuit for power supply 140. Zener diodes Z1 to Z6 for absorbing an overvoltage are connected between the gates and the sources of the FETs FET1 to FET6 of the inverter 37, respectively.

(23) A detail of the resistor voltage-dividing circuit for diagnosis 120 is a configuration (three-phase) as shown in FIG. 6. Connection point voltages of the upper-stage FETs and the lower-stage FETs are voltage-divided by resistors R121 and R122, which are interposed between the power supply (VR) and the ground (GND), and voltage-divided voltages are supplied to the FET-short detecting section 110 via resistors R11 to R13 with three-phase. When the upper-stage FETs and the lower-stage FETs are turned-OFF, the connection point voltages of the upper-stage FETs and the lower-stage FETs are voltage-divided into VR, and voltage-divided voltages SHU (U-phase), SHV (V-phase) and SHW (W-phase) of the respective phases are outputted.

(24) The FET-short detecting section 110 detects the short failure of the upper-stage FETs and the lower-stage FETs of the inverter 37 based on the voltage-divided voltages SHU, SHV and SHW which are obtained at the voltage-dividing circuit for diagnosis 120, detects whether the short failure occurs at the upper-stage FETs or the lower-stage FETs of the inverter 37 and outputs an error notification EN when the short failure of the FETs is detected. The error notification EN is inputted into the gate driving section 150, and the gate driving section 150 makes the outputs HD1g to LD6g set an L signal, and turns-OFF the FETs FET1 to FET6 of the inverter 37. The FET-short detecting section 110 notifies the detection of the short failure to the MCU 100 via an NDIAG terminal of a notification terminal, transmits an error signal ERA to an alarm input circuit 104, outputs a gate-OFF command GF via the alarm input circuit 104 and stops the operation of the inverter 37 via the gate driving section 150 based on the gate-OFF command GF.

(25) The MCU 100 has the detecting-section-failure diagnostic function for diagnosing the failure of the FET-short detecting section 110. When the MCU 100 detects the failure of the FET-short detecting section 110 in the diagnosis, the MCU 100 outputs the gate-OFF command GF via the alarm input circuit 104 and stops the operation of the inverter 37 via the gate driving section 150 based on the gate-OFF command GF. Or, the MCU 100 does not use the alarm input circuit 104, outputs the gate-OFF command GF with the duty signals HD1 to HD3 and LD4 to LD6 to the gate driving section 150, and may stop the working of the inverter 37.

(26) FIG. 7 shows a detail configuration example of the FET-short detecting section 110 and the gate driving section 150, and the voltage-divided voltages SHU, SHV and SHW from the resistor voltage-dividing circuit for diagnosis 120 are inputted into negative terminal inputs () of upper stage-side (H-side) comparators (three comparators) 117 and are inputted into positive terminal inputs (+) of lower stage-side (L-side) comparators (three comparators) 117 in the FET-short detecting section 110. The FET-short detecting section 110 includes a serial peripheral interface (SPI) communication circuit 112, and the SPI communication circuit 112 transmits an H-side setting signal vthh_Sh and an L-side setting signal vthl_Sh to threshold setting sections 113 and 114, respectively. The voltage HS is supplied to the threshold setting section 113, and the threshold setting section 114 is grounded. The threshold setting sections 113 and 114 set thresholds HREF and LREF based on the setting signals vthh_Sh and vthl_Sh, respectively, and the threshold HREF is HSvthh_Sh and the threshold LREF is vthl_Sh. The threshold HREF is inputted into positive terminal inputs (+) of the H-side comparators 117, and the threshold LREF is inputted into negative terminal inputs () of the L-side comparators 117. The comparators 117 respectively compare the connection point (voltage-divided) voltages SHU, SHV and SHW with the thresholds HREF and LREF in accordance with a following Table 1, and comparator outputs shuh, shvh, shwh, shul, shvl and shwl which have a binary value (H or L) are outputted.

(27) TABLE-US-00001 TABLE 1 comparator comparator input input output signal abnormality state SHU > LREF shul = H LD4 = H external FET short of HD1g SHV > LREF shvl = H LD5 = H external FET short of HD2g SHW > LREF shwl = H LD6 = H external FET short of HD3g SHU < HREF shuh = H HD1 = H external FET short of LD4g SHV < HREF shvh = H HD2 = H external FET short of LD5g SHW < HREF shwh = H HD3 = H external FET short of LD6g Here, HREF=HSvthh_Sh (H-side detection threshold) and LREF=vthl_Sh (L-side detection threshold).
That is, the upper-stage comparators corresponding to the upper-stage FETs FET1 to FET3 satisfy a below Equation 1, and the lower-stage comparators corresponding to the lower-stage FETs FET4 to FET6 satisfy a below Equation 2.
shuh=H when SHU<HREF, and shuh=L when SHU>HREF
shvh=H when SHV<HREF, and shvh=L whenSHV>HREF
shwh=H when SHW<HREF, and shwh=L when SHW>HREF[Equation 1]
shul=H when SHU>LREF, and shul=L when SHU<LREF
shvl=H when SHV>LREF, and shvl=L when SHV<LREF
shwl=H when SHW>LREF, and shwl=L when SHW<LREF[Equation 2]

(28) In the above Table 1, LD4 denotes an input signal (a duty signal) from the MCU 100 (a duty calculating section 101) for driving the lower-stage FET4 of the U-phase, LD5 does an input signal (a duty signal) from the MCU 100 for driving the lower-stage FET5 of the V-phase, LD6 does an input signal (a duty signal) from the MCU 100 for driving the lower-stage FET6 of the W-phase, HD1 does an input signal (a duty signal) from the MCU 100 for driving the upper-stage FET1 of the U-phase, HD2 does an input signal (a duty signal) from the MCU 100 for driving the upper-stage FET2 of the V-phase and HD3 does an input signal (a duty signal) from the MCU for driving the upper-stage FET3 of the W-phase. These duty signals LD4 to HD3 are respectively inputted into corresponding AND-circuits 116.

(29) Comparison results shuh to shwl from the six comparators 117 and the duty signals LD4 to HD3 are inputted into six AND-circuits 116, and the respective outputs of the AND-circuits are inputted into six filters 115. The respective filters 115 are digital filters for judging whether for example, a 10 [ps]-continuation is satisfied or not, and an inputting clk4m is a clock signal for counting a time 10 [s]. A setting changing signal CCH for changing a count time is inputted into the filters 115 from the SPI communication circuit 112. As well, the SPI communication circuit 112 is an interface with the MCU 100, and is able to change the filtering time and is in a pseudo able to set an internal value of error logic to an error state.

(30) The respective outputs shuho, shvho, shwho, shulo, shvlo and shwlo of the filters 115 are inputted into an error logic circuit 111, and the error logic circuit 111 outputs the error notifications EN (gate_en_u, gate_en_v, gate_en_w and gate_en_r) and notifies the error to the MCU 100 via the NDIAG terminal. The error logic circuit 111 is a circuit which turns-OFF the output of the NDIAG and the upper-stage FETs FET1 to FET3 and the lower-stage FETs FET3 to FET 6 based on an abnormality judging result of the FET-short detection, and enables to change the internal value from the SPI communication circuit 112 in order to judge the failure of the FET-short detection.

(31) As shown in FIG. 8, an operation check of the NDIAG terminal can be performed by setting a register diag_dg=1, which comprises the SPI communication circuit 112 and the error logic circuit 111, by using the SPI communication of the MCU 100, and then by checking whether the NDIAG function is normally operated or not. Besides, the registers are various memories in the error logic circuit 111, and indicate status information and configuration information of an integrated circuit (IC).

(32) That is, when setting the register diag_dg=1 or 0 by using the SPI communication, in a case of the register diag_dg=0, the NDIAG=H is obtained by a denying section (NOT) 103, and in a case of the register diag_dg=1, the NDIAG=L is obtained by the denying section 103. It is possible to confirm whether the NDIAG operates normally or not by performing a comparison of expectation values of the NDIAG due to the MCU 100. The NDIAG=H is obtained by setting again the register diag_dg=0, and the normal abnormality detecting function becomes available.

(33) Next, the FET-short-detection operation check will be described by showing the configuration of the U-phase in FIG. 9 and FIG. 10. FIG. 9 shows the FET-short detection and FIG. 10 does a confirmation configuration that the FET driving is OFF at the time of the short detection.

(34) In FIG. 9, it is possible to confirm whether the short detecting functions of the respective FETs FET1 to FET6 work normally or not by that the MCU 100 sets ALARM1 or ALARM2. That is, the ALARM1=L or the ALARM2=L is inputted into an alarm input circuit 104, and the gate-OFF command GF, which is an input of the driving logic section 151, is set to H. Since the output HD1g of the driving logic section 151 is L by setting the ALARM1=L or the ALARM2=L, the voltage-divided voltage SHU is the middle voltage between the power supply (VR) and the ground (GND) and then the output shul of the comparator 117 is H. Since the duty signal LD4 from the MCU 100 is H and the output shul of the comparator 117 is H, the output (a register scul) of the AND-circuit 116 is H, the state becomes to the short detecting state, and the NDIAG becomes to L. Accordingly, it is possible to diagnose whether the short detecting function works normally or not by monitoring the NDIAG. The NDIAG becomes to H by clearing the register (scul) in the error logic circuit 111 by means of the SPI communication.

(35) FIG. 10 shows the confirmation configuration that the FET driving is OFF at the time of the short detection. By setting respective phase registers shuh_dg, shul_dg, shvh_dg, shvl_dg, shwh_dg and shwl_dg by means of the SPI communication of the MCU 100, it is capable of confirming that the FET1 to FET6 are turned-OFF at the time of the short detection of the respective FETs FET1 to FET6. That is, in a case of the register shul_dg=1, a register sh_op is set to 001 or 010 (the FET driving is turned-OFF at the time of the short detection) with the SPI communication of the SPI communication circuit 112 and the register shul_dg is set to 1 with the SPI communication. The register scul is 1 (the short detecting state) at a state of the register shul_dg=1, and then the NDIAG becomes to L. In the state of the NDIAG=L, when the duty signal LD4=H is inputted from the MCU 100, it is possible to detect that the FET1 and the FET4 are turned-OFF by monitoring the connection point voltage of the upper stage FET1 and the lower stage FET4. The register shul_dg=0 and NDIAG=H are obtained by setting again the register shul_dg=0, and the normal abnormality detecting function becomes available.

(36) As well, the error logic circuit 111 performs a logic built-in self test (LBIST). In a case of the register shul_dg=0, when the unit is actually the short detecting state, the NDIAG becomes to L. Similarly, the operation checks with reference to the another phases can be performed.

(37) In such a configuration, the operation example (the first embodiment) will be described with reference to the flowchart of FIG. 11.

(38) When the operation is started (Step S1), the detecting-section-failure diagnostic function in the MCU 100 is worked (Step S2), and diagnoses whether the FET-short detecting section 110 is failed or not (Step S3). When the failure of the FET-short detecting section 110 is diagnosed by the detecting-section-failure diagnostic function, the MCU 100 outputs the ALARM1 or the ALARM2, the alarm input circuit 104 outputs the gate-OFF command GF (Step S4), and the inverter 37 is stopped (Step S5) by inputting the gate-OFF command GF into the gate driving section 130.

(39) In a case that the failure of the FET-short detecting section 110 is not detected at the above Step S3, the FET-short detecting section 110 diagnoses the short failure of the FETs of the inverter (Step S10). The FET-short detecting section 110 diagnoses the upper-stage FETs and the lower-stage FETs of the inverter 37 by comparing the status of the above Table 1, and at first judges whether the upper-stage FETs are failed or not (Step S11). In a case that the upper-stage FETs are failed, the lower-stage FETs are turned-OFF with the error notifications EN, and further the upper-stage FETs are also turned-OFF (Step S12). Next, it is judged whether the lower-stage FETs are failed or not (Step S13). In a case that the lower-stage FETs are failed, the upper-stage FETs are turned-OFF with the error notifications EN, and further the lower-stage FETs are also turned-OFF (Step S14).

(40) As well, the order of detecting the short failure of the upper-stage FETs and the lower-stage FETs may be changeable.

(41) The detection of the short failure of the lower-stage (L-side) FETs monitors the drain voltages SHU, SHV and SHW of the lower-stage FETs in a state that the upper-stage (H-side) FETs are turned-ON state (the lower-stage FETs are turned-OFF state), and it is judged that the short failure occurs if the drain voltages SHU, SHV and SHW are lower than the threshold HREF. Further, if the drain voltages SHU, SHV and SHW are equal to or higher than the threshold HREF, it is judged that the short failure does not occur. In a case that the short failure is detected, the error notifications EN are transmitted from the FET-short detecting section 110 to the gate driving section 150, and the inverter FETs are turned-OFF. Concretely, if the FETs are not failed in normal, in a case that the upper-stage FETs are turned-ON (=the lower-stage FETs are turned-OFF), the connection point voltages SHU, SHV and SHW are represented by a following Equation 3 as an ON-resistance of the upper-stage FETs is .sub.RON and the current is ION.
connection point voltage=supplying voltage HSRONION[Equation 3]

(42) If the lower-stage FETs are the short failure, the connection point voltages SHU, SHV and SHW are equivalent to 0 [V]. In the present embodiment, the H-side setting signal vthh_Sh and the L-side setting signal vthl_Sh are set to 1 [V]. In order to avoid an erroneous detection, the above values are set to a sufficiently larger value than the ON-resistance .sub.RON of the upper-stage FETs the current ION.

(43) Further, the input signals HD1 to HD3 and LD4 to LD6 of the gate driving section 150 are the duty signals from the MCU 100 in order to drive the FETs (FET1 to FET6) of the inverter 37, and the gate driving section 150 drives the FET1 to the FET6 of the inverter 37 based on these duty signals HD1 to HD3 and LD4 to LD6, respectively. However, the inverter FETs are turned-ON or turned-OFF with a time delay for the inputs of the duty signals HD1 to HD3 and LD4 to LD6, due to a delay of an internal circuit and a capacitance of the inverter FETs. In order to prevent from the erroneous detection of the FET-short failure due to the above time delay, in a case that an input condition of the comparator 117 in the FET-short detecting section 110 only continues for 10 [ps], it is judged that the FET-short is detected.

(44) Next, the operation that the MCU 100 detects the failure of the FET-short detecting section 110 will be described.

(45) At start up, the detecting-section-failure diagnostic function in the MCU 100 diagnoses whether the FET-short detecting section 110 is failed or not. When the FET-short detecting section 110 is failed, the MCU 100 outputs the ALARM1 or the ALARM2 to the alarm input circuit 104, and the alarm input circuit 104 outputs the gate-OFF command GF to the gate driving section 150 and then turns-OFF the inverter FETs. Concretely, there is provided the resistor voltage-dividing circuit for diagnosis 120 to resistor-voltage-divide so that in a case that the outputs HD1g to LD6g of the gate driving section 150 are OFF, the connection point voltage SHU between the upper-stage FET1 and the lower-stage FET4 of the inverter 37, the connection point voltage SHV between the upper-stage FET2 and the lower-stage FET5 and the connection point voltage SHW between the upper-stage FET3 and the lower-stage FET6 are almost 6 [V] being the inverter power supply voltage (the battery voltage 12 [V])0.5. At start up, the MCU 100 outputs the gate-OFF command GF to forcibly turn-OFF the outputs HD1g to LD6g of the gate driving section 150, and the H signal is inputted into any one of the duty signals HD1 to HD3 and LD4 to LD6 being inputted into the gate driving section 150. Thereby, the abnormality condition of the above FET-short detection is forcibly established, and the MCU 100 diagnoses whether the failure detection by means of the FET-short detecting section 110 is no-detection state or not by monitoring that the logic output of the NDIAG is L (the logic output is H when the short failure is not detected).

(46) Further, in a case that the FET-short detecting section 110 detects the FET-short failure, in order to confirm that the inverter FETs be able to turn-OFF, the MCU 100 outputs the signal (SPI) to forcibly transit the error notifications EN of the FET-short detecting section 110 to the FET-short detecting state, and the H signal is inputted into any one of the duty signals HD1 to HD3 and LD4 to LD6 being inputted into the gate driving section 150. Furthermore, the connection point voltages SHU, SHV and SHW of the upper-stage FETs and the lower-stage FETs of the inverter 37 are monitored. Thereby, the MCU 100 diagnoses that the inverter FETs are turned-OFF. If the inverter FETs are not turned-OFF, in a case that the duty signals HD1 to HD3 are H, the connection point voltages SHU, SHV and SHW are equivalent to the power supply voltage of the inverter 37 (the voltage VR), and in a case that the duty signals LD4 to LD6 are H, the connection point voltages SHU, SHV and SHW are equivalent to 0 [V] (grounded). Consequently, since the above voltages are not the inverter power supply voltage0.5 in a case that the inverter FETs are turned-OFF, it is possible to detect that the inverter FETs are not turned-OFF.

(47) In a case that the MCU 100 diagnoses that the FET-short is detected by the FET-short detecting section 110 and the inverter FETs are not turned-OFF at the time of the FET-short detection, the MCU 100 sets the duty signals HD1 to HD3 and LD4 to LD6 to the gate driving section 150 to L (=OFF) and maintains a safety state (an assist stop state) as the system.

(48) It is possible to confirm that the FET-short detecting section 110 correctly works by using the detecting-section-failure diagnostic function, it is impossible to detect the occurrence of the no-detection failure of the FET-short detecting section 110 corresponding to the first failure by immediately turning-OFF the inverter FETs when the failure is detected, thereafter the short failure of the inverter FETs corresponding to the second failure occurs causing to the works of the inverter FETs, and it is possible to prevent that the overcurrent continuously flows in the FETs thereby to maintain the safety of the system. By using the FET-short detecting section 110 secured the safety as described above, it is possible to remove the expensive power supply relay or the switch which is disposed on the power supply line of the inverter for blocking the overcurrent which is generated in an occurrence time of the FET-short failure of the inverter.

(49) Next, a timing operation example of the FET-short detection will be described with reference to timing charts of FIGS. 12A to 12J and FIGS. 13A to 13J.

(50) FIGS. 12A to 12J show a state that the short failure at the lower-stage (L-side) FETs occurred at a time point t1, the short failure is detected at a time point t2 and the short failure is released at a time point t8. When the short failure is detected at the time point t2, the filter outputs shuho to shwho vary from L to H, the NDIAG is latched to L and the duty signals HD1gto LD6g are latched to OFF, as shown in FIGS. 12H to 12J.

(51) FIGS. 13A to 13J show a state that the short failure at the upper-stage (H-side) FETs occurred and is detected at a time point t10 and the short failure is released at a time point t17. When the short failure is detected at the time point t10, the filter outputs shulo to shwlo vary from L to H, the NDIAG is latched to L and the duty signals HD1g to LD6g are latched to OFF, as shown in FIGS. 13H to 13J.

(52) The dark current suppressing switch 130 made of the semiconductor switch (for example, the FET or the transistor) is provided between the power supply (the voltage VR) of the inverter 37 and the control section such as the MCU 100. The dark current suppressing switch 130 is switched-ON by the MCU 100 after the starting of the MCU 100 and is switched-OFF by the switching signal SW1 when the operation of the MCU 100 is stopped (the MCU 100 is de-energized). Thereby, the dark current, which flows from the power supply (the voltage VR) of the inverter to the control section while the operation of the ECU is stopped (the operation of the MCU is stopped), can be suppressed (the second embodiment).

(53) FIG. 14 shows the second embodiment of the present invention corresponding to FIG. 7, the dark current suppressing switch 130 which comprises the FET 131 is interposed between the power supply VR and the control system, and the output voltage HS of the dark current suppressing switch 130 is supplied to the threshold setting section 113 and so on. A parasitic diode 131D having a function to block the dark current is in parallel connected to the FET 131 of the dark current suppressing switch 130. In the present embodiment, the FET is mentioned as an example. Alternatively, it is possible to use the semiconductor transistors such as general transistors.

(54) In such a configuration, the operation example (the second embodiment) will be described to the flowchart of FIG. 15.

(55) When the operation is started (Step S20), the MCU 100 outputs the switching signal SW1, and the FET 131 of the dark current suppressing switch 130 is switched-ON (Step S21). Next, the detecting-section-failure diagnostic function in the MCU 100 works (Step S22), and diagnoses whether the FET-short detecting section 110 is failed or not (Step S23). When the failure of the FET-short is diagnosed by the detecting-section-failure diagnostic function, the MCU 100 outputs the ALRAM1 or the ALARM2, the alarm input circuit 104 outputs the gate-OFF command GF (Step S24), and the inverter 37 is stopped (Step S25) by inputting the gate-OFF command GF into the gate driving section 130. The switching signal SW1 is outputted and the FET 131 of the dark current suppressing switch 130 is switched-OFF (Step S26). Thereby, since the dark current, which flows from the power supply VR of the inverter 37 to the control system while the operation of the MCU is stopped, can be suppressed, a wasted battery consumption is suppressed.

(56) In a case that the failure of the FET-short detecting section 110 is not detected at the above Step S23, the FET-short detecting section 110 diagnoses the short failure of the FETs of the inverter (Step S30). The FET-short detecting section 110 diagnoses the upper-stage FETs and the lower-stage FETs of the inverter 37 by comparing the status of the Table 1, and at first judges whether the upper-stage FETs are failed or not (Step S31). In a case that the upper-stage FETs are failed, the lower-stage FETs are turned-OFF by the error notifications EN, and further the upper-stage FETs perform the OFF-operation (Step S32). The FET 131 of the dark current suppressing switch 130 is switched-OFF with the switching signal SW1 (Step S33). Thereby, the dark current, which flows from the power supply VR of the inverter 37 to the control system while the operation of the MCU is stopped, can be suppressed.

(57) Next, it is judged whether the lower-stage FETs are failed or not (Step S34). In a case that the lower-stage FETs are failed, the upper-stage FETs are turned-OFF by the error notifications EN, and further the lower-stage FETs perform the OFF-operation (Step S35). The FET 131 of the dark current suppressing switch 130 is switched-OFF with the switching signal SW1 (Step S36). Thereby, the dark current, which flows from the power supply VR of the inverter 37 to the control system while the operation of the MCU is stopped, can be suppressed.

(58) In a case that neither the upper-stage FETs nor the lower-stage FETs are failed, the above operations are repeated. The order of detecting the short failure of the upper-stage FETs and the lower-stage FETs may be changeable.

(59) Further, in the above-described first and second embodiments, the upper-stage FETs and the lower-stage FETs are latched OFF when detecting the FET short. It is not limited to the above example, and the operation, which the upper-stage FETs and the lower-stage FETs are turned-OFF only when the FET short is detected, may be applicable. Only the upper-stage FETs and the lower-stage FETs whose phase is the failure may be turned-OFF or the all inverter FETs may be turned-OFF.

(60) In the above-described embodiments, the setting signals vthh_Sh and vthl_Sh are set to 1 [V]. It is not limited to the above example, and in order to avoid the erroneous detection, the value that is sufficiently larger than the ON-resistance of the upper-stage FETs .sub.RONthe current .sub.ION may be used. The determining time of the short detection is set to 10 [s]. It is not limited to the above example, and the sufficiently long time, which the time delay of the gate driving section and the switching time of the inverter FETs are considered, may be used. Further, the above-described logic H and L may be switched.

(61) In the above-described first and second embodiments, the dark current suppressing semiconductor switch is provided between the MCU and the power supply of the inverter (the voltage VR), that is, between the FET-short detecting section and the power supply of the inverter (the voltage VR). It is not limited to the above example, and the semiconductor switches may be connected between the power supply of the inverter (the voltage VR) and the control section, and be provided on the all paths which generate the dark current. In the above embodiments, although the MCU comprises the function which diagnoses whether the failure of the FET-short detecting section is occurred or not, the above function may be provided at the external of the MCU.

(62) Furthermore, in the above-described embodiments, although the electronic control unit being applied to the electric power steering apparatus is described as an example, the electronic control unit can be applied to other apparatus which uses the inverter.

EXPLANATION OF REFERENCE NUMERALS

(63) 1 handle (steering wheel)

(64) 2 column shaft (steering shaft, handle shaft)

(65) 10 torque sensor

(66) 12 vehicle speed sensor

(67) 20 motor

(68) 23 motor release switch

(69) 30 control unit (ECU)

(70) 31 current command value calculating section

(71) 35 PI-control section

(72) 36 PWM-control section

(73) 37 inverter

(74) 100 micro controller unit (MCU)

(75) 101 duty calculating section

(76) 110 FET-short detecting section

(77) 111 error logic circuit

(78) 112 SPI communication circuit

(79) 113, 114 threshold setting section

(80) 117 comparator

(81) 120 resistor voltage-dividing circuit for diagnosis

(82) 130 dark current suppressing switch

(83) 140 resistor voltage-dividing circuit for power supply

(84) 150 gate driving section

(85) 151 driving logic section