Abstract
A rectifier device is described herein. In accordance with one embodiment, the rectifier device includes a semiconductor body doped with dopants of a first doping type and one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type. Thereby, the one or more well regions and the surrounding semiconductor body form a pn-junction. The rectifier device further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode, which is parallel to the load current path. An alternating input voltage is applied between the anode terminal and the cathode terminal during operation of the rectifier device. The rectifier device includes a control circuit that is configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased, wherein the first MOS transistor and the diode are integrated in the semiconductor body and the control circuit is at least partly arranged in the one or more well regions. Further, the rectifier device includes a switching circuit that is configured to electrically connect a first well region of the one or more well regions with the anode terminal, as long as the alternating input voltage is above a threshold value, and, to pull the voltage of first well region towards the alternating input voltage, as long as the alternating input voltage is at or below the threshold value.
Claims
1. A rectifier device comprising: a semiconductor body doped with dopants of a first doping type; one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type, the one or more well regions and the surrounding semiconductor body forming a pn-junction; an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode connected parallel to the load current path, wherein an alternating input voltage is operably applied between the anode terminal and the cathode terminal; a control circuit that is configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased, the first MOS transistor and the diode being integrated in the semiconductor body and the control circuit being at least partly arranged in the one or more well regions; and a switching circuit that is configured to electrically connect a first well region of the one or more well regions with the anode terminal, as long as the alternating input voltage is above a predetermined threshold value, and, to pull the voltage of first well region towards the alternating input voltage, as long as the alternating input voltage is at or below the predetermined threshold value.
2. The rectifier device of claim 1, wherein to electrically connect the first well region with the anode terminal the switching circuit comprises: a resistor coupled between the first well region and the anode terminal.
3. The rectifier device of claim 1, wherein to electrically connect the first well region with the anode terminal the switching circuit comprises: a first transistor coupled between the first well region and the anode terminal.
4. The rectifier device of claim 3, wherein the first transistor is configured to selectively connect the first well region and the anode terminal, wherein the first transistor has a gate connected to a circuit node, which is coupled to the cathode terminal, the voltage of the circuit node alternating in accordance with the alternating input voltage.
5. The rectifier device of claim 4, wherein the switching circuit further comprises: a second transistor coupled between the cathode terminal and the circuit node, a gate of the second transistor being coupled to a supply node to receive an internal supply voltage.
6. The rectifier device of claim 5, wherein the switching circuit further comprises: a third transistor coupled between the cathode terminal and the first well region; a circuit configured to provide a gate voltage to the third transistor, so that the third transistor operates in its linear region.
7. The rectifier device of claim 6, wherein the circuit configured to provide the gate voltage to the third transistor comprises: a fourth transistor coupled to the anode terminal and configured to receive a drain current from a current source circuit, a gate electrode of the fourth transistor being connected to a gate electrode of the third transistor and connected to a drain of the fourth transistor.
8. The rectifier device of claim 1, wherein the switching circuit further comprises: a second transistor and a fifth transistor that form a cascode circuit coupled between the well region and the cathode terminal; a gate electrode of the second transistor being connected to a circuit node operably receiving a substantially constant gate voltage.
9. The rectifier device of claim 8, wherein the switching circuit further comprises: a first transistor configured to connect and disconnect the first well region and the anode terminal, wherein the transistor has a gate connected to a common circuit node of the second transistor and a fifth transistor.
10. The rectifier device of claim 9, wherein the switching circuit further comprises: a fourth transistor coupled to the anode terminal and configured to receive a drain current from a current source circuit, a gate electrode of the fourth transistor being connected to gate electrodes of the third transistor and the fifth transistor and connected to a drain of the fourth transistor.
11. A semiconductor device comprising: a semiconductor body doped with dopants of a first doping type; one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type; an alternating substrate voltage being operably applied to the semiconductor body; a switching circuit that includes: a first transistor coupled between the first well region and the anode terminal, a third transistor coupled between the first well region and the cathode terminal, a second transistor coupled between the cathode terminal and a first circuit node, a fifth transistor coupled between the first circuit node and the first well region, and a series circuit with a fourth transistor and a current source circuit coupled between an internal supply node and the anode terminal, wherein the third transistor, the fourth transistor, and the fifth transistor have gate electrodes coupled to a drain of the fourth transistor, wherein the first transistor has a gate electrode coupled to the first circuit node and wherein the second transistor has a gate electrode coupled to the internal supply node.
12. The circuit of claim 11, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-channel MOS transistors.
13. The circuit of claim 11, wherein the first transistor is a depletion-type MOS transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The embodiment described herein can be better understood with reference to the following description and drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the embodiments. Furthermore, in the figures, like reference numerals designate corresponding parts. In the drawings:
(2) FIG. 1 illustrates, as an illustrative example, a three-phase full-wave rectifier circuit composed of six diodes connected to a three-phase alternator.
(3) FIG. 2 illustrates a power MOSFET which can be used to replace a diode in a rectifier circuit, wherein, in the embodiments described herein, the power MOSFET is reverse conducting when switched on.
(4) FIG. 3 is a cross-sectional view of a semiconductor body illustrating exemplary implementation of the power MOSFET of FIG. 2.
(5) FIG. 4 is a circuit diagram illustrating the power MOSFET of FIG. 2 and a control circuit that is configured to actively switch the MOSFET on when the body diode becomes forward biased.
(6) FIG. 5 is a timing diagram illustrating the voltage across the body diode of the MOSFET of FIG. 4, when the MOSFET is connected to a load and not actively switched on while being supplied with an alternating voltage.
(7) FIG. 6 is a circuit diagram illustrating an exemplary supply circuit which may be included in the control circuit to generate an internal supply voltage.
(8) FIGS. 7A and 7B are a timing diagrams illustrating one example of how the MOSFET of FIG. 4 may be switched on and off when supplied with an alternating voltage.
(9) FIG. 8 is a cross-sectional view of a semiconductor body similar to FIG. 3; parasitic components which may give rise to latch-up effects are illustrated in this Figure.
(10) FIG. 9 is one exemplary circuit which may used to prevent activation of parasitic components.
(11) FIG. 10 is another exemplary circuit, which is a simplified modification of the example of FIG. 9.
DETAILED DESCRIPTION
(12) As mentioned above, several types of rectifiers exist. FIG. 1 illustrates one exemplary implementation of a three-phase full-wave rectifier, which is built using six diodes D.sub.1, D.sub.2, D.sub.3, D.sub.4, D.sub.5, D.sub.6 connected in a bridge configuration (a so-called three-phase rectifier bridge). FIG. 1 also illustrates a three-phase AC voltage source G which may represent, for example, an electric grid, the secondary sides of a three-phase transformer, an AC generator such as a three-phase alternator used in an automobile, or any other common AC voltage source. The voltage source G provides three-phases, which are connected to the rectifier bridge. The AC voltages between the phases are denoted as V.sub.UV, V.sub.UW, and V.sub.VW. A capacitor C.sub.1 may be connected to the output of the rectifier bridge to reduce the ripple of the DC output voltage V.sub.DC. As mentioned, an automotive battery may be coupled to the rectifier bridge so that the battery can be charged by the generator G.
(13) Silicon diodes usually have a forward voltage of approximately 0.6 to 0.7 volts, and therefore may cause significant power dissipation. To reduce the power dissipation, a silicon diode may be replaced by a rectifier device including a controllable semiconductor switch. In the example illustrated in FIG. 2, the rectifier device 10 includes a power MOS transistor M.sub.P (MOSFET), which has an intrinsic diode D.sub.R (body diode) coupled in parallel to the load current path (drain-source current path) of the power MOS transistor M.sub.P. The node and cathode terminals of the rectifier device 10 correspond to anode and cathode of the intrinsic diode and are labelled A and K, respectively. Although a MOSFET is used in the examples described herein, an IGBT with an integrated reverse diode may be used instead. Generally, the rectifier device 10 may have only two terminals and thus may be used as a simple replacement for a normal silicon diode.
(14) Unlike in known active rectifier circuits (also referred to as synchronous rectifiers), the power MOS transistor M.sub.P is operated in a reverse conducting mode. Basically, a standard rectifier diode (as used for example in the rectifier bridge of FIG. 1) is replaced by the body diode (see FIG. 2, diode D.sub.R) of a power MOS transistor, which can be bypassed by the MOS channel of the power MOS transistor, when the power MOS transistor is activated (i.e. switched on). That is, the power MOS transistor is switched on (which makes the MOS channel conductive), when the body diode is forward biased, thus bypassing the load current path through the body diode. When the diode D.sub.R is reverse biased, the MOSFET M.sub.P is always off during normal operation. In the example depicted in FIG. 2, the rectifier device 10 has only two terminals, a first terminal A (connected to the anode of the body diode D.sub.R) and a second terminal K (connected to the cathode of the body diode D.sub.R). As will be explained later, the control circuit used to switch the MOSFET M.sub.P on and off may be integrated in the same semiconductor die as the MOSFET M.sub.P, and the internal supply of the integrated control circuit may be internally generated from the AC voltage applied at the two terminals A and K. As only two terminals are used by the rectifier device 10, it can readily be used as a replacement for ordinary silicon rectifier diodes to reduce power losses.
(15) FIG. 3 illustrates one exemplary implementation of the power MOS transistor M.sub.P of FIG. 2 in a silicon substrate. In the present example, the MOSFET is implemented using a vertical transistor structure composed of a plurality of transistors cells. The term vertical is commonly used in the context of power transistors and refers to the direction of the load current path (MOS channel), which extends vertically with respect to a horizontal plane defined by the bottom plane of the semiconductor substrate. The term vertical can thus be used to discriminate vertical transistors from planar transistors, in which the load current path (MOS channel) extends parallel to the horizontal plane. In the present example, the vertical MOS transistor is implemented as a so-called trench transistor, which has its gate electrodes arranged in trenches formed in the silicon body. However, other types of vertical power transistors or other types of transistors may be used as well.
(16) Power MOS transistors are usually formed by a plurality of transistors cells coupled in parallel. In the example of FIG. 3, the semiconductor body 100 is essentially formed by a semiconductor substrate 101 (wafer), on which a (e.g. monocrystalline) semiconductor layer 101 is deposited using epitaxial growth. The semiconductor substrate 101 and the semiconductor layer 101 may be doped with dopants of a first doping type, e.g. n-type dopants, wherein the concentration of dopants may be much lower in the semiconductor layer 101 (therefore labelled n.sup.) as compared to the highly doped substrate 101 (labelled n.sup.+). Trenches 110 are formed in the semiconductor layer by an anisotropic etching process. The trenches 110 extendfrom the top surface of the semiconductor body 100vertically into the semiconductor body 100 and are filled with conductive material (e.g. highly doped polycrystalline silicon) to form gate electrodes 112 within the trenches 110. The gate electrodes 112 are isolated from the surrounding semiconductor body 100 by an oxide layer 111, which is disposed on the inner surfaces of the trenches 110 (e.g. by an oxidation process) before filling them with the mentioned conductive material.
(17) An upper portion of the semiconductor layer 101 is doped with dopants of a second doping type, e.g. p-type dopants, e.g. using a first doping process (e.g. diffusion process of dopants or ion implantation). The resulting p-doped region is usually referred to as the body region 103, whereas the remaining n-doped portion of the semiconductor layer 101 (directly adjoining the substrate 101) forms the so-called drift region 102 of the MOS transistor. As the trenches 110 extend down to the drift region 102, the body region 103 is segmented into a plurality of body regions associated with a respective plurality of transistor cells.
(18) A second doping process (e.g. diffusion process of dopants or ion implantation) is used to form source regions 105. Therefore, the MOS transistor M.sub.P is also referred to as DMOS (double-diffused metal-oxide-semiconductor) transistor. The source regions are doped with dopants of the same type as the substrate 101 (e.g. n-type dopants). The concentration of dopants may be comparably high (therefore labelled n.sup.+), but is not necessarily equal to the concentration of dopants in the substrate 101. The source regions 105 extend vertically into the semiconductor body starting from the top surface of the semiconductor body and adjoining the trenches 112. Body contact regions 104, which are doped with dopants of the same type as the body regions 103, may be formed between neighboring trenches 110 in order to allow to electrically contact the body regions 103 at the top surface of the semiconductor body 100. The source regions 105 and the body contract regions 104 are electrically contacted at the top surface of the semiconductor body 100 by the conductive layer 115 (e.g. metal layer) that forms the source electrode S of the power MOS transistor. Thereby the individual transistors cells are electrically connected in parallel. The gate electrodes 112 in the trenches 110 must be isolated from the conductive layer 115 and are also connected to each other, e.g. at the end of the trenches 110 (not visible in FIG. 3). The drain electrode D is formed by another conductive layer 116 at the bottom surface of the semiconductor body 100.
(19) The body diode D.sub.R (see also FIG. 3) of the MOSFET is also shown in the cross-sectional view of FIG. 3. It is formed by the p-n junctions at the transitions between the body regions 103 (in each transistor cell) and the drift region 102. The source electrode S (which is electrically connected to the source and body contact regions 105, 104) is therefore also the anode of the diode D.sub.R, and the drain electrode D is also the cathode of the diode D.sub.R. A transistor designed according to the example of FIG. 3 or similar transistor designs are as such known (sometimes referred to as DMOS transistor) and thus not further explained in detail.
(20) What should be mentioned at this point is that the MOS transistor M.sub.P is not the only component integrated in the substrate. All other circuitry needed to control the switching operation of the MOS transistor M.sub.P can also be integrated in the same semiconductor body 100. The embodiments described herein may be designed as two-terminal rectifier devices (terminals A and K), which have only two external pins and essentially behave like diodes. Unlike a normal silicon diode, the rectifier devices described herein may be designed to have a very low forward voltage as the low-resistive MOS channel bypasses the current path through the body diode D.sub.R while the body diode is forward biased. In the following, the potential at the first terminal A (anode, corresponds to the source electrode of the power MOS transistor M.sub.P) is denoted as reference voltage V.sub.REF, whereas the voltage at the second terminal K (cathode, corresponds to the drain electrode of the power MOS transistor M.sub.P) is denoted as substrate voltage V.sub.SUBST (voltage present in the substrate 101, see FIG. 3). The reference voltage V.sub.REF may be regarded as (floating) ground potential for the circuitry included in the rectifier device 10.
(21) FIG. 4 illustrates the rectifier device 10 of FIG. 2 in more detail. Accordingly, the rectifier device includes the MOSFET M.sub.P (DMOS transistor), which includes the intrinsic reverse diode D.sub.R (see FIG. 2) as well as a control circuit 11 connected to a gate terminal of the MOS transistor M.sub.P. As explained above, the MOS transistor M.sub.P and its intrinsic body diode D.sub.Rand also the control circuit 11are connected between the first and the second terminals A and K. The electric potential V.sub.REF at the first terminal (anode) can be defined as zero volts (0 V) and can thus be regarded as reference or ground potential (ground GND) for all circuitry integrated in the semiconductor body 100. With respect to the reference potential V.sub.REF, the substrate voltage V.sub.SUBST may oscillate from negative values of approximately 0.7 volts minimum (i.e. the negative forward voltage of the body diode D.sub.R) to a positive peak value V.sub.AC_MAX of an alternating input voltage applied between the two terminals A and K. In the example of FIG. 4, the rectifier device 10 is supplied by an AC source Q.sub.AC via a resistor R.sub.V. However, supplying the rectifier device 10 as illustrated in FIG. 4 should be regarded merely as a hypothetical example, which is used to explain the function of the rectifier device 10.
(22) In the present example, the control circuit 11 includes a logic circuit 14, which implements the control function for switching the power MOS transistor on and off, as explained further below with reference to FIGS. 7A and 7B, and a gate driver 13 that generates a gate signal V.sub.G based on the logic signal ON provided by the logic circuit 14. The internal supply voltage V.sub.S may be provided by a supply circuit as shown, for example, in FIG. 6. The supply voltage V.sub.H for the gate driver 13 may be buffered, for example, by a capacitor (not shown). The logic circuit 14 is basically configured to detect that the substrate voltage V.sub.SUBST has become negative and trigger the activation the MOS transistor M.sub.P by setting the logic signal ON e.g. to a high level. The logic circuit 14 is basically configured to detect that the substrate voltage V.sub.SUBST is about to become again positive and trigger the deactivation of the MOS transistor M.sub.P. As mentioned, a negative substrate voltage V.sub.SUBST entails a forward biasing of the body diode D.sub.R.
(23) FIG. 5 is a timing diagram illustrating the waveform of the substrate voltage V.sub.SUBST with respect to the reference potential V.sub.REF for the hypothetic case, in which the MOSFET M.sub.P included in the rectifier device 10 is never switched on and, therefore, the load current i.sub.L can only pass the rectifier device 10 via the body diode D.sub.R. In this example it is further assumed that an alternating input voltage V.sub.AC is applied to a series circuit of the rectifier device 10 and a load (see FIG. 4, resistor R.sub.V). Without loss of generality, the reference potential V.sub.REF may be defined as 0 V. While the body diode D.sub.R is reverse biased (V.sub.SUBST>0 V), the substrate voltage V.sub.SUBST follows the alternating input voltage V.sub.AC and the load current is approximately zero (diode D.sub.R is blocking). While the body diode D.sub.R is reverse biased (V.sub.SUBST<0V) during normal operation, the substrate voltage V.sub.SUBST follows the alternating input voltage V.sub.AC as long as the alternating input voltage V.sub.AC is higher than the negative forward voltage V.sub.D of the body diode D.sub.R (e.g. V.sub.AC>0.6V). However, when the instantaneous level of the alternating input voltage V.sub.AC becomes lower (i.e. more negative) than the negative forward voltage V.sub.D of the body diode D.sub.R (e.g., V.sub.AC<0.6V), the substrate voltage V.sub.SUBST will be approximately limited to the negative forward voltage V.sub.D of the body diode D.sub.R (e.g., V.sub.SUBST0.6V). In this situation, the diode D.sub.R is forward biased and thus conductive, and the difference between the (negative) substrate voltage and the alternating input voltage V.sub.AC is the voltage drop across the load (e.g., resistor R.sub.V in the example of FIG. 4). The load current i.sub.L actually passing through the rectifier device 10, while (V.sub.AC<V.sub.D) depends on the load.
(24) As mentioned above, a voltage drop across the rectifier device 10 of approximately 600 to 700 mV (at room temperature) may cause significant power dissipation. To reduce the substrate voltage V.sub.SUBST while the body diode D.sub.R is forward biased, the MOS transistor M.sub.P can be switched on to make the MOS channel of the MOS transistor M.sub.P conductive. In this case, the body diode D.sub.R is bypassed via the low-ohmic current path provided by the MOS channel. However, in the time period in which the body diode D.sub.R is reverse biased (i.e. blocking), the MOS transistor should remain switched off. The logic circuit 14 that controls the switching operation of the MOS transistor M.sub.P is included in the control circuit 11 (see FIG. 4). Accordingly, the rectifier device 10 essentially behaves like a diode with a very low forward voltage of approximately 100-200 millivolts.
(25) As shown in FIG. 4, the control circuit 11 is coupled between the two terminals A and K, at which the alternating input voltage is applied (see FIG. 5). However, some circuit components in the control circuit 11 need a DC supply voltage in order to operate properly. Therefore, the control circuit 11 may include at least one supply circuit, which provides an internal supply voltage V.sub.S for supplying various other circuit components of the control circuit 11. Before explaining exemplary implementations of the control circuit 11 and its function in more detail, an exemplary implementation of the internal supply circuit is explained with reference to FIG. 6.
(26) The exemplary supply circuit 12 illustrated in FIG. 6 is coupled between the first terminal A (reference potential V.sub.REF) and the second terminal K (substrate voltage V.sub.SUBST), which are connected to the source and drain of the power MOS transistor M.sub.P, respectively. In this example, a series circuit composed of a diode D.sub.S and a Zener diode D.sub.Z is electrically connected between the substrate (being at substrate voltage V.sub.SUBST) and the source electrode of the MOS transistor M.sub.P (being at reference potential V.sub.REF). A buffer capacitor C.sub.S is connected parallel to the Zener diode D.sub.Z as shown in FIG. 6. The capacitor C.sub.S is charged via the diode D.sub.S when the level of the substrate voltage V.sub.SUBST is higher than the sum of the voltage V.sub.IN across the capacitor C.sub.S and the forward voltage of the diode D.sub.S. The Zener diode D.sub.Z limits the capacitor voltage V.sub.IN across the capacitor C.sub.S to a maximum value, which is determined by the Zener voltage of the Zener diode D.sub.Z. Further, the diode D.sub.S prevents the discharging of the capacitor C.sub.S via the substrate when the substrate voltage V.sub.SUBST falls to values lower than the capacitor voltage V.sub.IN. The capacitor voltage V.sub.IN may be supplied as input voltage to a voltage regulator device REG, and the input voltage V.sub.IN is buffered by the capacitor C.sub.S while the substrate voltage V.sub.SUBST is low. The regulated output voltage of the voltage regulator REG is denoted as V.sub.S. The regulated output voltage V.sub.S may be regarded as internal supply voltage that is used to supply any circuitry (e.g. logic circuits such as logic circuit 14, see FIG. 4) integrated in the rectifier device 10.
(27) It is noted that the circuit of FIG. 6 should be regarded as an illustrative example and may also be implemented in various alternative ways. For example, the Zener diode D.sub.Z may be replaced by a any voltage limiting circuit configured to limit the capacitor voltage to a desired maximum. Further, diode D.sub.S may be replaced by a transistor that is able to limit the current passing through it. Dependent on the application, the Zener diode D.sub.Z may be omitted. The capacitor C.sub.S may be replaced by any circuit (e.g. series or parallel circuit of several capacitors) that provides a sufficient capacitance to be able to buffer the input voltage V.sub.IN while the substrate voltage V.sub.SUBST is too low to charge the capacitor C.sub.S. In some implementations, the voltage regulator REG may be substituted by other circuitry that provides a similar function. If the capacitance of the capacitor C.sub.S is high enough to ensure an acceptably low ripple, the regulator REG may be also omitted.
(28) FIGS. 7A and 7B include timing diagrams illustrating the function of one exemplary embodiment of the rectifier device 10 implemented according to the basic example of FIG. 4. In particular, the function of the control logic used to switch on and switch off of the MOS transistor M.sub.P is illustrated by the timing diagrams of FIGS. 7A and 7B. The diagram of FIG. 7A is essentially the same as the diagram of FIG. 5 except that, in the current example, power MOS transistor M.sub.P is switched on when the intrinsic body diode D.sub.R is forward biased in order to bypass the body diode D.sub.R via the activated MOS channel. The bypassing of the body diode D.sub.R results in a voltage drop across the rectifier device 10 which is significantly lower than the forward voltage of a normal diode.
(29) The first diagram of FIG. 7B shows a magnified segment of the waveform shown in FIG. 7A. FIG. 7A shows a full cycle of the substrate voltage V.sub.SUBST, whereas the first diagram of FIG. 7B only shows approximately the second half of the cycle, during which the substrate voltage V.sub.SUBST is negative. The second diagram of FIG. 7B illustrates a simplified waveform of the logic signal ON (see FIG. 4) which triggers the activation/deactivation of the MOS transistor M.sub.P to switch it on and off. As can be seen in FIGS. 7A and 7B, the MOS transistor M.sub.P is switched on when the control circuit 11 detects (by means of logic circuit 14, see FIG. 4) that the substrate voltage V.sub.SUBST is negative (i.e. the diode D.sub.R is forward biased). This detection can be made based on various criteria. In the present example, negative threshold voltages V.sub.ON and V.sub.OFF are used to determine the time instants for switching the MOS transistor M.sub.P on and off (i.e. begin and end of the on-time period T.sub.ON of MOS transistor M.sub.P). Accordingly, the MOS transistor M.sub.P is switched on when the substrates voltage V.sub.SUBST reaches or falls below the first threshold V.sub.ON, and the MOS transistor M.sub.P is switched off when the substrates voltage V.sub.SUBST again reaches or exceeds the second threshold V.sub.OFF.
(30) In the present example, the condition V.sub.SUBST=V.sub.ON is fulfilled at time t.sub.1 and the control signal ON (see second diagram of FIG. 7B), as well as the corresponding gate voltage V.sub.G, are set to a high level to switch the MOS transistor M.sub.P on. When the substrate voltage V.sub.SUBST reaches or exceeds the second threshold V.sub.OFF at the end of a cycle, the MOS transistor M.sub.P is switched off again. In the present example, the condition V.sub.SUBST=V.sub.OFF is fulfilled at time t.sub.2 and the control signal ON (see bottom diagram of FIG. 7B), as well as the corresponding gate voltage V.sub.G, are set to a low level to switch the MOS transistor M.sub.P off. When the MOS transistor M.sub.P is switched off at time t.sub.2, the substrate voltage V.sub.SUBST may abruptly fall to V.sub.D before it again rises to positive values at the beginning of the next cycle. It is understood that the waveforms shown in FIGS. 7A and 7B are merely an illustrative example and are not to scale.
(31) While the MOS transistor M.sub.P is switched on (i.e. during the on-time period T.sub.ON), the substrate voltage V.sub.SUBST equals R.sub.ON.Math.i.sub.L, wherein R.sub.ON is the on-resistance of the activated MOS channel. In the present example, only two threshold values are used to switch the MOS transistor M.sub.P on and off. However, two or more threshold values may be used to switch-on and/or switchoff. In this case the power MOSFET may be switched on or off (or both) gradually (stepwise) by subsequently switching on/off two or more groups of transistor cells of the power MOSFET.
(32) Referring back to FIG. 7A, both the first threshold V.sub.ON and the second threshold V.sub.OFF are negative (note that the reference voltage V.sub.REF is defined as zero), but higher than the negative forward voltage V.sub.D of the body diode D.sub.R of the MOS transistor M.sub.P. Further, the second threshold V.sub.OFF may be higher (less negative) than the first threshold V.sub.ON. That is, the condition V.sub.D<V.sub.ON<V.sub.OFF<0 V is fulfilled in the present example, e.g. V.sub.ON=250 mV and V.sub.OFF=50 mV, while V.sub.D700 mV. At this point it should be noted that the cycle time T.sub.CYCLE is given by the frequency of the AC input voltage V.sub.AC.
(33) As can be seen in FIG. 7B, the MOS transistor M.sub.P should only switch on once in each cycle (see FIG. 7A, period T.sub.CYCLE) of the substrate voltage V.sub.SUBST, specifically, when the condition V.sub.SUBST=V.sub.ON is met for the first time. When the condition is met again in the same cycle, a second switch-on of the MOS transistor M.sub.P should be prevented (e.g. at time instant t.sub.2, see first diagram of FIG. 7A). Similarly, the MOS transistor M.sub.P should be switched off when the condition V.sub.SUBST=V.sub.OFF is met at the end of a cycle. If this condition is met earlier during a cycle (e.g. shortly after time t.sub.1, if R.sub.ON.Math.i.sub.L(t.sub.1)>V.sub.OFF), an early switch-off of the MOS transistor should be prevented. In order to avoid an undesired early switch-off of the MOS transistor, the control circuit may include a timer that prevents a switch-off for a specific time span (e.g. during the first half of the on-time T.sub.ON). It is noted that the control logic (e.g. control logic 14, see FIG. 4) that exhibits the behaviors illustrated in FIGS. 7A and 7B may be implemented in numerous different ways. The actual implementation may depend on the application as well as on the semiconductor technology used to manufacture the rectifier device 10. It is understood that a skilled person is able to implement the functionality discussed above with reference to FIGS. 7A and 7B.
(34) FIG. 8 is a simplified cross-sectional view of a rectifier device as described herein with reference to FIGS. 1 to 7. An example of the portion of the rectifier device, which includes the power MOS transistor M.sub.P, has been described with reference to in FIG. 3. As mentioned, other circuitry is integrated in the same semiconductor substrate such as the control circuit 11 (see FIG. 4) which may include the logic circuit 14 and the supply circuit 12. Whenas in the example of FIG. 3the power MOS transistor is an n-channel transistor, the semiconductor substrate 101 will be doped with dopants of the first type (n-type). Therefore, analogously to the example of FIG. 3, the semiconductor body 100 shown in FIG. 8 is essentially formed by the semiconductor substrate 101 (wafer), on which the (e.g. monocrystalline) semiconductor layer 101 is deposited using epitaxial growth. The semiconductor layer 101 is doped with dopants of the same type as the type of the dopants used for doping the substrate 101, wherein the concentration of dopants may be much lower in the semiconductor layer 101 (therefore labelled n.sup.) as compared to the highly doped substrate 101 (labelled n.sup.+).
(35) Well regions 200 and 300 may be formed in the semiconductor layer 101, e.g., using ion implantation, diffusion of dopants or other known doping processes. During fabrication, the well regions 200 and 300 may be formed in the same or in a different step as the body regions 103 shown in FIG. 3, and the type of dopants used to dope the well regions 200 and 300 is complementary to the type of dopants used to dope the semiconductor layer 101. That is, well regions 200 and 300 are p-doped (thus referred to as p-wells) in case the substrate 101 and the semiconductor layer 101 are n-doped (thus referred to as n-substrate). Similar to the body regions 103, the p-wells 200 and 300 extend, from the top surface of the semiconductor body 100, vertically into the semiconductor layer 101 and are laterally confined by the material of the surrounding semiconductor layer 101. Various circuit components may be integrated in the p-wells 200 and 300 and further p-wells. In the present example of FIG. 8, well region 200 includes an n-channel MOSFET and well region 300 includes a p-channel MOSFET. These two MOSFETs may be combined to form, e.g., a CMOS inverter or other circuitry. It is, however, emphasized that these two MOSFETs have to be merely regarded as representatives for arbitrary circuits and circuit elements (e.g. control circuit 11, see FIG. 4) integrated in the well regions 200 and 300 and other well regions in the semiconductor body 100. The individual integrated circuit components may be connected to form a specific circuit by conductive lines formed in one or more wiring layers on top of the semiconductor body 100. The wiring of integrated circuit components is as such known and thus not further explained herein.
(36) To from an n-channel MOSFET in p-well 200, a drain region 203 and a source region 204 are formed within the p-well 200 and embedded therein. Drain region 203 and source region 204 are both doped with n-type dopants. A gate electrode 206 is arranged on the top surface of the semiconductor body 100, but electrically isolated therefrom. The gate electrode 206 extends between the drain region 203 and the source region 304. The p-well 200 can be regarded as the transistor body region andwhen the gate electrode 206 is sufficiently charged during operationan (n-type) MOS channel is generated in that portion of the p-well 200, which separates drain region 203 and source region 204 from each other. A well contact region 202 may also be formed within the p-well 200 and allows to contact the p-well 200. Usually, the well contact region 202 is p-doped but with a higher concentration of dopants than the p-well 200.
(37) To from a p-channel MOSFET in p-well 300 an additional n-doped well 301 (n-well) is embedded in p-well 300. The n-well 301 may also be formed using ion implantation, diffusion of dopants or other known doping processes. It extends from the top surface of the semiconductor body vertically into the p-well 300 and thus is embedded within the p-doped semiconductor material of the p-well 300. Analogously to the n-channel MOSFET in p-well 200, a drain region 303 and a source region 304 are formed within the n-well 301. A gate electrode 306 is arranged on the top surface of the semiconductor body 100, but electrically isolated therefrom. The gate electrode 306 extends between the drain region 303 and the source region 304. The n-well 301 can be regarded as transistor body region, andwhen the gate electrode 306 is sufficiently charged during operationan (p-type) MOS channel is generated in that portion of the n-well 301, which separates drain region 303 and source region 304 from each other. A body contact region 305 is formed in the n-well 301 to allow to electrically contact the n-well 301. The body contact region is usually n-doped like the n-well but with a higher concentration of dopants that the n-well 301. Further, a well contact region 302 may also be formed within the p-well 300 and allows to contact the p-well 300. Usually, the well contact region 302 is p-doped but with a higher concentration of dopants than the p-well 300 (like well contact region 202).
(38) As shown in FIG. 8, the voltage (potential) of the p-wells 200 and 300 is denoted as V.sub.PISO. Drain, source, and gate voltage of the n-channel MOSFET in p-well 200 are denoted as V.sub.D1, V.sub.S1, and V.sub.G1, respectively. The body voltage of the n-channel MOSFET equals V.sub.PISO. Drain, source, gate, and body voltage of the p-channel MOSFET in n-well 301 are denoted as V.sub.D2, V.sub.S2, V.sub.G2, and V.sub.B2, respectively. One can see from FIG. 17, that a pn-junction is formed at the interface between the n-doped semiconductor layer 101 and the p-wells 200, 300. It is desired thatduring normal operationthis pn-junction is reversed biased and thus forms a so-called pn-junction isolation. In applications with DC supply, the n-substrate 101 is usually electrically connected with the highest available DC supply voltage (i.e. substrate voltage V.sub.SUBST corresponds to the highest available supply voltage) and, as a result, the mentioned pn-junction isolation is always reverse biased and thus in a blocking state. However, the examples described herein relate to rectifier devices, which are operated with an alternating supply (input) voltage that is applied between drain and source of the power MOS transistor M.sub.P integrated in the rectifier device (see, e.g., FIGS. 3 and 4). As the drain of the power MOS transistor M.sub.P is electrically connected to the n-substrate (see FIG. 3, drain electrode 116, substrate 101), the substrate voltage V.sub.SUBST is not a DC voltage but an alternating voltage as shown, for example, in FIG. 7A.
(39) As can be seen in FIG. 7A, the substrate voltage V.sub.SUBST cyclically assumes negative values (if the reference potential V.sub.REF is defined as 0V), and thus the above-mentioned pn-junction isolation may be come forward biased which may cause a latch-up of the rectifier device. A latch-up may be caused by an undesired activation of parasitic transistors shown in FIG. 8 and explained in the following. The pn-junction between p-well 200 and the subjacent n-doped semiconductor layer 101 may form the base-emitter diode of a parasitic npn-type bipolar junction transistor T.sub.P1. The pn-junctions between the p-well 200 and the n-doped drain and source regions 203, 204 form multiple collector-base diodes of the parasitic transistor T.sub.P1. One can see from FIG. 8 that parasitic transistor T.sub.P1 may be switched on, when the substrate voltage V.sub.SUBST becomes negative and thus the base-emitter diode of transistor TP1 becomes forward biased. An activated (switched on) parasitic transistor T.sub.P1 may de-facto short-circuit the substrate 101 with drain and source regions 203, 204, which may irreversibly damage the rectifier device.
(40) Similar to parasitic transistor T.sub.P1, the pn-junction between p-well 300 and the subjacent n-doped semiconductor layer 101 may form the base-emitter diode of a further parasitic npn-type bipolar junction transistor T.sub.P2a. The pn-junction between the p-well 300 and the n-well 301 form the collector-base diode of the parasitic transistor T.sub.P2a. Simultaneously, the pn-junction between the p-well 300 and the n-well 301 form the collector-base diode of a parasitic pnp-type bipolar junction transistor T.sub.P2b, whose multiple emitters are formed by the drain and source regions 303 and 304 embedded in n-well 301. The two parasitic transistors T.sub.P2a and T.sub.P2b are connected in a way that they form a thyristor (pnpn-structure) with the p-well 300 forming the thyristor's gate. This thyristor may be switched on, when the substrate voltage V.sub.SUBST becomes negative and thus the base-emitter diode of transistor T.sub.P2a becomes forward biased (which in turn leads to an activation of transistor T.sub.P2b). The activated (switched on) thyristor may de-facto short-circuit the substrate 101 with drain and source regions 303, 204, which also may irreversibly damage the rectifier device.
(41) To prevent short circuits, latch-up and similar effects in the rectifier device due to the activation of parasitic bipolar junction transistors or thyristors the pn-junction isolations between the substrate 101 and the p-wells 200 and 300 (and further p-wells) have to be maintained in an isolating state during any operation state of the rectifier device, even during operation states, in which the substrate voltage V.sub.SUBST is negative. In other words, the pn-junctions between the n-doped semiconductor layer 101 and the p-wells 200 and 300 have to be (and maintained) reverse biased irrespective of the polarity of the substrate voltage V.sub.SUBST.
(42) One solution of the above-described problem with regard to latch-up and similar effects is to employ a circuit including one or more switches configured to electrically connect the p-wells (e.g. p-wells 200 and 300) to the substrate 101 during operating states, in which the substrate voltage is negative with respect to ground potential, which is the potential of the anode terminal of the rectifier device 10 (i.e. the source electrode of the MOS transistor M.sub.P, see FIG. 4). In this regard to electrically connect means to connect by a comparably low-resistance current path, which may be provided, e.g. by an active MOS channel of a MOS transistor.
(43) FIG. 9 illustrates a circuit which allows to switch one or more p-wells (voltage V.sub.PISO) between ground GND (anode A of the rectifier device) and substrate (see FIG. 8, regions 101, 102, cathode K of rectifier device) with low quiescent current and low complexity of the circuit. According to FIG. 9 the circuit includes basically two current mirrors CM1 and CM2 as well as one semiconductor switch N.sub.5 which is configured to connect one or more of the p-wells to ground GND (and thus to the anode A). The first current mirror CM1 includes an input stage with a first transistor N.sub.1 and an output stage with a second transistor N.sub.2. The first transistor N.sub.1 of the input stage may be implemented as an n-channel MOSFET and is connected as a diode (gate electrically connected to drain). The diode-connected transistor N.sub.1 is connected in series with a current source circuit Q.sub.1, wherein the series circuit is coupled between ground GND and a supply node, at which an internal supply voltage V.sub.INT is provided. The internal supply voltage V.sub.INT may directly or indirectly depend on the output voltage V.sub.S generated, for example, by the supply circuit 12 shown in FIG. 6 or any other suitable supply circuit. That is, the internal supply voltage V.sub.INT may be equal to the voltage V.sub.S provided by the supply circuit 12 or derived therefrom. For example, the internal supply voltage V.sub.INT may be a few volts, e.g. approximately 2-5V. In the present embodiment, the current source circuit Q.sub.1 is be a constant current source; in other embodiments the current source circuit Q.sub.1 is a simple resistor or any other circuitry suitable to limit the drain current i.sub.1 of transistor N.sub.1
(44) The transistor N.sub.2 of the output stage of current mirror CM1 has a gate electrode electrically connected to the gate electrode of transistor N.sub.1. The source of transistor N.sub.2 is electrically connected to the p-well. The drain of transistor N.sub.2 is connected to substrate (and thus to the cathode K of the rectifier device) via a pull-up circuit that, in the present example, is composed of a further transistor N.sub.4, whichtogether with transistor N.sub.2forms a kind of cascode circuit. That is, the drain-source current paths of transistors N.sub.2 and N.sub.4 are connected in series and the gate electrode of transistor N.sub.4 is connected to the supply circuit node that provides the internal supply voltage V.sub.INT. Accordingly, when the substrate voltage is positive and at a sufficiently high level (to drive the mirror current i.sub.2), then the mirror current i.sub.2 (drain current of transistor N.sub.2) passing through transistors N.sub.2 and N.sub.4 corresponds to the drain current i.sub.1 of transistor N.sub.1, and the voltage V.sub.X at circuit node X between transistors N.sub.2 and N.sub.4 equals V.sub.INTV.sub.GS4, wherein V.sub.GS4 is the gate-source voltage of transistor N.sub.4. In this situation the voltage V.sub.X is high enough to activate the further transistor N.sub.5, whose drain-source current path connects the p-well with ground and whose gate is provided with the voltage V.sub.X. Summarizing the above, for sufficiently positive substrate voltages V.sub.SUBST, the voltage V.sub.X at circuit node X is high enough to switch on the transistor N.sub.5 and thus to electrically connect the p-well to ground (V.sub.PISO=0V).
(45) The second current mirror is formed by transistor N.sub.1, which is the input stage for both current mirrors, CM1 and CM2, and transistor N.sub.3, whose drain-source current path is connected between substrate (cathode terminal K) and p-well and whose gate is connected to the gates of transistors N.sub.1 and N.sub.2 as shown in FIG. 9. For sufficiently positive substrate voltages V.sub.SUBST, the transistor N.sub.3 will sink a drain current i.sub.3 from substrate. The current mirror CM2 may, however, be designed such that the current i.sub.3 is comparably small and does not contribute significantly to the overall power losses.
(46) When the substrate voltage V.sub.SUBST decreases and becomes negative (in each cycle, see FIG. 7A), then the output stages (transistors N.sub.2 and N.sub.3) cannot anymore mirror the current i.sub.1. That is, they cannot sink the drain currents i.sub.2 and i.sub.3 in a way that they are proportional to drain current i.sub.1. When the substrate voltage V.sub.SUBST becomes negative, then transistor N.sub.4 is operated in a reverse direction (drain becomes source and source becomes drain) in its linear region (triode or ohmic mode). In this situation, the resistance of the MOS channel of transistor N.sub.4 is low enough to pull the voltage V.sub.X at circuit node X towards negative values (i.e. transistor N.sub.4 acts as a pull-down resistor) to switch the transistor N.sub.5 off thus disconnecting the p-well from ground GND.
(47) When the substrate voltage V.sub.SUBST becomes negative, then transistor N.sub.3 is also operated in a reverse direction (drain becomes source and source becomes drain) in its linear region (triode or ohmic mode). In this situation, the resistance of the MOS channel of transistor N.sub.3 is low enough to pull the voltage V.sub.PISO in the p-well towards the negative substrate voltage V.sub.SUBST. When the substrate voltage V.sub.SUBST again rises in the next cycle, the transistors N.sub.1, N.sub.2, and N.sub.3 will again operate as current mirrors CM1, CM2 and transistor N5 will be re-activated to connect the p-well to ground GND. The input stage transistor N.sub.1 of current mirror CM1 in combination with the current source circuit Q.sub.1 can be regarded as a (biasing) circuit configured to provide a gate voltage to transistor N.sub.3, so that the third transistor N.sub.3 operates in its linear region. When the substrate voltage V.sub.SUBST is negative, the resistance of the drain-source path of transistor N.sub.3 will be lower as compared with a situation, in which the substrate voltage V.sub.SUBST is at a high (positive) value. As such, transistor N.sub.3 acts as a pull-down resistor when the substrate voltage V.sub.SUBST is negative.
(48) All transistors N.sub.1 to N.sub.5 may be implemented as n-channel MOSFETs of the enhancement-type. However, in the present example, the transistor N.sub.5 is of the depletion type (threshold voltage for activating the transistor is negative). FIG. 10 illustrates a modification of the circuit of FIG. 9, in which transistor N.sub.5, which can be seen as a controllable (adjustable) resistance, is replaced by an ohmic resistor R.sub.5. As a consequence, transistors N.sub.2 and N.sub.4, which basically drive the transistor N.sub.5 in a high ohmic state (when substrate voltage is low) or a low ohmic state (when substrate voltage is high), may be omitted. The current mirror CM2 is identical with the previous example of FIG. 9, whose output transistor N3, provides a low ohmic connection to substrate (cathode terminal K) when the substrate voltage is low (i.e. at negative voltages). In this situation, the resistance provided by transistor N3 is lower than the resistor R.sub.5 and thus the voltage V.sub.PISO is pulled towards the substrate voltage V.sub.SUBST instead of ground potential.
(49) Although various embodiments have been illustrated and described with respect to one or more specific implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the features and structures recited herein. With particular regard to the various functions performed by the above described components or structures (units, assemblies, devices, circuits, systems, etc.), the terms (including a reference to a means) used to describe such components are intended to correspondunless otherwise indicatedto any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the herein illustrated exemplary implementations of the present disclosure.
