Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity

Abstract

Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

Claims

1. A method of operation in a computational system, the computational system comprising a quantum processor comprising a plurality of qubits and one or more coupling devices arranged to form a working graph for embedding a problem graph, the computational system further comprising at least one non-quantum processor-based device, the method comprising: receiving a plurality of problems, each problem representable as a problem graph having a number of decision variables; selecting, from the plurality of problems, a first problem based on one of more properties of the first problem; selecting, from the plurality of problems, a second problem based on at least one of the one or more properties of the first problem and one or more properties of the second problem; determining, for each of the first and the second problems, a placement of the problem graph representing the problem in a placement graph; determining an executable representation of the placement graph together with the placements of the first and the second problems, the representation executable by the quantum processor in one or more executions; providing the executable representation to the quantum processor for execution; receiving, from the quantum processor, an output based on at least one execution of the executable representation by the quantum processor; and generating a first solution to the first problem and a second solution to the second problem by disaggregating representations of the first and the second solutions from the output.

2. The method of claim 1 further comprising determining, for each of the plurality of problems, the problem graph for the problem, the problem graph comprising a sub-graph representing the problem in the placement graph and wherein, for each of the first and the second problems, determining a placement of the problem graph comprises determining a placement of the sub-graph in the placement graph.

3. The method of claim 1 wherein selecting the second problem comprises generating a plurality of clusters of problems based on the one or more properties for each of the plurality of problems, selecting a cluster based on the one or more properties of the cluster's constituent problems, and selecting one or more of the cluster's constituent problems based on the one or more properties of at least one of the cluster's constituent problems.

4. The method of claim 1 wherein, for at least one of the first and the second problems, the one or more properties of the problem are selected from the group consisting of: a size of the problem, a temperature at which the problem is to be executed, a number of samples to be obtained from the problem, an annealing schedule of the problem, a position of the problem in a queue, and a priority of the problem.

5. The method of claim 1 wherein selecting the second problem comprises selecting a smallest problem from at least a subset of the plurality of problems.

6. The method of claim 1 further comprising iteratively selecting one or more further problems from at least a subset of the plurality of problems and determining a placement for each of the one or more further problems in the placement graph until at least one of: no more of the one or more further problems are placeable in the placement graph without removing an already-placed problem from the placement graph or placements have been determined for each problem in the at least a subset of problems.

7. The method of claim 6 wherein determining the placement of at least one of the one or more further problems comprises moving the placement of a previously-placed problem from a first region to a second region in the placement graph, wherein the placement of the at least one of the one or more further problems comprises at least part of the first region.

8. The method of claim 1 wherein generating the first and the second solutions comprises: dividing the output into a plurality of subgraphs, each subgraph corresponding to at least one of the plurality of problems and based on the placement of the corresponding problem's problem graph in the placement graph; and associating, for each problem graph, one or more output values of one or more of the plurality of qubits in a corresponding subgraph of the respective the problem graph with one or more vertices in the problem graph.

9. The method of claim 1 wherein the second problem is a variation of the first problem.

10. The method of claim 9 wherein the variation comprises a spin reversal transformation.

11. The method of claim 7 further comprising receiving a plurality of data values and a machine learning model, wherein the first problem comprises a first instantiation of the machine learning model with a first one of the plurality of data values and the second problem comprises a second instantiation of the machine learning model with a second one of the plurality of data values.

12. A computational system, comprising: at least one quantum processor comprising a plurality of qubits and one or more coupling devices arranged to form a working graph for embedding a problem graph; at least one non-quantum post-processing processor-based device; at least one processor-based controller communicatively coupled to the at least one quantum processor and the at least one non-quantum post-processing processor-based device, in operation the at least one processor-based controller: receives a plurality of problems, each problem representable as a problem graph having a number of decision variables; selects, from the plurality of problems, a first problem based on one of more properties of the first problem; selects, from the plurality of problems, a second problem based on at least one of the one or more properties of the first problem and one or more properties of the second problem; determines, for each of the first and the second problems, a placement of the problem graph representing the problem in a placement graph; determines an executable representation of the placement graph together with the placements of the first and the second problems, the representation executable by the quantum processor in one or more executions; provides the executable representation to the quantum processor for execution; receives, from the quantum processor, an output based on at least one execution of the executable representation by the quantum processor; and generates a first solution to the first problem and a second solution to the second problem by disaggregating representations of the first and the second solutions from the output.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the drawings.

(2) FIG. 1 is a processor hardware graph illustrating the interconnections realized between the qubits in an example quantum processor architecture, in accordance with the presently described systems, devices, articles, and methods.

(3) FIG. 2 is a processor working graph corresponding to the hardware graph of FIG. 1 and including inoperative computation devices and couplers.

(4) FIG. 3 is a schematic diagram of a C.sub.24 problem graph with a C.sub.12 subgraph which may be processed by a C.sub.12 quantum processor, in accordance with the presently described systems, devices, articles, and methods.

(5) FIG. 4 is a qubit graph illustrating a native K.sub.4,4 bipartite graph for a quantum processor, in accordance with the presently described systems, devices, articles, and methods.

(6) FIG. 5 is a qubit graph illustrating a K.sub.5,5 bipartite graph for a quantum processor, in accordance with the presently described systems, devices, articles, and methods.

(7) FIG. 6 is a qubit graph illustrating a modified K.sub.4,4 non-bipartite graph for a quantum processor, in accordance with the presently described systems, devices, articles, and methods.

(8) FIG. 7 is a schematic diagram of an initial working/hardware graph and an expanded working/hardware graph of a quantum processor, in accordance with the presently described systems, devices, articles, and methods.

(9) FIG. 8 is a flow diagram showing a method of operation in a computational system which includes modeling a problem on a full-yield hardware graph, performing the problem on a quantum processor, obtaining solutions from the quantum processor, filling holes, and performing a classical heuristic, in accordance with the presently described systems, devices, articles, and methods.

(10) FIG. 9 is a flow diagram showing a method of operation in a computational system which includes partitioning a problem graph into problem sub-graphs, performing the problem sub-graphs on a quantum processor, and performing a classical heuristic, in accordance with the presently described systems, devices, articles, and methods.

(11) FIG. 10 is a flow diagram showing a low-level method of operation in a computational system which includes receiving a problem graph, performing the problem on a quantum processor, and performing a classical heuristic, in accordance with the presently described systems, devices, articles, and methods.

(12) FIG. 11 is a block diagram illustrating elements of an example embodiment of a computational system, in accordance with the presently described systems, devices, articles, and methods.

(13) FIG. 12A is a flow diagram illustrating an example method of operation of a computational system such as the computational system of FIG. 11, in accordance with the present systems, devices, articles, and methods, according to at least one implementation.

(14) FIG. 12B is a flow diagram illustrating another example method of operation of a computational system such as the computational system of FIG. 11, which includes performing a classical post-processing technique to improve the results obtained from the sample mixing, in accordance with the present systems, devices, articles, and methods, according to at least one implementation.

(15) FIG. 13 is a block diagram of a hybrid computing system in accordance with the present systems, devices, articles, and methods, according to at least one implementation.

(16) FIG. 14 is a schematic diagram of a portion of an exemplary superconducting quantum processor designed for quantum annealing (and/or adiabatic quantum computing) components from which may be used to implement the present systems and devices.

(17) FIG. 15 is a schematic diagram of an embodiment of a system comprising two superconducting flux qubits and a ZX-coupler enabling ZX interactions therebetween.

(18) FIG. 16 is a flow diagram that shows an exemplary method for parallel computation using an analog processor.

(19) FIGS. 17A and 17B are schematic diagrams that show example placement graphs.

DETAILED DESCRIPTION

(20) In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one skilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and/or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

(21) Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprising” is synonymous with “including,” and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

(22) Reference throughout this specification to “one implementation” or “an implementation” means that a particular feature, structure or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases “in one implementation” or “in an implementation” in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

(23) As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the context clearly dictates otherwise.

(24) The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

(25) Graphical Descriptions for Analog Processors

(26) In at least some approaches to dealing with the constraints of at least some analog processors, the representation of the problem graph is selected so that it fits within the processor's working graph. That is, a problem graph G.sub.P, where vertices are variables and edges are interactions between variables, may be embedded in a logical graph G.sub.L where each vertex represents a logical computation device and each edge represents a tunable coupler coupling logical computation devices. Logical graph G.sub.L may be represented as an embedded topology defined within a working graph G.sub.W, which is the set of working computation devices and couplers on a hardware graph (or “design graph”), G.sub.H, of the analog processor. In at least some such approaches, this may be expressed as:
G.sub.P≤.sub.EG.sub.L≤.sub.ETG.sub.W≤.sub.CG.sub.H (1)
where E is an embedding method, ET is an embedded topology method, and C is a calibration method. For at least some problems, representing G.sub.P in a computable form on G.sub.W involves some overhead (which may comprise, e.g., the use of additional computation devices and/or couplers). In some circumstances, appropriate methods E, ET, and/or C may be selected to reduce this overhead, thereby expanding the scope of problems that may be solved on a given working graph G.sub.W. However, in such approaches, the scope of problem graphs G.sub.P which may be solved on a given analog processor is still constrained by the size, connectivity, and/or topology of the working graph G.sub.W of the processor. The relationship between problem graph, working graph, and hardware graph is further described in, for example, U.S. provisional patent application Ser. No. 61/983,370 filed 2014 Apr. 3. Further discussion of embedding and embedded topologies is provided in, for example, U.S. provisional patent application Ser. No. 62/114,406.

(27) FIGS. 1 and 2 show examples of systems and devices which may implement the present disclosure, including a partial hardware graph of a quantum processor (FIG. 1), and a corresponding partial working graph of a quantum processor (FIG. 2). FIG. 3 shows an example of problem graphs embedded on a working/hardware graphs.

(28) FIG. 1 shows a hardware graph 100 illustrating the interconnections realized between the qubits in an example quantum processor architecture. Graph 100 includes vertices (e.g., 104, only one called out to prevent clutter) and edges (e.g., 106, 108, only two called out to prevent clutter). As shown herein, each vertex is represented as a black dot and each vertex also corresponds to a qubit. Each diamond shaped sub-graph, for example 102a, is a unit cell (or sub-topology). Unit cells may comprise any suitable design, including a bi-partite graph of type and size K.sub.4,4 (i.e., a 4-by-4 unit cell). U.S. Pat. No. 8,421,053 and U.S. provisional patent application Ser. No. 62/114,406 describe example quantum processors with qubits laid out into an architecture of unit cells including bipartite graphs, such as K.sub.4,4, in greater detail.

(29) Only five unit cells 102a, 102b, 102c, 102d, and 102e are called out in FIG. 1 to reduce clutter. Each unit cell, such as 102a, 102b, 102c, 102d, and 102e, may represent a unit cell such as the unit cells from U.S. Pat. No. 8,421,053 and/or the like. The lines in FIG. 1 are potential couplings representing intra-cell couplers and inter-cell couplers that may be established between qubits in the same unit cell or adjacent unit cells, respectively. Intra-cell couplings (e.g., 106) are represented with diagonal lines with respect to an orientation of the view of the drawing sheet. Inter-cell couplings (e.g., 108) may be established between horizontally adjacent unit cells, and/or vertically adjacent unit cells and are represented with horizontal and vertical lines with respect to an orientation of the view of the drawing sheet. As illustrated, unit cell 102a is positioned immediately next to unit cell 102b in a horizontal direction with no other unit cells in between, thereby making unit cells 102a and 102b horizontally adjacent and nearest neighbors. Unit cell 102a positioned immediately next to unit cell 102e in a vertical direction with no other unit cells in between, thereby making unit cells 102b and 102c vertically adjacent and nearest neighbors. As shown in hardware graph 100, a unit cell may interact with four other unit cells placed horizontally adjacent, or vertically adjacent by inter-cell coupling, except for those unit cells located at the peripheries of hardware graph 100, which may have fewer adjacent unit cells. The inter-cell couplings marked by couplings 112 and couplings 114 represent further couplings to unit cells not included in FIG. 1.

(30) Those of skill in the art will appreciate that this assignment of vertical and horizontal directions is arbitrary, used as a convenient notation, and not intended to limit the scope of the present systems and devices in any way. It will also be appreciated that the arrangement of inter-cell couplings as horizontal and vertical lines and the intra-cell couplings as diagonal lines is a convention.

(31) FIG. 2 shows an example working graph 200 corresponding to the hardware graph 100 of FIG. 1. An example processor designed based on hardware graph 100 may comprise one or more qubits and/or couplers which are inoperative due to, for example, fabrication defects. Such qubits and/or couplers may be partially operable, in some implementations, but are rendered inoperative during a calibration process to avoid undesirable behavior during operation of the processor. For example, as depicted in FIG. 2, vertex 204a and edge 206a each correspond to an inoperative qubit and coupler, respectively. All other elements of working graph 200 correspond to the like-depicted elements of hardware graph 100. This reduced availability of qubits and/or couplers constrains the scope of problems which may be computed by the processor (relative to the scope of problems which could be computed by a processor implementing the full hardware graph 100 without any inoperative elements).

(32) An example hardware graph G.sub.H for a quantum processor may be based on a C.sub.12 Chimera graph containing 1152 vertices (qubits) and 3360 edges (couplers). A Chimera graph of size Cs is an s×s grid of chimera cells, each containing a complete bipartite graph on 8 vertices (a K.sub.4,4). Each vertex is connected to its four neighbors inside the cell as well as (for at least non-boundary vertices) two neighbors (north/south or east/west) outside the cell, for example. Thus, every vertex, excluding boundary vertices, has degree 6. Because the chip fabrication process leaves some small number (typically fewer than 5%) of qubits and couplers unusable, each processor has a specific working graph G.sub.W⊂C.sub.12. For instance, the working graph of an example C.sub.12-based processor with Chimera cells may have 1097 working qubits and 3045 working couplers out of the 1152 qubits and 3360 couplers defined by the C.sub.12 Chimera graph. Thus, some problems which are representable on a full C.sub.12 graph may not be representable on a particular processor with an imperfect working graph, and the set of such problems is likely to vary between processors (since each processor is likely to have different sets of unusable qubits and/or couplers).

(33) The systems and methods described herein for analog processing of problem graphs are not limited to Chimera graphs for the quantum processor, and may be implemented using suitable hardware graphs. Example hardware topologies are discussed in greater detail in, for example, U.S. Pat. Nos. 8,195,596, 8,063,657, 8,421,053, 8,772,759, 9,170,278, 9,178,154, and 9,183,508.

(34) In some instances, a problem may be represented by a problem graph which is larger than and/or has higher connectivity than the working and/or hardware graph of the processor. In some instances, even if the problem graph is not larger or more/differently connected than the quantum processor, the problem graph may be further represented by an embedding and/or embedded topologies which are larger and/or more highly connected than the working and/or hardware graph. Systems, methods, and articles for working such cases are discussed herein below with reference to FIGS. 3 through 15.

(35) Processing Highly-Connected Problem Graphs

(36) For the purposes of the present specification and the appended claims, a problem graph (and/or its representation) may be considered to be more highly connected than a processor's working and/or hardware graph if the computation of the problem graph (and/or its representation) requires the use of a coupler which the working/hardware graph does not provide. Such problem graphs (and/or their representations) do not necessarily have more edges than the processor has couplers, and their vertices are not necessarily higher-degree (i.e., the vertices do not necessarily have more edges than the processor's qubits have couplers). That is, “more highly connected than the processor” (or a graph of the processor) means “differently connected than the processor in a way which does not permit every connection to be encoded on the processor”. Since such mismatches between problem graphs and processors can generally be resolved by increasing the connectivity of the processor, it is convenient to include these problems within the definition of “more highly connected”.

(37) The inventors have observed, through experiment, that quantum processors tend to be good at quickly obtaining reasonably approximate solutions even when the complete problem cannot be mapped to the processor's working graph, whereas classical heuristic methods tend to struggle with such large-scale estimations. Conversely, classical heuristic methods tend to be good at computing “last-mile” optimizations (i.e., finding an improved solution based on a reasonable initial state), whereas quantum processors may have difficulty doing this when the problem graph is larger and/or has higher/different connectivity than the working graph of the quantum processor. Generally, the techniques discussed below are hybrid approaches which solve large parts of a problem using a quantum processor and refine the results classically (e.g., using a fat-tree algorithm and/or other classical heuristics).

(38) FIG. 3 is a schematic diagram of a sub-problem graph 300 represented (via an embedding) on a C.sub.24 hardware graph. Problem graph 300 is divided into subgraphs 302A-D, each of which may be processed by a C.sub.12 quantum processor. Such processing may be an iterative approach wherein the quantum processor processes multiple portions of the problem graph 300 separately and a classically-implemented postprocessing technique (e.g., a low-treewidth large neighborhood local search, aka “LTLNLS”, implementations of which are sometimes referred to as a “fat tree algorithm”) is used to improve the result, in particular to improve the results at the boundaries of the processor's working/hardware graph. In some implementations, the weights at the boundaries of the processor's working/hardware graph, indicated by dashed lines 304, may be set based on what is known of adjacent portions of the problem graph 300. The boundary areas 304 of the processor's working/hardware graph indicate areas of particular importance for refinement by the post-processing algorithm. In some implementations, the structure or logical topology of the problem subgraphs 302A-D and the processor's working/hardware graph are different.

(39) The technique described above may require multiple iterations. Generally, the quantum processor generates various patchwork results, followed by a classical heuristic to improve the overall graph, followed by further executions of the quantum processor based on the improved results, followed by the classical heuristic, etc. In some implementations, the classical technique may be performed first to provide an initial state. That is, the algorithm may begin with either quantum or classical processing, and may end with either quantum or classical processing.

(40) In some implementations, a problem may be computable with one iteration of the quantum processor rather than several iterations (each iteration may comprise one or more computations, e.g., depending on the results desired by the user).

(41) Processing Larger Problem Graphs

(42) FIGS. 4, 5 and 6 illustrate qubit graphs 400, 500 and 600, respectively, which allow for solving problems with problem graphs (and/or logical graphs) which are larger than the quantum processor's working/hardware graph. This technique involves using the processor's working and/or hardware graph as the basis for the problem graph, but allows the problem graph's representation to have added vertices and/or edges. The processor's working and/or hardware graph is thus a graph minor of the problem graph. If the number of vertices and edges added are small, this allows the quantum processor to generate a relatively good solution relatively quickly—in some circumstances, in one computation. A classical postprocessing technique (e.g., fat tree algorithm, other classical heuristic) can quickly improve the solution generated by the quantum processor. As used in this paragraph, the term “small” is based on the yield of the processor, the performance of the problem on the processor, and the performance of the classical heuristic, for example.

(43) For example, FIG. 4 is a qubit graph 400 illustrating a native K.sub.4,4 bipartite graph of the Chimera topology. The qubit graph 400 comprises qubits 402 and horizontal couplings 404. As shown in FIG. 5, rather than the K.sub.4,4 bipartite graph of the Chimera topology, a user may embed a problem on a K.sub.5,5 bipartite graph 500 which includes qubits 502 and couplings 504.

(44) The processor may execute using its native K.sub.4,4 graph, and a classical postprocessing technique may fairly quickly fill in the 20% of the qubits missing from the working/hardware graph. As another example, as shown in FIG. 6, the problem graph could be represented on a modified K.sub.4,4 graph 600 where additional couplings 602 are added between qubits 604 which are disconnected in the hardware and working graphs of the processor. Such additional couplings 602 (sometimes referred to as “vertical” couplings by the inventors) render the graph 600 non-bipartite, and thus may allow for the computation of more problems than are natively computable on the processor's K.sub.4,4 working and/or hardware graphs.

(45) Thus, using the techniques described herein, a user may interact with a problem graph with substantially-improved connectivity and/or an increased number of qubits relative to the actual working and/or hardware graph of a processor due to the quantum processor's ability to quickly get to a reasonably accurate approximation and the classical post-processing technique's ability to quickly perform “last-mile” optimization.

(46) In some circumstances, the classical and quantum portions of these computations may be performed in parallel, for example, when the results of one computation are not used as an initial state for the next computation. Such may potentially allow for the same total number of computations to be performed per unit time as if only quantum computations were performed.

(47) The aforementioned technique discussed with reference to FIGS. 4-26 may be considered to be a special case of the technique previously discussed with reference to FIG. 3. In particular, rather than representing the problem on any arbitrarily large and/or well-connected graph, this approach allows the user to embed the problem on a large and/or better-connected graph which shares the structure of the processor's working/hardware graph as a minor embedding. Such an approach may take advantage of the processor's native structure to improve results. Thus, where the problem graph (and/or its embedded representations) is larger than the working and/or hardware graph by a limited degree, this technique may allow for single-shot computation.

(48) Virtual Expansions of the Hardware Graph

(49) In some implementations, problems may be embedded on expanded versions of a processor's working and/or hardware graph. FIG. 7 is a schematic diagram 700 of an initial working and/or hardware graph 702 and an extended working and/or hardware graph 704 of a quantum processor. By retaining the structure of the working and/or hardware graph 702 as a subgraph of the larger extended graph 704 and (in some implementations) by limiting the degree of the extension, extended graph 704 may be able to solve a larger problem graph without substantially negatively impacting overall performance. In some embodiments, this technique involves adding an additional number of rows and/or columns of unit cells to the initial processor working/hardware graph 702.

(50) In some implementations, performance may be improved when the extended rows/columns are added around the boundary of the initial working and/or hardware graph 702. As shown in FIG. 7, the initial working and/or hardware graph 702 includes M rows of unit cells and N columns of unit cells, where M and N are positive integers. The extended working and/or hardware graph 704 includes M+A rows of unit cells and N+B columns of unit cells, where A and B are positive integers. In at least some implementations where an LTLNLS (e.g., “fat tree”) algorithm is used, this technique may work particularly well when the width of the added rows/columns is no greater than one treewidth. For instance, in an example treewidth-4 scenario, one row and one column of unit cells may be added, where each unit cell uses the Chimera topology discussed elsewhere herein.

(51) In some implementations, systems and methods described herein may enable the embedding of problems on an ideal hardware graph and may allow for the computation of such problems on an imperfect working graph (which is a graph minor the hardware graph). This may be done rather than (or in addition to) extending the working and/or hardware graph of the processor. FIG. 8 is a flow diagram showing a method 800 of operation in a computational system to embed a problem onto a “virtual full yield” quantum processor. As discussed above, a typical quantum processor's working graph may have a number of missing qubits and couplers due to the fabrication process. In the method 800, a problem graph is represented on an “as designed” or “ideal” hardware graph for a processor with 100% of its qubits and couplers operational. A benefit of this approach is that users may embed problems on an ideal graph even when the quantum processor does not provide such connectivity and, where missing elements are sparse, the results obtained after relatively quick classical post-processing tend to be quite accurate, particularly where inoperative qubits and/or couplers are sparsely distributed in the working graph.

(52) Virtual Full-Yield Hardware Graphs

(53) At 802, a problem may be modeled on the hardware graph (i.e., the “full yield” graph) of a quantum processor. At 804, the problem may be embedded onto the actual working graph of the quantum processor, which is a graph minor of the hardware graph. At 806, initial solutions to the problem are obtained from the quantum processor. Optionally, at 806, at least one processor-based controller of the computational system may execute a “fill holes heuristic” algorithm which specifically targets the missing qubits in the working graph to provide reasonable guesses for the values of the missing qubits based on the output of the quantum processor for surrounding, non-missing qubits. At 810, the results provided by the quantum processor at 804 (optionally, together with the guesses provided at 806) may be used as inputs to a classical post-processing classical operation which provides improved solutions.

(54) Processing Problems by Partitioning

(55) FIG. 9 shows a method 900 of operation in a computational system which includes partitioning a problem graph into problem sub-graphs, performing a computation based on the problem sub-graphs on a quantum processor, and performing a classical post-processing technique to improve the results obtained from the quantum processor.

(56) The method 900 starts at 902, for example, in response to submission of a problem or in response to an invocation by another routine. The method 900, or portions thereof, may be executed by one or more processor-based components, for example via one or more processor-based controllers of a job manager, which is communicatively coupled to one or more heuristic optimizers or solvers implemented via appropriate hardware circuitry (e.g., quantum processors, non-quantum processors). Such components and related systems and methods are described in greater detail in, for example, international patent application Serial No. PCT/US2015/046393, filed Aug. 21, 2015.

(57) At 904, at least one processor-based controller receives a representation of a problem graph for a problem which is to be solved. As discussed above, the problem graph may be larger and/or may have higher (or different) connectivity than a working and/or hardware graph of a quantum processor of the computational system. Additionally, the at least one processor-based controller may cause execution of at least one pre-processing operation on the problem, prior to submitting the problem to one or more solvers (e.g., heuristic optimizers). Such may, for example, include checking or confirming that a submitted problem is of a format which is suitable or acceptable for various solvers executable via the system. Additionally, or alternatively such may, for example, include generating one or more representations of the submitted problem.

(58) At 906, the at least one processor-based controller partitions the representation of the problem graph into multiple sub-graphs. At 908, the at least one processor-based controller may embed each of the sub-graphs onto a working graph of a quantum processor. For example, a problem graph represented on a C.sub.24 graph may be partitioned into four sub-graphs which are each embeddable on a hardware graph of a C.sub.12 quantum processor. As discussed above, for each of the sub-problem graphs, the at least one processor-based controller may set the weights at the boundary of the working/hardware graph based at least in part on known information regarding sub-problem graphs which are adjacent the sub-problem graph which is being embedded.

(59) As an example, one or more quantum processors may be selected from a variety of different types of quantum processors, for instance one or more superconducting quantum processors designed for AQC and/or quantum annealing.

(60) At 910, the at least one processor-based controller causes the quantum processor to generate one or more samples or solutions for each of the sub-problem graphs. At 912, at least one processor-based controller receives results of or samples from the quantum processor and causes an execution of at least one post-processing operation (e.g., a low-treewidth large neighborhood local search algorithm) on the respective samples via the at least one post-processing non-quantum processor-based device. For example, the post-processing may be executed via one or more non-quantum processors. The non-quantum processors may be selected from at least one of microprocessors, digital signal processors (DSPs), graphical processing units (GPUs), and/or field programmable gate arrays (FPGAs). For instance, a heuristic optimizer may be executed by one or more microprocessors, for instance in parallel by two or more microprocessors. Also for instance, a heuristic optimizer may be executed by one or more DSPs, for instance in parallel by two or more DSPs. Also for instance, a heuristic optimizer may be executed by one or more GPUS, for instance in parallel by two or more GPUs. Also for instance, a heuristic optimizer may be executed by one or more FPGAs, for instance in parallel by two or more FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more microprocessors and one or more DSPs, GPUs and/or FPGAs, for instance in parallel by the microprocessors and the DSPs, GPUs and/or FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more DSPs and one or more GPUs and/or FPGAs, for instance in parallel by the DSPs and the GPUs and/or FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more GPUs, one or more FPGAs, for instance in parallel by the GPUs and FPGAs. Any other combination or permutation of non-quantum processors may be employed which are suitable for the particular problem to be solved and the heuristic optimizer to be employed.

(61) Any suitable post-processing operation(s) may be used. The post-processing operation(s) may, for example include one or more of: low-treewidth large neighborhood local search (e.g., “fat tree”) operation, a majority voting post-processing operation, a greedy descent post-processing operation, a variable clamping post-processing operation, a variable branching post-processing operation, or a local field voting post-processing operation, via at least one digital processor executing corresponding instructions or software modules. These and other post-processing operations are discussed in greater detail in, for example, international patent application Serial No. PCT/US2015/046393, filed Aug. 21, 2015.

(62) At 914, at least one processor-based controller determines whether to further process the problem based at least in part on the results of the post-processing. For example, the at least one processor-based controller may determine whether an end condition has been satisfied. In some implementations where method 900 is configured to process the problem in one iteration, 914 is omitted and method 900 proceeds to 916.

(63) If the end condition has been determined to have been satisfied (or if 914 is omitted), control passes to 916 where the method 900 may terminate.

(64) If the end condition has been determined not to have been satisfied, the at least one processor-based controller may cause the quantum processor and or the non-quantum processor-based device to iteratively execute to further improve the results. The at least one processor-based controller may return the modified problem to the same heuristic optimizer(s) used in a previous iteration. Alternatively, the at least one processor-based controller of the computational system may, for example, switch between different ones of the heuristic optimizers between various iterations performed on the problem. For instance, the at least one processor-based controller of the computational system may cause a first one of the heuristic optimizers to optimize the respective problem and a second one of the heuristic optimizers to optimize the modified or intermediate problem, wherein the second one of the heuristic optimizers is different than the first one of the heuristic optimizers.

(65) The operations of the method 900 may be repeated one or more times, iteratively modifying the problem and performing optimization on the modified problem until an end condition is reached or satisfied.

(66) Processing Problems with Different Connectivity than the Hardware Graph

(67) FIG. 10 shows a method 1000 of operation in a computational system. The method 1000 starts at 1002, for example, in response to submission of a problem or in response to an invocation by another routine. The method 1000, or portions thereof, may be executed by one or more processor-based components, for example via one or more processor-based controllers of a job manager, which is communicatively coupled to one or more heuristic optimizers or solvers implemented via appropriate hardware circuitry (e.g., quantum processors, non-quantum processors). Such components and related systems and methods are described in greater detail in, for example, international patent application Serial No. PCT/US2015/046393, filed Aug. 21, 2015.

(68) At 1004, at least one processor-based controller receives a representation of a problem graph for a problem which is to be solved. As discussed above, the representation of the problem graph may be at least one of: larger than the working graph of a quantum processor, higher connectivity than the working graph, and/or may have different connectivity than the working graph (e.g., where the problem graph comprises an edge between vertices which correspond to qubits that do not share a coupler in the working graph). Additionally, the at least one processor-based controller may cause execution of at least one pre-processing operation on the problem, prior to submitting the problem to one or more solvers (e.g., heuristic optimizers). Such may, for example, include checking or confirming that a submitted problem is of a format which is suitable or acceptable for various solvers executable via the system. Additionally, or alternatively such may, for example, include generating one or more representations of the submitted problem.

(69) At 1006, the at least one processor-based controller may embed a portion of the relatively larger representation of problem graph onto the working graph of a quantum processor. For example, a K.sub.5,5 problem graph may embedded onto a K.sub.4,4 bipartite working graph of the quantum processor.

(70) At 1008, the at least one processor-based controller causes the quantum processor to generate one or more solution samples. At 1010, at least one processor-based controller receives results of the samples from the quantum processor and causes an execution of at least one post-processing operation (e.g., a low-treewidth large neighborhood local search algorithm) on the respective samples via the at least one post-processing non-quantum processor-based device.

(71) As discussed above, any suitable post-processing operation(s) may be used. The post-processing operation(s) may, for example include one or more of: low-treewidth large neighborhood local search algorithm operation, a majority voting post-processing operation, a greedy descent post-processing operation, a variable clamping post-processing operation, a variable branching post-processing operation, or a local field voting post-processing operation, via at least one digital processor executing corresponding instructions or software modules.

(72) At 1012, at least one processor-based controller determines whether to further process the problem based at least in part on the results of the post-processing. For example, the at least one processor-based controller may determine whether an end condition has been satisfied. In some implementations where method 1000 is configured to process the problem in one iteration, 1012 is omitted and method 1000 proceeds to 1014.

(73) If the end condition has been determined to have been satisfied (or if 1012 is omitted), control passes to 1014 where the method 1000 may terminate.

(74) If the end condition has been determined not to have been satisfied, the at least one processor-based controller may cause the quantum processor and or the non-quantum processor-based device to iteratively execute to further improve the results. The at least one processor-based controller may return the modified problem to the same heuristic optimizer(s) used in a previous iteration. Alternatively, the at least one processor-based controller of the computational system may, for example, switch between different ones of the heuristic optimizers between various iterations performed on the problem. For instance, the at least one processor-based controller of the computational system may cause a first one of the heuristic optimizers to optimize the respective problem and a second one of the heuristic optimizers to optimize the modified or intermediate problem, wherein the second one of the heuristic optimizers is different than the first one of the heuristic optimizers.

(75) The operations of the method 1000 may be repeated one or more times, iteratively modifying the problem and performing optimization on the modified problem until an end condition is reached or satisfied.

(76) Partitioning Problems

(77) As described above in relation to FIG. 3, a sub problem graph (such as sub-problem graph 300 of FIG. 3) may be generated by partitioning a problem graph into two or more sub-problem graphs, one of which may be embeddable onto the hardware graph of an analog processor such as a quantum processor. In some implementations, the problem graph may be partitioned, and a portion of the problem graph may be embedded onto a hardware graph of the analog processor.

(78) The technology described in the present application comprises systems and methods for blended or hybrid computation suitable, for example, for processing of problem graphs larger than the working graph of an analog processor. In one embodiment, the hybrid approach reflects at least in part the general structure of simulated annealing with parallel tempering, and uses analog processing hardware to suggest assignments for portions of the decision variables.

(79) The hybrid approach described in the present application partitions the graph underlying the problem Hamiltonian into two parts. The first part can be embedded in the hardware of the analog processor. Typically, the first part of the problem Hamiltonian is significantly smaller than the second part.

(80) In general terms, variables V can be partitioned into partitions U and W. The problem Hamiltonian:

(81) $H (x) = \underset{v \in V}{.Math.} h_{v} x_{v} + \underset{v \in V}{.Math.} \underset{u \in V}{.Math.} J_{u, v} x_{u} x_{v}$
can be expressed as a sum of three Hamiltonians, as follows:
H(x)=H.sub.U(x.sub.U)+H.sub.W(x.sub.W)+H.sub.UW(x)
where

(82) $H_{U} (x_{U}) = \underset{v \in U}{.Math.} h_{v} x_{v} + \underset{v \in U}{.Math.} \underset{u \in U}{.Math.} J_{u, v} x_{u} x_{v}$ $H_{W} (x_{W}) = \underset{v \in W}{.Math.} h_{v} x_{v} + \underset{v \in W}{.Math.} \underset{u \in W}{.Math.} J_{u, v} x_{u} x_{v}$
and

(83) $H_{UW} (x) = \underset{u \in U}{.Math.} \underset{v \in W}{.Math.} J_{u, v} x_{u} x_{v}$

(84) The partition (U, W) can be chosen such that

(85) $ε_{UW} = \underset{u \in U}{.Math.} \underset{v \in W}{.Math.} .Math. J_{u, v} .Math.$
is small. In terms of the underlying graph, it can be desirable that the weighted edge cut (where weights are replaced by their absolute values) induced by the partition (U,W) is small.

(86) FIG. 11 is a block diagram illustrating elements of an example embodiment of a computational system 1100, in accordance with the presently described systems, devices, articles, and methods. Computational system 1100 comprises partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and a sample mixer 1140. Partition generator 1110 can generate a partition of the variables into two or more subsets of variables. One or more classical solvers 1120 and/or one or more quantum solvers 1130 can generate partial samples. Sample mixer can mix partial samples from the one or more classical solvers 1120 and/or one or more quantum solvers 1130 to generate complete samples.

(87) In one implementation, partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and a sample mixer 1140 are run concurrently with one another. For example, in parallel operation, computational system 1100 can generate a partition, run classical and/or quantum solvers, and mix partial samples to complete samples at the same time. Parallel operation of partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and sample mixer 1140 can increase efficiency.

(88) In another implementation, partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and sample mixer 1140 are run sequentially. For example, in sequential operation, computational system 1100 may first generate a partition, and then run the one or more classical and/or quantum solvers in parallel, and finally mix the partial samples to generate complete samples.

(89) In yet another implementation, partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and a sample mixer 1140 are run using a suitable combination of sequential and parallel operation.

(90) Computational system 1100 further comprises a datastore, for example a database 1150. Partition generator 1110, one or more classical solvers 1120, one or more quantum solvers 1130, and a sample mixer 1140 can communicate through the datastore, e.g., database 1150. The datastore, e.g., database 1150 can store partitions, partial samples associated with partitions, and/or complete samples. A partial sample associated with a partition (U,W) is a set of spins x.sub.U or x.sub.W corresponding to the variables in one component or the other. Partial samples and complete samples are associated with temperatures. Classical solvers accept temperature as a parameter, and quantum solvers can simulate operation at various temperatures by scaling the Hamiltonian by a constant multiple.

(91) Typically, partition generator 1110 can generate more partitions than will be used by the solvers. Computational system 1100 can select a partition from the partitions generator by partition generator 1110. Partitions can be ranked according to the size of W (larger is better) and ε.sub.UW (smaller is better), and dissimilarity from previously chosen partitions. For example, the dissimilarity between (U.sub.1, W.sub.1) and (U.sub.2, W.sub.2) could be defined as the average graph distance between variables in W.sub.1 and W.sub.2.

(92) Computational system 1100 can place a determined bound on the number of partitions to store. When the bound is reached, computational system 1100 can discard (i.e., deleted from the database) a partition and the partial samples associated with it.

(93) In one implementation, computational system 1100 further comprises optional post-processing element 1145. Post-processing element 1145 is operable to perform one or more post-processing operations on the complete samples. Post-processing element 1145 can run concurrently or in sequence with partition generator 1110, classical solvers 1120, quantum solvers 1130, and sample mixer 1140. A method of operation of computational system 1100 comprising one or post-processing operations is described below with reference to FIG. 12B.

(94) FIG. 12A is a flow chart illustrating an example method of operation 1200a of a computational system such as computational system 1100 of FIG. 11. In some implementations, the computational system comprises a quantum processor comprising a plurality of qubits and one or more coupling devices arranged to form a working graph for embedding a problem graph. The computational system can further comprise at least one non-quantum processor-based device.

(95) The method 1200a starts at 1205, for example, in response to submission of a problem or in response to an invocation by another routine. The method 1200a, or portions thereof, may be executed by one or more processor-based components, for example via one or more processor-based controllers of a job manager, which is communicatively coupled to one or more quantum processors and/or non-quantum processor-based devices.

(96) At 1210, the computational system receives a problem represented as a problem graph having a number of decision variables. In one example, the problem graph is either larger than the working graph or has a connectivity that is higher than a connectivity of the working graph, or both.

(97) At 1220, the computational system partitions the problem graph into two sub-problem graphs, a first sub-problem graph and a second sub-problem graph. Typically, the first sub-problem graph is embeddable onto the working graph of the one or more quantum processors.

(98) At 1230, one or more classical solvers running on at least one non-quantum processor-based device generate a set of classically-generated partial samples. The classically-generated partial samples can be stored in a datastore such as database 1150 of FIG. 11.

(99) At 12110, the computational system embeds the first sub-problem graph onto the working graph of a quantum processor. Embedding the first sub-problem graph onto the working graph of the quantum processor can include setting a contribution of weights to a qubit bias at a boundary of the first sub-problem graph. The quantum processor can generate a set of quantum-generated partial samples. The quantum-generated partial samples can be stored in a datastore such as database 1150 of FIG. 11.

(100) The computational system can run the classical and quantum solvers in parallel or in sequence, or in a suitable combination of parallel and sequential operation.

(101) At 1250, the computational system can perform a sample mixing operation on the classically-generated and the quantum-generated partial samples to generate complete samples. The sample mixing operation can include reading partial samples from the datastore. The complete samples can be written to a datastore. The datastore can be the same or different than the datastore used to store the partial samples. The sample mixing operation can be initiated and/or controlled by at least one controller in the computational system.

(102) At 1260, if the end condition has been determined to have been satisfied, control passes to 1265 where method 1200a may terminate. If the end condition has been determined not to have been satisfied, control returns to 1220, and method 1200a performs another iteration. Acts 1220, 1230, 1240, 1245, and 1250 of method 1200a may be repeated one or more times, until the end condition is reached or satisfied.

(103) The classical and quantum solvers can operate in several modes. In one mode of operation of the classical and quantum solvers, the Hamiltonian H.sub.UW(x) is ignored. Embedding the sub-problem graph onto the graph includes setting a contribution of weights to a qubit bias at the boundary of the sub-problem to zero. Samples are generated for a range of temperatures. This mode is known as an “unbounded” mode.

(104) In another mode of operation, the spins in either U (in the case of a quantum solver) or W (in the case of a classical solver) are fixed with the spins from a partial sample associated with the partition (U,W) or with spins from a complete sample. The solver uses one of the augmented Hamiltonians:
H.sub.W+αH.sub.UW(x.sub.U)
or
H.sub.U+αH.sub.UW(x.sub.W)
with α=1. This mode is known as a “bounded” mode.

(105) The unbounded mode can be useful at the beginning, and immediately after a partition is chosen. Partial samples found in an unbounded mode for a partition can be used to seed a round of bounded mode for the same partition. In this approach, samples can be selected as seeds with a variety of temperatures, and the solver can be operated at the sample temperature. Optionally, in this approach, complete samples can take the place of partial samples. The sample mixer can be bypassed when the partial samples are generated by a classical or a quantum solver operating in bounded mode and where the result is a complete set of spins.

(106) In another mode of operation, one or more samples are averaged, and the corresponding augmented Hamiltonian can take 0≤α≤1. This mode is known as a “soft-bounded” mode. In this mode of operation of the solvers, seeds used to initialize the solvers can have the same temperature as each other, and the solver can operate at that temperature. When there are more than a determined number of partial samples associated with a particular component of a particular partition and a particular temperature, the solvers can stop.

(107) In yet another mode of operation (known as a back or reverse anneal mode), qubits in the quantum processor are prepared in a particular seed state, and the annealing schedule is run backwards for a selected time tp, known as an annealing offset. The annealing schedule is then run forwards from the annealing offset. The annealing offset can be configured during operation of computational system 400 of FIG. 4.

(108) In one implementation, the sample mixer monitors the datastore for the appearance of a new partial solution. When a new partial solution appears, the sample mixer combines the new partial solution with other partial solutions at the same temperature, or similar temperatures. The resulting complete samples are inserted into the datastore with probability P(E.sub.x, E.sub.T, T) where E.sub.X is the Hamiltonian energy of a sample x, E.sub.T is the mean Hamiltonian energy of samples at the sample temperature T, and P is a probability function. For example, the probability function can be:
P(E.sub.x,E.sub.T,T)=1 if E.sub.x<E.sub.T,else P(E.sub.x,E.sub.T,T)=e.sup.−(E.sup.x.sup.−E.sup.T.sup.)T

(109) When there are more than a determined number of complete samples at a particular temperature, a portion of the highest-energy samples can be distributed to higher temperature levels T′ with probability P(E.sub.x, E.sub.T, T′). Samples can be discarded if they fail to be inserted at the highest temperature level. Similarly, a portion of the lowest-energy samples can be distributed to lower temperature levels, starting at the lowest energy level and rising until T′=T, at which point the sample can be discarded.

(110) In another implementation, a global annealing schedule can be used, in which the temperature of samples is adjusted according to an annealing schedule. For example, each stage of the annealing schedule can be triggered after a certain number of partitions have been generated. In some implementations, the temperature of samples is lowered according to an annealing schedule.

(111) In one implementation, the approach comprises embedding the problem on a suitably sized Chimera graph (for example a C.sub.m graph), and using a “window” of the embedding (for example a C.sub.n subgraph of the C.sub.m graph) as a partition.

(112) FIG. 12B is a flow diagram illustrating another example method of operation 1200b of a computational system such as computational system 400 of FIG. 4, which includes performing a classical post-processing technique to improve the results obtained from the sample mixing, in accordance with the present systems, devices, articles, and methods, according to at least one implementation.

(113) Method 1200b starts at 1205, for example, in response to submission of a problem or in response to an invocation by another routine. Method 1200b, or portions thereof, may be executed by one or more processor-based components, for example via one or more processor-based controllers of a job manager, which is communicatively coupled to one or more quantum processors and/or non-quantum processor-based devices.

(114) At 1210, the computational system receives a problem represented as a problem graph having a number of decision variables. In one example, the problem graph is either larger than the working graph or has a connectivity that is higher than a connectivity of the working graph, or both.

(115) At 1220, the computational system partitions the problem graph into two sub-problem graphs, a first sub-problem graph and a second sub-problem graph. Typically, the first sub-problem graph is embeddable onto the working graph of the one or more quantum processors.

(116) At 1230, one or more classical solvers running on at least one non-quantum processor-based device generate a set of classically-generated partial samples. The classically-generated partial samples can be stored in a datastore, for example a database such as database 450 of FIG. 4.

(117) At 1240, the computational system embeds the first sub-problem graph onto the working graph of a quantum processor. Embedding the first sub-problem graph onto the working graph of the quantum processor can include setting a contribution of weights to a qubit bias at a boundary of the first sub-problem graph. The quantum processor can generate a set of quantum-generated partial samples. The quantum-generated partial samples can be stored in a datastore for example a database such as database 450 of FIG. 4.

(118) The computational system can run the classical and quantum solvers in parallel or in sequence, or in a suitable combination of parallel and sequential operation.

(119) At 1250, the computational system can perform a sample mixing operation on the classically-generated and the quantum-generated partial samples to generate complete samples. The sample mixing operation can include reading partial samples from the datastore. The complete samples can be written to a datastore, for example a database. The datastore, e.g., database, can be the same or different than the datastore (e.g., database) used to store the partial samples. The sample mixing operation can be initiated and/or controlled by at least one controller in the computational system.

(120) At 1255, the computation system can perform a classical post-processing operation on the complete samples generated by the sample mixing operation at 1250. At least one processor-based controller causes an execution of at least one post-processing operation (e.g., a low-treewidth large neighborhood local search algorithm) on the respective complete samples via the at least one post-processing non-quantum processor-based device. The complete samples may be read from the datastore (e.g., database).

(121) The post-processing may be executed via one or more non-quantum processors, for example. The non-quantum processors may be selected from at least one of microprocessors, digital signal processors (DSPs), graphical processing units (GPUs), and/or field programmable gate arrays (FPGAs). For instance, a heuristic optimizer may be executed by one or more microprocessors, for instance in parallel by two or more microprocessors. Also for instance, a heuristic optimizer may be executed by one or more DSPs, for instance in parallel by two or more DSPs. Also for instance, a heuristic optimizer may be executed by one or more GPUs, for instance in parallel by two or more GPUs. Also for instance, a heuristic optimizer may be executed by one or more FPGAs, for instance in parallel by two or more FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more microprocessors and one or more DSPs, GPUs and/or FPGAs, for instance in parallel by the microprocessors and the DSPs, GPUs and/or FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more DSPs and one or more GPUs and/or FPGAs, for instance in parallel by the DSPs and the GPUs and/or FPGAs. Additionally or alternatively, heuristic optimizers may be executed by one or more GPUs, one or more FPGAs, for instance in parallel by the GPUs and FPGAs. Any other combination or permutation of non-quantum processors may be employed which are suitable for the particular problem to be solved and the heuristic optimizer to be employed.

(122) Any suitable post-processing operation(s) may be used. The post-processing operation(s) may, for example include one or more of: low-treewidth large neighborhood local search (e.g., “fat tree”) operation, a majority voting post-processing operation, a greedy descent post-processing operation, a variable clamping post-processing operation, a variable branching post-processing operation, or a local field voting post-processing operation, via at least one digital processor executing corresponding instructions or software modules. These and other post-processing operations are discussed in greater detail in, for example, international patent application Serial No. PCT/US2015/046393, filed Aug. 21, 2015.

(123) At 1260, if the end condition has been determined to have been satisfied, control passes to 1265 where method 1200b may terminate. If the end condition has been determined not to have been satisfied, control returns to 1220, and method 1200b performs another iteration. Acts 1220, 1230, 1240, 1245, 1250, and 1255 of method 1200b may be repeated one or more times, until the end condition is reached or satisfied. At least one processor-based controller determines whether to further process the problem based at least in part on the results of the post-processing. For example, the at least one processor-based controller may determine whether an end condition has been satisfied. In some implementations, method 1200b is configured to process the problem in one iteration, and method 1200b proceeds to 1265. If the end condition has been determined to have been satisfied, control passes to 1265 where the method 1200b may terminate.

(124) If the end condition has been determined not to have been satisfied, the at least one processor-based controller may cause the quantum processor and or the non-quantum processor-based device to iteratively execute to further improve the results. The operations of the method 1200b may be repeated one or more times, iteratively, until an end condition is reached or satisfied.

(125) The computational system can run the partitioning, the generation of partial samples by classical and/or quantum solvers, the sample mixing, and the post-processing operation(s) in parallel or in sequence, or in a suitable combination of parallel and sequential operation.

(126) Parallel Quantum Computation

(127) In some implementations, a plurality of problems are represented simultaneously on the hardware graph of an analog processor, thereby allowing for parallel computation of the problems. Alternatively, or in addition, some simultaneously-represented problems may be executed sequentially (e.g., by setting sequential annealing schedules for different problems), thereby allowing for execution of the problems without an intervening re-initialization of the analog processor. Either instance results in improvement in the efficiency of operation of the analog processor.

(128) There may be challenges to implementing such parallel computation on an analog processor. For example, different problems may be of different sizes (and/or connectivity), be executed at different physical temperatures, have different annealing schedules (e.g., some problems may execute in 1 ms, whereas others might execute in 20 ms—twenty times longer!), be executed a different number of times (e.g., to produce a particular number of samples), and/or have other distinguishing characteristics which may pose obstacles to efficient parallel computation. Such obstacles may be particularly pronounced for analog processors that have fixed/limited size (and/or connectivity), require significant time to change temperatures, and/or require significant preprocessing (and/or initialization) to embed and execute a new problem graph.

(129) FIG. 16 shows an exemplary method 1600 for parallel computation using an analog processor, such as a quantum processor. The method involves executing at least a subset of problems in problem queue 1602. Problems in Zproblem queue 1602 may be provided by a user and/or may be generated by a computing system; for example, problem queue 1602 may comprise sub-problems generated by partitioning (e.g., as described above). The problems may comprise any suitable problem representation; for example, the problems may comprise quadratic unconstrained binary optimization problems (aka “QUBOs”), graphical representations (e.g., a problem graph or an embedded graph), and/or other representations. Graphical representations may be represented on a virtual graph (e.g., on full-yield, enlarged, and/or higher-connectivity virtualizations of a hardware graph and/or a subset thereof, as described above) and/or as embedded problems in a hardware graph of the analog processor.

(130) The term “queue” here is used for convenience and is not used to imply any particular data structure—queue 1602 may comprise (for example) a FIFO queue, a heap, an array, and/or any other suitable representation of the problems. Queue 1602 may be maintained by the same and/or a different computing system as the system performing method 1600. The problems of queue 1602 may be submitted by one or more users at one or more times across one or more submissions.

(131) In some implementations, queue 1602 is generated at 1605 by receiving a set of problems and, for each problem, finding a subgraph of the analog processor's hardware graph (and/or of the placement graph, defined below) that can contain the problem. Act 1605 may comprise optimizing to find the smallest such subgraph (and/or an approximation thereof). The graphical representation of the problem may then be added to the queue 1602 (e.g., to the back of a FIFO queue 1602).

(132) The problems of queue 1602 are associated with properties 1604. These properties may be predetermined (e.g., by a queue manager when problems are submitted to queue 1602) and/or may optionally be determined at 1610. Properties 1604 for a given problem in queue 1602 may comprise a size of the problem (e.g., a number of edges, a number of vertices, and/or a diameter of a problem graph), a temperature at which the problem is to be computed (e.g., 0.01° K), a number of samples to produce from the problem, an annealing schedule for the problem (if the analog processor implements annealing), a position of the problem in queue 1602, and/or a priority of the problem.

(133) At 1615, the computing system selects a plurality of problems for parallel computation from queue 1602. In some implementations, selecting a plurality of problems comprises selecting a first problem (e.g., by selecting the frontmost element of queue 1602, by selecting a highest-priority element of queue 1602, by selecting an element with an associated temperature nearest to the current temperature, and/or some combination of these and/or other factors) and querying the queue for other problems with complementary properties 1604. For example, in some implementations the computing system selects the frontmost problem of queue 1602 which satisfies certain selection criteria based on properties 1604, e.g., problems having the same temperature, overall annealing time, and/or number of samples as the first-selected problem. In some implementations, the computing system may greedily select the smallest (and not necessarily frontmost) problem which satisfies the selection criteria.

(134) The selection of act 1615 may be iteratively repeated to select further elements of plurality of selected problems. On subsequent iterations the selection may further be restricted to problems having a size which is small enough to be accommodated by the remaining space of the hardware graph (and/or a virtual graph extending the hardware graph) after placing the previously-selected problems. The selection of 1615 may be repeated until no other problems in queue 1602 are eligible for selection (e.g., because none are small enough to fit into the remaining space of the hardware or virtual graph).

(135) In some implementations, act 1615 comprises generating problem clusters from the problems of queue 1602, for example using a clustering algorithm, such as (for example) K-means, fuzzy C-means, hierarchical clustering, mixture of Gaussians, and/or any other suitable clustering algorithm. Clusters may be determined based on a distance metric defined over at least a subset of the properties; for instance, for a given pair of problems, the distance metric may be based on a difference between the problems' overall annealing times, temperatures, sizes, priorities, and/or number of samples. In some implementations, one or more properties, such as temperature, may act as partitioning functions so that each cluster contains only problems with the same value for those properties.

(136) Once clusters have been identified, a cluster may be selected to form the plurality of selected problems for parallel computation based on the properties of one or more of its constituent problems. For example, a cluster may be selected based on containing the frontmost problem (and/or highest-priority problem) of queue 1602 may be selected, the cluster having the highest mean priority may be selected, a cluster having a (mean) temperature closest to the current temperature of the analog processor may be selected, and/or based on other characteristics of the cluster (e.g., based on other properties of problems in the cluster). The clustering algorithm may be repeated when all clustered problems have been executed, each time a problem is added to queue 1602, each time a cluster is exhausted, prior to each execution by the analog processor, and/or at any other suitable time. In some implementations, clusters are updated when new problems are added to queue 1602 (e.g., by adding the new problems to the nearest previously-identified clusters) without necessarily reiterating the clustering algorithm.

(137) Act 1615 may be interleaved (or otherwise executed alternately and/or in parallel) with determination of problem placement 1620, where selected problems are placed on a hardware graph of the analog processor and/or a virtual graph extending the hardware graph (e.g., such as an enlarger, higher-connectivity, or other graph, such as those as described above). Without loss of generality, this graph will be referred to herein as a “placement graph”. While space remains for problems to be added, each selected problem may be placed in a region of the placement graph which is unoccupied by other problems. In implementations where 1616 does not precisely determine whether a problem will fit in the placement graph after adding previously-selected problems, determination of problem placement 1620 may comprise rejecting problems which will not fit and replacing them in queue 1602 (e.g., at the front). For example, if clustering was used to select the plurality of problems, the problems may be selected for placement from within the cluster based on some criteria (e.g., the criteria for iterative selection of individual problems described above).

(138) In some implementations, placement of a problem 1620 involves moving a previously-placed problem to a different region and placing the currently-selected problem into at least part of the vacated space. In implementations where the placement graph has a regular topology (e.g., a Chimera graph), such placement may involve taking a Chimera-structured representation of the problem being placed and shifting it to an empty region of the appropriate size. The selection of a region may be done greedily, heuristically, and/or via any other approach.

(139) In some implementations, the computing system may place problems in the placement graph by executing a graph optimization algorithm, such as cliquer (see P. Ostergard, Cliquer—routines for clique searching, available at https://users.aalto.fi/˜pat/cliquer.html).

(140) FIGS. 17A and 17B (collectively and individually “FIG. 17”) show schematically example placement graphs 1700a and 1700b. Each of these example placement graphs comprises a “full-yield” Chimera graph 1702 having regularly-tiled, bipartite unit cells 1704 comprising qubits 1706 and couplers 1708. Graph 1702 may be virtual; for example, the corresponding hardware graph may be missing one or more qubits 1706 and couplers 1708. In placement graph 1700a, four problems are represented, each having a subgraph which fits inside a 2-unit-cell-by-2-unit-cell region 1710 (sometimes referred to as a “C2” subgraph). In placement graph 1700a, eight problems are represented, one having a subgraph which fits inside a 3-unit-cell-by-3-unit-cell region 1712 (sometimes referred to as a “C3” subgraph) and the other seven fitting inside 1-unit-cell regions (sometimes referred to as a “C1“subgraph”). These examples are non-limiting; in particular, placement graphs are not necessarily Chimera-structured, they are not necessarily virtual graphs, and the boundaries of regions 1710, 1712, 1714 do not necessarily need to fall along unit cell boundaries (i.e., different qubits in a unit cell may belong to different regions).

(141) Returning to FIG. 16, at 1625, the computing system submits the placement graph (including the problems placed thereon at 1620) to the analog processor. Where the placement graph is a subgraph of the hardware graph, this may be done by generating machine instructions corresponding to the values of the graph (i.e. the values of its vertices and edges). Where the placement graph is not a subgraph of the hardware graph (e.g. where it is a virtual graph corresponding to a full-yield virtualization of the hardware graph, an enlarged hardware graph, a highly-connected version of the hardware graph, and/or another virtual graph at least partially executable by the analog processor in one or more computations), it may be executed by any suitable methods, such as (but not limited to) methods described elsewhere herein for solving virtual graphs. Such execution may comprise postprocessing by a digital processor.

(142) At 1630, the results of the execution are communicated from the analog processor to a digital processor and disaggregated. Disaggregation may comprise, for example, reading the output of the analog processor, dividing the output into subgraphs which correspond to the problem subgraphs placed in the placement graph, and associating output values (e.g., spins) of hardware qubits (and, optionally, couplers) in each subgraph with their corresponding vertices (and, optionally, edges) in the corresponding problem subgraph, thereby providing a set of results 1608. Each subgraph of output values in results 1608 may then be treated as a result from an analog processor having the topology of the subgraph, without necessarily requiring any knowledge of the other problems represented on the same placement graph (or their associated results).

(143) In implementations where the placement graph is not itself a subgraph of the hardware graph, the output of the analog processor may be post-processed to generate a virtual output graph with vertices and edges that correspond to those of the placement graph prior to disaggregation.

(144) In some implementations, method 1600 comprises computing a one or more variations of a problem. Variations of a problem may include, for example, spin reversal transformations, modified annealing schedules, and/or other modifications or transformations of the problem. For instance, in some circumstances it is desirable to execute multiple variations of a problem (especially where the problem has an Ising/QUBO structure), with each variation being subject to a spin reversal transformation on or more qubits (see, for example, K. Pudenz, Parameter Setting for Quantum Annealers, arXiv:1711.07552v1 (November 2017)). As another example, in some circumstances it is desirable to execute a problem multiple times with different annealing schedules as part of determining an optimal (or near-optimal) annealing schedule. If the size of the problem is smaller than the size of the placement graph, method 1600 may comprise placing one or more variations of the same problem on the same graph, with each variation being subject to a spin reversal transformation, a modified annealing schedule, and/or some other modification or transformation.

(145) In suitable circumstances, this can provide a substantial speedup over implementations where each spin reversal transformation variation is computed using an independent execution of the analog processor. For example, if a user has requested that a problem represented by a C2 subgraph be subjected to 100 spin reversal transforms, then a C12-sized placement graph (i.e. a 12-unit-cell-by-12-unit-cell Chimera-structured graph) can fit 36 variations of the problem, thereby requiring only three executions to compute all 100 variations, rather than 100 executions.

(146) In some implementations, method 1600 comprises performing a mini-batching technique. Mini-batching is a technique used, for example, in machine learning algorithms faced with large-scale dataset, where the dataset is divided into small batches and parameters of the model are updated on a batch-by-batch basis. If the machine learning model is small enough to be represented multiple times on the placement graph, problem queue 1602 of method 1600 may comprise instantiations of the model, each instantiation using a data element from the dataset as input. For instance, each instantiation may comprise a restricted Boltzmann machine generated from a data element from the dataset using the model. A reduced number of executions (potentially as few as a single execution) may then be performed to generate one mini-batch. Alternatively, or in addition, problem queue 1602 may comprise different models to be trained in parallel (on the same or different data).

(147) Hybrid Computing Systems

(148) The present systems and methods may be implemented by, for example, a hybrid computing system comprising a digital computer (or any other non-analog computer as described elsewhere herein) coupled to a quantum computer. In some embodiments, the analog computer comprises a quantum computer comprising a quantum processor, and the quantum computer's computation devices comprise qubits. U.S. provisional patent application Ser. No. 62/114,406 describes example hybrid computing systems in greater detail. For the sake of convenience, the following disclosure refers generally to “qubits” and “quantum processors”, although those skilled in the art will appreciate that this disclosure may be implemented in systems comprising other analog processors.

(149) FIG. 13 is a block diagram of a hybrid computing system 1300 in accordance with the present systems, devices, articles, and methods, according to at least one implementation. Hybrid computing system 1300 comprises a digital computer 1305 coupled to an analog computer 1350. In some implementations, analog computer 1350 is a quantum computer and digital computer 1305 is a classical computer. The exemplary digital computer 1305 includes one or more digital processors (DP) 1310 that may be used to perform classical digital processing tasks described in the present systems and methods.

(150) Digital computer 1305 may include at least one system memory 1320, and at least one system bus 1317 that couples various system components, including system memory 1320 to digital processors 1310.

(151) Each of digital processors 1310 may be any logic processing unit, such as one or more central processing units (“CPUs”), graphics processing units (“GPUs”), digital signal processors (“DSPs”), application-specific integrated circuits (“ASICs”), field-programmable gate arrays (“FPGAs”), etc. Unless described otherwise, the construction and operation of the various blocks shown in FIG. 13 are of conventional design. As a result, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art.

(152) Digital computer 1305 may include a user input/output subsystem 1311. In some implementations, the user input/output subsystem includes one or more user input/output components such as a display 1312, mouse 1313, and/or keyboard 1314. System bus 1317 can employ any known bus structures or architectures, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 1320 may include non-volatile memory, such as read-only memory (“ROM”), static random access memory (“SRAM”), Flash NAND; and volatile memory such as random access memory (“RAM”) (not shown), all of which are examples of nontransitory computer- or processor-readable media. An basic input/output system (“BIOS”) 1321, which can form part of the ROM, contains basic routines that help transfer information between elements within digital computer 1305, such as during startup.

(153) Digital computer 1305 may also include other non-volatile memory 1315. Non-volatile memory 1315 may take a variety of forms, including: a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to removable optical disks, and/or a magnetic disk drive for reading from and writing to magnetic disks, all of which are examples of nontransitory computer- or processor-readable media. The optical disk can be a CD-ROM or DVD, while the magnetic disk can be a magnetic floppy disk or diskette. Non-volatile memory 1315 may communicate with digital processor via system bus 1317 and may include appropriate interfaces or controllers 1316 coupled to system bus 1317. Non-volatile memory 1315 may serve as long-term storage for computer- or processor-readable instructions, data structures, or other data (also called program modules) for digital computer 1305.

(154) Although digital computer 1305 has been described as employing hard disks, optical disks and/or magnetic disks, those skilled in the relevant art will appreciate that other types of non-volatile computer-readable media may be employed, such a magnetic cassettes, flash memory cards, Flash, ROMs, smart cards, etc., all of which are further examples of nontransitory computer- or processor-readable media. Those skilled in the relevant art will appreciate that some computer architectures conflate volatile memory and non-volatile memory. For example, data in volatile memory can be cached to non-volatile memory. Or a solid-state disk that employs integrated circuits to provide non-volatile memory. Some computers place data traditionally stored on disk in memory. As well, some media that are traditionally regarded as volatile can have a non-volatile form, e.g., Non-Volatile Dual In-line Memory Module variation of Dual In Line Memory Modules.

(155) Various sets of computer- or processor-readable instructions (also called program modules), application programs and/or data can be stored in system memory 1320.

(156) In the various implementations, system memory 1320 may store generative learning instructions. For example, generative learning instructions in system memory 1320 can implement the methods like those described in reference to FIGS. 1 through 12 on digital processors 1310 and/or analog computer 1350.

(157) In the various implementations, system memory 1320 may store runtime instructions to provide executable procedures and parameters to deploy and/or monitor generative learning methods.

(158) While shown in FIG. 13 as being stored in system memory 1320, the instructions and/or data described above can also be stored elsewhere including in non-volatile memory 1315 or one or more other non-transitory computer- or processor-readable media.

(159) Analog computer 1351 includes an analog processor 1340 such as a quantum processor. Quantum processor 1340 can include programmable elements such as qubits, couplers, and other devices. Quantum processor 1340 can include superconducting qubits.

(160) In various implementations, quantum processor 1340 performs quantum annealing and/or adiabatic quantum computation.

(161) FIG. 14 is a schematic diagram of a portion of an exemplary superconducting quantum processor 1400 designed for quantum annealing (and/or adiabatic quantum computing) components from which may be used to implement the present systems and devices. The portion of superconducting quantum processor 1400 shown in FIG. 14 includes two superconducting qubits 1401, and 1402. Also shown is a tunable coupling (diagonal coupling terms in the system Hamiltonian, for example between horizontally or vertically arrayed qubits 1401, 1402) via coupler 1410 between qubits 1401 and 1402 (i.e., providing 2-local interaction). While the portion of quantum processor 1400 shown in FIG. 14 includes only two qubits 1401, 1402 and one coupler 1410, those of skill in the art will appreciate that quantum processor 1400 may include any number of qubits and any number of couplers coupling information between them.

(162) The portion of quantum processor 1400 shown in FIG. 14 may be implemented to physically realize quantum annealing and/or adiabatic quantum computing. Quantum processor 1400 includes a plurality of interfaces 1421-1425 that are used to configure and control the state of quantum processor 1400. Each of interfaces 1421-1425 may be realized by a respective inductive coupling structure, as illustrated, as part of a programming subsystem and/or an evolution subsystem. Such a programming subsystem and/or evolution subsystem may be separate from quantum processor 1400, or it may be included locally (i.e., on-chip with quantum processor 1400).

(163) In the operation of quantum processor 1400, interfaces 1421 and 1424 may each be used to couple a flux signal into a respective compound Josephson junction 1431 and 1432 of qubits 1401 and 1402, thereby realizing a tunable tunneling term (the Δ.sub.i term) in the system Hamiltonian. This coupling provides the off-diagonal σ.sup.x terms of the Hamiltonian and these flux signals are examples of “delocalization signals”.

(164) In some implementations, the tunneling term is selected to make a first portion of the qubits on the quantum processor more classical relative a second portion of the qubits. For example, qubit 1401 may be a hidden unit in a Boltzmann machine and have a smaller tunneling term relative to qubit 1402.

(165) Similarly, interfaces 1422 and 1423 may each be used to apply a flux signal into a respective qubit loop of qubits 1401 and 1402, thereby realizing the h.sub.i terms in the system Hamiltonian. This coupling provides the diagonal σ.sup.z terms in the system Hamiltonian. Furthermore, interface 1425 may be used to couple a flux signal into coupler 1410, thereby realizing the J.sub.ij term(s) in the system Hamiltonian. This coupling provides the diagonal σ.sub.i.sup.zσ.sub.j.sup.z terms in the system Hamiltonian.

(166) In FIG. 14, the contribution of each of interfaces 1421-1425 to the system Hamiltonian is indicated in boxes 1421a-1425a, respectively. As shown, in the example of FIG. 14, the boxes 1421a-1425a are elements of time-varying Hamiltonians for quantum annealing and/or adiabatic quantum computing.

(167) Throughout this specification and the appended claims, the term “quantum processor” is used to generally describe a collection of physical qubits (e.g., qubits 1401 and 1402) and couplers (e.g., coupler 1410). The physical qubits 1401 and 1402 and the coupler 1410 are referred to as the “programmable elements” of the quantum processor 1400 and their corresponding parameters (e.g., the qubit h.sub.i values and the coupler J.sub.ij values) are referred to as the “programmable parameters” of the quantum processor. In the context of a quantum processor, the term “programming subsystem” is used to generally describe the interfaces (e.g., “programming interfaces” 1422, 1423, and 1425) used to apply the programmable parameters to the programmable elements of the quantum processor 1400 and other associated control circuitry and/or instructions.

(168) As previously described, the programming interfaces of the programming subsystem may communicate with other subsystems which may be separate from the quantum processor or may be included locally on the processor. As described in more detail later, the programming subsystem may be configured to receive programming instructions in a machine language of the quantum processor and execute the programming instructions to program the programmable elements in accordance with the programming instructions. Similarly, in the context of a quantum processor, the term “evolution subsystem” generally includes the interfaces (e.g., “evolution interfaces” 1421 and 1424) used to evolve the programmable elements of the quantum processor 1400 and other associated control circuitry and/or instructions. For example, the evolution subsystem may include annealing signal lines and their corresponding interfaces (1421, 1424) to the qubits (1401, 1402).

(169) Quantum processor 1400 also includes readout devices 1451 and 1452, where readout device 1451 is associated with qubit 1401 and readout device 1452 is associated with qubit 1402. In some embodiments, such as shown in FIG. 14, each of readout devices 1451 and 1452 includes a DC-SQUID inductively coupled to the corresponding qubit. In the context of quantum processor 1400, the term “readout subsystem” is used to generally describe the readout devices 1451, 1452 used to read out the final states of the qubits (e.g., qubits 1401 and 1402) in the quantum processor to produce a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latching elements, a shift register, or a multiplexer circuit) and/or may be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.). Qubit readout may also be performed using alternative circuits, such as that described in PCT Patent Publication WO2012064974.

(170) While FIG. 14 illustrates only two physical qubits 1401, 1402, one coupler 1410, and two readout devices 1451, 1452, a quantum processor (e.g., processor 1400) may employ any number of qubits, couplers, and/or readout devices, including a larger number (e.g., hundreds, thousands or more) of qubits, couplers and/or readout devices. The application of the teachings herein to processors with a different (e.g., larger) number of computational components should be readily apparent to those of ordinary skill in the art.

(171) FIG. 15 is a schematic diagram of an embodiment of a system 1500 comprising two superconducting flux qubits 1501, 1502 and a ZX-coupler 1505 enabling ZX interactions therebetween. Qubit 1501 is comprised of a qubit loop 1511 interrupted by a CJJ 1512, and qubit 1502 is similarly comprised of a qubit loop 1521 interrupted by a CJJ 1522. In the implementation shown in FIG. 15, ZX-coupler 1505 is formed by a closed loop of superconducting material that is inductively coupled to qubit 1501 by the exchange of flux 1531 with the qubit loop 1511 of qubit 1501. ZX-coupler 1505 is also inductively coupled to qubit 1502 by the exchange of flux 1532 with the CJJ 1522 of qubit 1502. ZX-coupler 1505 couples information between the persistent current in the qubit loop 1511 of qubit 1501 and the flux threading the CJJ 1522 of qubit 1502. If qubit 1501 is bistable, then the direction of persistent current flow in qubit loop 1511 may influence the magnitude of the tunneling rate in qubit 1502 by inductive coupling to CJJ 1522 of qubit 1502.

(172) In some implementations, ZX-coupler 1505 may include at least one magnetic flux inductor. In the illustrated implementation of FIG. 15, ZX-coupler 1505 includes two magnetic flux inductors 1541, 1542. Magnetic flux inductor 1541 is positioned proximate the qubit loop 1511 of qubit 1501 to establish a mutual inductance therebetween and realize the exchange of flux 1531. Magnetic flux inductor 1542 is positioned proximate the CJJ 1522 of qubit 1502 to establish a mutual inductance therebetween and realize the exchange of flux 1532. However, those of skill in the art will appreciate that the exchange of flux 1531 and 1532 may be realized, to some degree, without the inclusion of magnetic flux inductors 1541 and 1542. Whether or not magnetic flux inductors 1541 and 1542 are required depends on the magnitude of mutual inductance that is desired in the specific application of ZX-coupler 1505.

(173) ZX-coupler 1505 couples information between the Z-degree of freedom in qubit 1501 and the X-degree of freedom in qubit 1502. Thus, ZX-coupler 1505 provides ZX-coupling between qubits 1501 and 1502. In some embodiments, ZX-coupler 1505 may operate substantially unidirectionally such that information from the Z-degree of freedom in qubit 1501 influences the X-degree of freedom in qubit 1502 with little “back-coupling” from qubit 1502 to qubit 1501.

(174) Those of skill in the art will appreciate that the various components of system 1500 are not drawn to scale and, in particular, their shapes, relative proportions, and relative positions have been adjusted for clarity of illustration.

(175) In many applications, it is desirable to implement tunable coupling between qubits. In accordance with the present systems, methods and apparatus, the ZX-coupling principle taught in FIG. 15 is used to achieve tunable ZX-coupling by accordingly adapting ZX-coupler 1505.

(176) Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, and the like. In a superconducting flux qubit the Josephson energy dominates or is equal to the charging energy. In a charge qubit it is the reverse. Examples of flux qubits that may be used include rf-SQUIDs, which include a superconducting loop interrupted by one Josephson junction, persistent current qubits, which include a superconducting loop interrupted by three Josephson junctions, and the like.

(177) The qubits and coupling devices in a quantum processor may be arranged according to an architecture into a topology such that a certain number of qubits may be laid out in a sub-topology of qubits (hereinafter, “sub-topology”). A sub-topology is a portion of a quantum processor topology comprising qubits and coupling devices. A plurality of sub-topologies may be repeated or tiled (or otherwise directly communicatively coupled to one another) over an area of a quantum processor to produce a certain quantum processor topology.

(178) In some implementations, each sub-topology in a topology is identical to each other sub-topology in the same topology. In other implementations, one or more sub-topologies in the topology comprise a different configuration of qubits and coupling devices than another sub-topology in the same topology.

(179) In some circumstances, the classical and quantum portions of these computations may be performed in parallel, for example, when the results of one computation are not used as an initial state for the next computation. Such may potentially allow for the same total number of computations to be performed per unit time as if only quantum computations were performed.

(180) The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) method are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer or a system to program or otherwise control operation of an adiabatic quantum computer or a quantum annealer, for instance a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and/or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for exemplary purposes only and may change in alternative examples. Some of the exemplary acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

(181) The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the exemplary methods for quantum computation generally described above.

(182) The various implementations described above can be combined to provide further implementations. All of the commonly assigned US patent application publications, US patent applications, foreign patents, and foreign patent applications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to: U.S. Pat. No. 7,303,276; U.S. patent application Ser. No. 14/173,101, filed Feb. 5, 2014, now patent application publication no. 2014-0223224; International patent application Serial No. PCT/US2015/046393, filed Aug. 21, 2015; International patent application Serial No. PCT/US2016/015100, filed Jan. 27, 2016; International patent application Serial No. PCT/US2014/014836, filed Feb. 5, 2014, now WIPO publication number WO2014123980; U.S. patent application Ser. No. 14/339,289, filed Jul. 23, 2014, now US Patent Application Publication 2015-0032993; U.S. patent application Ser. No. 14/340,303, filed Jul. 24, 2014, now patent application publication no. 2015-0032994; U.S. provisional patent application Ser. No. 61/858,011, filed Jul. 24, 2013; U.S. provisional patent application Ser. No. 62/040,643, filed Aug. 22, 2014, titled: SYSTEMS AND METHODS FOR PROBLEM SOLVING VIA SOLVERS EMPLOYING PROBLEM MODIFICATION; U.S. provisional patent application Ser. No. 62/040,646, filed Aug. 22, 2014, titled: SYSTEMS AND METHODS FOR PROBLEM SOLVING VIA SOLVERS EMPLOYING POST-PROCESSING THAT OVERLAPS WITH PROCESSING; U.S. provisional patent application Ser. No. 62/040,661, filed Aug. 22, 2014, titled: SYSTEMS AND METHODS FOR PROBLEM SOLVING VIA SOLVERS EMPLOYING SELECTION OF HEURISTIC OPTIMIZER(S); U.S. provisional patent application Ser. No. 62/040,890, filed Aug. 22, 2014, titled: Systems and methods for improving the performance of a quantum processor by correcting to reduce intrinsic/control errors; and U.S. provisional patent application Ser. No. 62/048,043, filed Sep. 9, 2014, titled: Systems and Methods for Improving the Performance of a Quantum Processor via Reduced Readouts.

(183) These and other changes can be made to the implementations in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity

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